| ARMScheduleA8.td (208954) | ARMScheduleA8.td (210299) |
|---|---|
| 1//=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=// | 1//=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=// |
| 2// | 2// |
| 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. | 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. |
| 7// | 7// |
| 8//===----------------------------------------------------------------------===// 9// 10// This file defines the itinerary class data for the ARM Cortex A8 processors. 11// 12//===----------------------------------------------------------------------===// 13 14// 15// Scheduling information derived from "Cortex-A8 Technical Reference Manual". --- 11 unchanged lines hidden (view full) --- 27def CortexA8Itineraries : ProcessorItineraries< 28 [A8_Issue, A8_Pipe0, A8_Pipe1, A8_LdSt0, A8_LdSt1, A8_NPipe, A8_NLSPipe], [ 29 // Two fully-pipelined integer ALU pipelines 30 // 31 // No operand cycles 32 InstrItinData<IIC_iALUx , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>, 33 // 34 // Binary Instructions that produce a result | 8//===----------------------------------------------------------------------===// 9// 10// This file defines the itinerary class data for the ARM Cortex A8 processors. 11// 12//===----------------------------------------------------------------------===// 13 14// 15// Scheduling information derived from "Cortex-A8 Technical Reference Manual". --- 11 unchanged lines hidden (view full) --- 27def CortexA8Itineraries : ProcessorItineraries< 28 [A8_Issue, A8_Pipe0, A8_Pipe1, A8_LdSt0, A8_LdSt1, A8_NPipe, A8_NLSPipe], [ 29 // Two fully-pipelined integer ALU pipelines 30 // 31 // No operand cycles 32 InstrItinData<IIC_iALUx , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>, 33 // 34 // Binary Instructions that produce a result |
| 35 InstrItinData<IIC_iALUi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 36 InstrItinData<IIC_iALUr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>, 37 InstrItinData<IIC_iALUsi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>, 38 InstrItinData<IIC_iALUsr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>, | 35 InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 36 InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>, 37 InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>, 38 InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>, |
| 39 // 40 // Unary Instructions that produce a result | 39 // 40 // Unary Instructions that produce a result |
| 41 InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 42 InstrItinData<IIC_iUNAsi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, 43 InstrItinData<IIC_iUNAsr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>, | 41 InstrItinData 42 InstrItinData 43 InstrItinData |
| 44 // 45 // Compare instructions | 44 // 45 // Compare instructions |
| 46 InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>, 47 InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 48 InstrItinData<IIC_iCMPsi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, 49 InstrItinData<IIC_iCMPsr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>, | 46 InstrItinData 47 InstrItinData 48 InstrItinData 49 InstrItinData |
| 50 // 51 // Move instructions, unconditional | 50 // 51 // Move instructions, unconditional |
| 52 InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>, 53 InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>, 54 InstrItinData<IIC_iMOVsi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>, 55 InstrItinData<IIC_iMOVsr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>, | 52 InstrItinData 53 InstrItinData 54 InstrItinData 55 InstrItinData |
| 56 // 57 // Move instructions, conditional | 56 // 57 // Move instructions, conditional |
| 58 InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>, 59 InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, 60 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, 61 InstrItinData<IIC_iCMOVsr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>, | 58 InstrItinData 59 InstrItinData 60 InstrItinData 61 InstrItinData |
| 62 63 // Integer multiply pipeline 64 // Result written in E5, but that is relative to the last cycle of multicycle, 65 // so we use 6 for those cases 66 // 67 InstrItinData<IIC_iMUL16 , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>, | 62 63 // Integer multiply pipeline 64 // Result written in E5, but that is relative to the last cycle of multicycle, 65 // so we use 6 for those cases 66 // 67 InstrItinData<IIC_iMUL16 , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>, |
| 68 InstrItinData<IIC_iMAC16 , [InstrStage<1, [A8_Pipe1], 0>, | 68 InstrItinData |
| 69 InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>, | 69 InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>, |
| 70 InstrItinData<IIC_iMUL32 , [InstrStage<1, [A8_Pipe1], 0>, | 70 InstrItinData |
| 71 InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>, | 71 InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>, |
| 72 InstrItinData<IIC_iMAC32 , [InstrStage<1, [A8_Pipe1], 0>, | 72 InstrItinData |
| 73 InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>, | 73 InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>, |
| 74 InstrItinData<IIC_iMUL64 , [InstrStage<2, [A8_Pipe1], 0>, | 74 InstrItinData |
| 75 InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>, | 75 InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>, |
| 76 InstrItinData<IIC_iMAC64 , [InstrStage<2, [A8_Pipe1], 0>, | 76 InstrItinData |
| 77 InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>, | 77 InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>, |
| 78 | 78 |
| 79 // Integer load pipeline 80 // 81 // loads have an extra cycle of latency, but are fully pipelined 82 // use A8_Issue to enforce the 1 load/store per cycle limit 83 // 84 // Immediate offset 85 InstrItinData<IIC_iLoadi , [InstrStage<1, [A8_Issue], 0>, 86 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, --- 74 unchanged lines hidden (view full) --- 161 InstrStage<1, [A8_LdSt0]>], [3, 3, 1, 1]>, 162 // 163 // Store multiple 164 InstrItinData<IIC_iStorem , [InstrStage<2, [A8_Issue], 0>, 165 InstrStage<2, [A8_Pipe0], 0>, 166 InstrStage<2, [A8_Pipe1]>, 167 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 168 InstrStage<1, [A8_LdSt0]>]>, | 79 // Integer load pipeline 80 // 81 // loads have an extra cycle of latency, but are fully pipelined 82 // use A8_Issue to enforce the 1 load/store per cycle limit 83 // 84 // Immediate offset 85 InstrItinData<IIC_iLoadi , [InstrStage<1, [A8_Issue], 0>, 86 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, --- 74 unchanged lines hidden (view full) --- 161 InstrStage<1, [A8_LdSt0]>], [3, 3, 1, 1]>, 162 // 163 // Store multiple 164 InstrItinData<IIC_iStorem , [InstrStage<2, [A8_Issue], 0>, 165 InstrStage<2, [A8_Pipe0], 0>, 166 InstrStage<2, [A8_Pipe1]>, 167 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 168 InstrStage<1, [A8_LdSt0]>]>, |
| 169 | 169 |
| 170 // Branch 171 // 172 // no delay slots, so the latency of a branch is unimportant 173 InstrItinData<IIC_Br , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>, 174 175 // VFP 176 // Issue through integer pipeline, and execute in NEON unit. We assume 177 // RunFast mode so that NFP pipeline is used for single-precision when --- 93 unchanged lines hidden (view full) --- 271 // 272 // Double-precision FP SQRT 273 InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 274 InstrStage<29, [A8_NPipe], 0>, 275 InstrStage<29, [A8_NLSPipe]>], [29, 1]>, 276 // 277 // Single-precision FP Load 278 // use A8_Issue to enforce the 1 load/store per cycle limit | 170 // Branch 171 // 172 // no delay slots, so the latency of a branch is unimportant 173 InstrItinData<IIC_Br , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>, 174 175 // VFP 176 // Issue through integer pipeline, and execute in NEON unit. We assume 177 // RunFast mode so that NFP pipeline is used for single-precision when --- 93 unchanged lines hidden (view full) --- 271 // 272 // Double-precision FP SQRT 273 InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 274 InstrStage<29, [A8_NPipe], 0>, 275 InstrStage<29, [A8_NLSPipe]>], [29, 1]>, 276 // 277 // Single-precision FP Load 278 // use A8_Issue to enforce the 1 load/store per cycle limit |
| 279 InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Issue], 0>, | 279 InstrItinData |
| 280 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 281 InstrStage<1, [A8_LdSt0], 0>, 282 InstrStage<1, [A8_NLSPipe]>]>, 283 // 284 // Double-precision FP Load 285 // use A8_Issue to enforce the 1 load/store per cycle limit | 280 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 281 InstrStage<1, [A8_LdSt0], 0>, 282 InstrStage<1, [A8_NLSPipe]>]>, 283 // 284 // Double-precision FP Load 285 // use A8_Issue to enforce the 1 load/store per cycle limit |
| 286 InstrItinData<IIC_fpLoad64, [InstrStage<2, [A8_Issue], 0>, | 286 InstrItinData |
| 287 InstrStage<1, [A8_Pipe0], 0>, 288 InstrStage<1, [A8_Pipe1]>, 289 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 290 InstrStage<1, [A8_LdSt0], 0>, 291 InstrStage<1, [A8_NLSPipe]>]>, 292 // 293 // FP Load Multiple 294 // use A8_Issue to enforce the 1 load/store per cycle limit | 287 InstrStage<1, [A8_Pipe0], 0>, 288 InstrStage<1, [A8_Pipe1]>, 289 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 290 InstrStage<1, [A8_LdSt0], 0>, 291 InstrStage<1, [A8_NLSPipe]>]>, 292 // 293 // FP Load Multiple 294 // use A8_Issue to enforce the 1 load/store per cycle limit |
| 295 InstrItinData<IIC_fpLoadm, [InstrStage<3, [A8_Issue], 0>, | 295 InstrItinData |
| 296 InstrStage<2, [A8_Pipe0], 0>, 297 InstrStage<2, [A8_Pipe1]>, 298 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 299 InstrStage<1, [A8_LdSt0], 0>, 300 InstrStage<1, [A8_NLSPipe]>]>, 301 // 302 // Single-precision FP Store 303 // use A8_Issue to enforce the 1 load/store per cycle limit | 296 InstrStage<2, [A8_Pipe0], 0>, 297 InstrStage<2, [A8_Pipe1]>, 298 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 299 InstrStage<1, [A8_LdSt0], 0>, 300 InstrStage<1, [A8_NLSPipe]>]>, 301 // 302 // Single-precision FP Store 303 // use A8_Issue to enforce the 1 load/store per cycle limit |
| 304 InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Issue], 0>, | 304 InstrItinData |
| 305 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 306 InstrStage<1, [A8_LdSt0], 0>, 307 InstrStage<1, [A8_NLSPipe]>]>, 308 // 309 // Double-precision FP Store 310 // use A8_Issue to enforce the 1 load/store per cycle limit | 305 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 306 InstrStage<1, [A8_LdSt0], 0>, 307 InstrStage<1, [A8_NLSPipe]>]>, 308 // 309 // Double-precision FP Store 310 // use A8_Issue to enforce the 1 load/store per cycle limit |
| 311 InstrItinData<IIC_fpStore64,[InstrStage<2, [A8_Issue], 0>, | 311 InstrItinData |
| 312 InstrStage<1, [A8_Pipe0], 0>, 313 InstrStage<1, [A8_Pipe1]>, 314 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 315 InstrStage<1, [A8_LdSt0], 0>, 316 InstrStage<1, [A8_NLSPipe]>]>, 317 // 318 // FP Store Multiple 319 // use A8_Issue to enforce the 1 load/store per cycle limit | 312 InstrStage<1, [A8_Pipe0], 0>, 313 InstrStage<1, [A8_Pipe1]>, 314 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 315 InstrStage<1, [A8_LdSt0], 0>, 316 InstrStage<1, [A8_NLSPipe]>]>, 317 // 318 // FP Store Multiple 319 // use A8_Issue to enforce the 1 load/store per cycle limit |
| 320 InstrItinData<IIC_fpStorem, [InstrStage<3, [A8_Issue], 0>, | 320 InstrItinData |
| 321 InstrStage<2, [A8_Pipe0], 0>, 322 InstrStage<2, [A8_Pipe1]>, 323 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 324 InstrStage<1, [A8_LdSt0], 0>, 325 InstrStage<1, [A8_NLSPipe]>]>, 326 327 // NEON 328 // Issue through integer pipeline, and execute in NEON unit. 329 // 330 // VLD1 331 // FIXME: We don't model this instruction properly | 321 InstrStage<2, [A8_Pipe0], 0>, 322 InstrStage<2, [A8_Pipe1]>, 323 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 324 InstrStage<1, [A8_LdSt0], 0>, 325 InstrStage<1, [A8_NLSPipe]>]>, 326 327 // NEON 328 // Issue through integer pipeline, and execute in NEON unit. 329 // 330 // VLD1 331 // FIXME: We don't model this instruction properly |
| 332 InstrItinData<IIC_VLD1, [InstrStage<1, [A8_Issue], 0>, | 332 InstrItinData |
| 333 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 334 InstrStage<1, [A8_LdSt0], 0>, 335 InstrStage<1, [A8_NLSPipe]>]>, 336 // 337 // VLD2 338 // FIXME: We don't model this instruction properly | 333 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 334 InstrStage<1, [A8_LdSt0], 0>, 335 InstrStage<1, [A8_NLSPipe]>]>, 336 // 337 // VLD2 338 // FIXME: We don't model this instruction properly |
| 339 InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Issue], 0>, | 339 InstrItinData |
| 340 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 341 InstrStage<1, [A8_LdSt0], 0>, 342 InstrStage<1, [A8_NLSPipe]>], [2, 2, 1]>, 343 // 344 // VLD3 345 // FIXME: We don't model this instruction properly | 340 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 341 InstrStage<1, [A8_LdSt0], 0>, 342 InstrStage<1, [A8_NLSPipe]>], [2, 2, 1]>, 343 // 344 // VLD3 345 // FIXME: We don't model this instruction properly |
| 346 InstrItinData<IIC_VLD3, [InstrStage<1, [A8_Issue], 0>, | 346 InstrItinData |
| 347 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 348 InstrStage<1, [A8_LdSt0], 0>, 349 InstrStage<1, [A8_NLSPipe]>], [2, 2, 2, 1]>, 350 // 351 // VLD4 352 // FIXME: We don't model this instruction properly | 347 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 348 InstrStage<1, [A8_LdSt0], 0>, 349 InstrStage<1, [A8_NLSPipe]>], [2, 2, 2, 1]>, 350 // 351 // VLD4 352 // FIXME: We don't model this instruction properly |
| 353 InstrItinData<IIC_VLD4, [InstrStage<1, [A8_Issue], 0>, | 353 InstrItinData |
| 354 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 355 InstrStage<1, [A8_LdSt0], 0>, 356 InstrStage<1, [A8_NLSPipe]>], [2, 2, 2, 2, 1]>, 357 // 358 // VST 359 // FIXME: We don't model this instruction properly | 354 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 355 InstrStage<1, [A8_LdSt0], 0>, 356 InstrStage<1, [A8_NLSPipe]>], [2, 2, 2, 2, 1]>, 357 // 358 // VST 359 // FIXME: We don't model this instruction properly |
| 360 InstrItinData<IIC_VST, [InstrStage<1, [A8_Issue], 0>, | 360 InstrItinData |
| 361 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 362 InstrStage<1, [A8_LdSt0], 0>, 363 InstrStage<1, [A8_NLSPipe]>]>, 364 // 365 // Double-register FP Unary 366 InstrItinData<IIC_VUNAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 367 InstrStage<1, [A8_NPipe]>], [5, 2]>, 368 // --- 226 unchanged lines hidden (view full) --- 595 InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>, 596 InstrItinData<IIC_VTB3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 597 InstrStage<1, [A8_NLSPipe]>, 598 InstrStage<1, [A8_NPipe], 0>, 599 InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>, 600 InstrItinData<IIC_VTB4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 601 InstrStage<1, [A8_NLSPipe]>, 602 InstrStage<1, [A8_NPipe], 0>, | 361 InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 362 InstrStage<1, [A8_LdSt0], 0>, 363 InstrStage<1, [A8_NLSPipe]>]>, 364 // 365 // Double-register FP Unary 366 InstrItinData<IIC_VUNAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 367 InstrStage<1, [A8_NPipe]>], [5, 2]>, 368 // --- 226 unchanged lines hidden (view full) --- 595 InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>, 596 InstrItinData<IIC_VTB3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 597 InstrStage<1, [A8_NLSPipe]>, 598 InstrStage<1, [A8_NPipe], 0>, 599 InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>, 600 InstrItinData<IIC_VTB4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 601 InstrStage<1, [A8_NLSPipe]>, 602 InstrStage<1, [A8_NPipe], 0>, |
| 603 InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 3, 1]>, | 603 InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>, |
| 604 // 605 // VTBX 606 InstrItinData<IIC_VTBX1, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 607 InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>, 608 InstrItinData<IIC_VTBX2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 609 InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>, 610 InstrItinData<IIC_VTBX3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 611 InstrStage<1, [A8_NLSPipe]>, 612 InstrStage<1, [A8_NPipe], 0>, | 604 // 605 // VTBX 606 InstrItinData<IIC_VTBX1, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 607 InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>, 608 InstrItinData<IIC_VTBX2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 609 InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>, 610 InstrItinData<IIC_VTBX3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 611 InstrStage<1, [A8_NLSPipe]>, 612 InstrStage<1, [A8_NPipe], 0>, |
| 613 InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 1]>, | 613 InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>, |
| 614 InstrItinData<IIC_VTBX4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 615 InstrStage<1, [A8_NLSPipe]>, 616 InstrStage<1, [A8_NPipe], 0>, | 614 InstrItinData<IIC_VTBX4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 615 InstrStage<1, [A8_NLSPipe]>, 616 InstrStage<1, [A8_NPipe], 0>, |
| 617 InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]> | 617 InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]> |
| 618]>; | 618]>; |