Deleted Added
sdiff udiff text old ( 263508 ) new ( 266715 )
full compact
A15SDOptimizer.cpp (263508) A15SDOptimizer.cpp (266715)
1//=== A15SDOptimizerPass.cpp - Optimize DPR and SPR register accesses on A15==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 404 unchanged lines hidden (view full) ---

413
414 SmallVector<unsigned, 8> Defs;
415 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
416 MachineOperand &MO = MI->getOperand(i);
417
418 if (!MO.isReg() || !MO.isUse())
419 continue;
420 if (!usesRegClass(MO, &ARM::DPRRegClass) &&
1//=== A15SDOptimizerPass.cpp - Optimize DPR and SPR register accesses on A15==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 404 unchanged lines hidden (view full) ---

413
414 SmallVector<unsigned, 8> Defs;
415 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
416 MachineOperand &MO = MI->getOperand(i);
417
418 if (!MO.isReg() || !MO.isUse())
419 continue;
420 if (!usesRegClass(MO, &ARM::DPRRegClass) &&
421 !usesRegClass(MO, &ARM::QPRRegClass))
421 !usesRegClass(MO, &ARM::QPRRegClass) &&
422 !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR
422 continue;
423
424 Defs.push_back(MO.getReg());
425 }
426 return Defs;
427}
428
429// Creates a DPR register from an SPR one by using a VDUP.

--- 103 unchanged lines hidden (view full) ---

533unsigned
534A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) {
535 MachineBasicBlock::iterator InsertPt(MI);
536 DebugLoc DL = MI->getDebugLoc();
537 MachineBasicBlock &MBB = *MI->getParent();
538 InsertPt++;
539 unsigned Out;
540
423 continue;
424
425 Defs.push_back(MO.getReg());
426 }
427 return Defs;
428}
429
430// Creates a DPR register from an SPR one by using a VDUP.

--- 103 unchanged lines hidden (view full) ---

534unsigned
535A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) {
536 MachineBasicBlock::iterator InsertPt(MI);
537 DebugLoc DL = MI->getDebugLoc();
538 MachineBasicBlock &MBB = *MI->getParent();
539 InsertPt++;
540 unsigned Out;
541
541 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass)) {
542 // DPair has the same length as QPR and also has two DPRs as subreg.
543 // Treat DPair as QPR.
544 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
545 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
542 unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
543 ARM::dsub_0, &ARM::DPRRegClass);
544 unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
545 ARM::dsub_1, &ARM::DPRRegClass);
546
547 unsigned Out1 = createDupLane(MBB, InsertPt, DL, DSub0, 0);
548 unsigned Out2 = createDupLane(MBB, InsertPt, DL, DSub0, 1);
549 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);

--- 16 unchanged lines hidden (view full) ---

566 unsigned PrefLane = getPrefSPRLane(Reg);
567 unsigned Lane;
568 switch (PrefLane) {
569 case ARM::ssub_0: Lane = 0; break;
570 case ARM::ssub_1: Lane = 1; break;
571 default: llvm_unreachable("Unknown preferred lane!");
572 }
573
546 unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
547 ARM::dsub_0, &ARM::DPRRegClass);
548 unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
549 ARM::dsub_1, &ARM::DPRRegClass);
550
551 unsigned Out1 = createDupLane(MBB, InsertPt, DL, DSub0, 0);
552 unsigned Out2 = createDupLane(MBB, InsertPt, DL, DSub0, 1);
553 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);

--- 16 unchanged lines hidden (view full) ---

570 unsigned PrefLane = getPrefSPRLane(Reg);
571 unsigned Lane;
572 switch (PrefLane) {
573 case ARM::ssub_0: Lane = 0; break;
574 case ARM::ssub_1: Lane = 1; break;
575 default: llvm_unreachable("Unknown preferred lane!");
576 }
577
574 bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass);
578 // Treat DPair as QPR
579 bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
580 usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
575
576 Out = createImplicitDef(MBB, InsertPt, DL);
577 Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
578 Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
579 eraseInstrWithNoUses(MI);
580 }
581 return Out;
582}

--- 129 unchanged lines hidden --- 		581
582 Out = createImplicitDef(MBB, InsertPt, DL);
583 Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
584 Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
585 eraseInstrWithNoUses(MI);
586 }
587 return Out;
588}

--- 129 unchanged lines hidden ---