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AArch64InstrInfo.td (263508) AArch64InstrInfo.td (266715)
1//===----- AArch64InstrInfo.td - AArch64 Instruction Info ----*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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2582 InstrItinClass itin> :
2583 A64I_LDSTex_stn <size,
2584 opcode{2}, 0, opcode{1}, opcode{0},
2585 outs, ins,
2586 !strconcat(asm, "\t$Rs, $Rt, [$Rn]"),
2587 pat, itin> {
2588 let mayStore = 1;
2589 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
1//===----- AArch64InstrInfo.td - AArch64 Instruction Info ----*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 2573 unchanged lines hidden (view full) ---

2582 InstrItinClass itin> :
2583 A64I_LDSTex_stn <size,
2584 opcode{2}, 0, opcode{1}, opcode{0},
2585 outs, ins,
2586 !strconcat(asm, "\t$Rs, $Rt, [$Rn]"),
2587 pat, itin> {
2588 let mayStore = 1;
2589 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
2590 let Constraints = "@earlyclobber $Rs";
2590}
2591
2592multiclass A64I_SRex<string asmstr, bits<3> opcode, string prefix> {
2593 def _byte: A64I_SRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2594 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2595 [], NoItinerary>;
2596
2597 def _hword: A64I_SRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),

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2591}
2592
2593multiclass A64I_SRex<string asmstr, bits<3> opcode, string prefix> {
2594 def _byte: A64I_SRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2595 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2596 [], NoItinerary>;
2597
2598 def _hword: A64I_SRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),

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