1/* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
10
11 This file is part of GAS, the GNU Assembler.
12
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
16 any later version.
17
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26 02110-1301, USA. */
27
28#include <limits.h>
29#include <stdarg.h>
30#define NO_RELOC 0
31#include "as.h"
32#include "safe-ctype.h"
33#include "subsegs.h"
34#include "obstack.h"
35
36#include "opcode/arm.h"
37
38#ifdef OBJ_ELF
39#include "elf/arm.h"
40#include "dw2gencfi.h"
41#endif
42
43#include "dwarf2dbg.h"
44
45#define WARN_DEPRECATED 1
46
47#ifdef OBJ_ELF
48/* Must be at least the size of the largest unwind opcode (currently two). */
49#define ARM_OPCODE_CHUNK_SIZE 8
50
51/* This structure holds the unwinding state. */
52
53static struct
54{
55 symbolS * proc_start;
56 symbolS * table_entry;
57 symbolS * personality_routine;
58 int personality_index;
59 /* The segment containing the function. */
60 segT saved_seg;
61 subsegT saved_subseg;
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes;
64 int opcode_count;
65 int opcode_alloc;
66 /* The number of bytes pushed to the stack. */
67 offsetT frame_size;
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
74 offsetT fp_offset;
75 int fp_reg;
76 /* Nonzero if an unwind_setfp directive has been seen. */
77 unsigned fp_used:1;
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored:1;
80} unwind;
81
82/* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85static unsigned int marked_pr_dependency = 0;
86
87#endif /* OBJ_ELF */
88
89/* Results from operand parsing worker functions. */
90
91typedef enum
92{
93 PARSE_OPERAND_SUCCESS,
94 PARSE_OPERAND_FAIL,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96} parse_operand_result;
97
98enum arm_float_abi
99{
100 ARM_FLOAT_ABI_HARD,
101 ARM_FLOAT_ABI_SOFTFP,
102 ARM_FLOAT_ABI_SOFT
103};
104
105/* Types of processor to assemble for. */
106#ifndef CPU_DEFAULT
107#if defined __XSCALE__
108#define CPU_DEFAULT ARM_ARCH_XSCALE
109#else
110#if defined __thumb__
111#define CPU_DEFAULT ARM_ARCH_V5T
112#endif
113#endif
114#endif
115
116#ifndef FPU_DEFAULT
117# ifdef TE_LINUX
118# define FPU_DEFAULT FPU_ARCH_FPA
119# elif defined (TE_NetBSD)
120# ifdef OBJ_ELF
121# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
122# else
123 /* Legacy a.out format. */
124# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
125# endif
126# elif defined (TE_VXWORKS)
127# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
128# else
129 /* For backwards compatibility, default to FPA. */
130# define FPU_DEFAULT FPU_ARCH_FPA
131# endif
132#endif /* ifndef FPU_DEFAULT */
133
134#define streq(a, b) (strcmp (a, b) == 0)
135
136static arm_feature_set cpu_variant;
137static arm_feature_set arm_arch_used;
138static arm_feature_set thumb_arch_used;
139
140/* Flags stored in private area of BFD structure. */
141static int uses_apcs_26 = FALSE;
142static int atpcs = FALSE;
143static int support_interwork = FALSE;
144static int uses_apcs_float = FALSE;
145static int pic_code = FALSE;
146
147/* Variables that we set while parsing command-line options. Once all
148 options have been read we re-process these values to set the real
149 assembly flags. */
150static const arm_feature_set *legacy_cpu = NULL;
151static const arm_feature_set *legacy_fpu = NULL;
152
153static const arm_feature_set *mcpu_cpu_opt = NULL;
154static const arm_feature_set *mcpu_fpu_opt = NULL;
155static const arm_feature_set *march_cpu_opt = NULL;
156static const arm_feature_set *march_fpu_opt = NULL;
157static const arm_feature_set *mfpu_opt = NULL;
158static const arm_feature_set *object_arch = NULL;
159
160/* Constants for known architecture features. */
161static const arm_feature_set fpu_default = FPU_DEFAULT;
162static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
163static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
164static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
165static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
166static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
167static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
168static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
169static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
170
171#ifdef CPU_DEFAULT
172static const arm_feature_set cpu_default = CPU_DEFAULT;
173#endif
174
175static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
176static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
177static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
178static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
179static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
180static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
181static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
182static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
183static const arm_feature_set arm_ext_v4t_5 =
184 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
185static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
186static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
187static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
188static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
189static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
190static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
191static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0);
192static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
193static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
194static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
195static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
196static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
197static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
198static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
199
200static const arm_feature_set arm_arch_any = ARM_ANY;
201static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
202static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
203static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
204
205static const arm_feature_set arm_cext_iwmmxt2 =
206 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
207static const arm_feature_set arm_cext_iwmmxt =
208 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
209static const arm_feature_set arm_cext_xscale =
210 ARM_FEATURE (0, ARM_CEXT_XSCALE);
211static const arm_feature_set arm_cext_maverick =
212 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
213static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
214static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
215static const arm_feature_set fpu_vfp_ext_v1xd =
216 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
217static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
218static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
219static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
220static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
221static const arm_feature_set fpu_vfp_v3_or_neon_ext =
222 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
223
224static int mfloat_abi_opt = -1;
225/* Record user cpu selection for object attributes. */
226static arm_feature_set selected_cpu = ARM_ARCH_NONE;
227/* Must be long enough to hold any of the names in arm_cpus. */
228static char selected_cpu_name[16];
229#ifdef OBJ_ELF
230# ifdef EABI_DEFAULT
231static int meabi_flags = EABI_DEFAULT;
232# else
233static int meabi_flags = EF_ARM_EABI_UNKNOWN;
234# endif
235
236bfd_boolean
237arm_is_eabi(void)
238{
239 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
240}
241#endif
242
243#ifdef OBJ_ELF
244/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
245symbolS * GOT_symbol;
246#endif
247
248/* 0: assemble for ARM,
249 1: assemble for Thumb,
250 2: assemble for Thumb even though target CPU does not support thumb
251 instructions. */
252static int thumb_mode = 0;
253
254/* If unified_syntax is true, we are processing the new unified
255 ARM/Thumb syntax. Important differences from the old ARM mode:
256
257 - Immediate operands do not require a # prefix.
258 - Conditional affixes always appear at the end of the
259 instruction. (For backward compatibility, those instructions
260 that formerly had them in the middle, continue to accept them
261 there.)
262 - The IT instruction may appear, and if it does is validated
263 against subsequent conditional affixes. It does not generate
264 machine code.
265
266 Important differences from the old Thumb mode:
267
268 - Immediate operands do not require a # prefix.
269 - Most of the V6T2 instructions are only available in unified mode.
270 - The .N and .W suffixes are recognized and honored (it is an error
271 if they cannot be honored).
272 - All instructions set the flags if and only if they have an 's' affix.
273 - Conditional affixes may be used. They are validated against
274 preceding IT instructions. Unlike ARM mode, you cannot use a
275 conditional affix except in the scope of an IT instruction. */
276
277static bfd_boolean unified_syntax = FALSE;
278
279enum neon_el_type
280{
281 NT_invtype,
282 NT_untyped,
283 NT_integer,
284 NT_float,
285 NT_poly,
286 NT_signed,
287 NT_unsigned
288};
289
290struct neon_type_el
291{
292 enum neon_el_type type;
293 unsigned size;
294};
295
296#define NEON_MAX_TYPE_ELS 4
297
298struct neon_type
299{
300 struct neon_type_el el[NEON_MAX_TYPE_ELS];
301 unsigned elems;
302};
303
304struct arm_it
305{
306 const char * error;
307 unsigned long instruction;
308 int size;
309 int size_req;
310 int cond;
311 /* "uncond_value" is set to the value in place of the conditional field in
312 unconditional versions of the instruction, or -1 if nothing is
313 appropriate. */
314 int uncond_value;
315 struct neon_type vectype;
316 /* Set to the opcode if the instruction needs relaxation.
317 Zero if the instruction is not relaxed. */
318 unsigned long relax;
319 struct
320 {
321 bfd_reloc_code_real_type type;
322 expressionS exp;
323 int pc_rel;
324 } reloc;
325
326 struct
327 {
328 unsigned reg;
329 signed int imm;
330 struct neon_type_el vectype;
331 unsigned present : 1; /* Operand present. */
332 unsigned isreg : 1; /* Operand was a register. */
333 unsigned immisreg : 1; /* .imm field is a second register. */
334 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
335 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
336 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
337 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
338 instructions. This allows us to disambiguate ARM <-> vector insns. */
339 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
340 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
341 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
342 unsigned issingle : 1; /* Operand is VFP single-precision register. */
343 unsigned hasreloc : 1; /* Operand has relocation suffix. */
344 unsigned writeback : 1; /* Operand has trailing ! */
345 unsigned preind : 1; /* Preindexed address. */
346 unsigned postind : 1; /* Postindexed address. */
347 unsigned negative : 1; /* Index register was negated. */
348 unsigned shifted : 1; /* Shift applied to operation. */
349 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
350 } operands[6];
351};
352
353static struct arm_it inst;
354
355#define NUM_FLOAT_VALS 8
356
357const char * fp_const[] =
358{
359 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
360};
361
362/* Number of littlenums required to hold an extended precision number. */
363#define MAX_LITTLENUMS 6
364
365LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
366
367#define FAIL (-1)
368#define SUCCESS (0)
369
370#define SUFF_S 1
371#define SUFF_D 2
372#define SUFF_E 3
373#define SUFF_P 4
374
375#define CP_T_X 0x00008000
376#define CP_T_Y 0x00400000
377
378#define CONDS_BIT 0x00100000
379#define LOAD_BIT 0x00100000
380
381#define DOUBLE_LOAD_FLAG 0x00000001
382
383struct asm_cond
384{
385 const char * template;
386 unsigned long value;
387};
388
389#define COND_ALWAYS 0xE
390
391struct asm_psr
392{
393 const char *template;
394 unsigned long field;
395};
396
397struct asm_barrier_opt
398{
399 const char *template;
400 unsigned long value;
401};
402
403/* The bit that distinguishes CPSR and SPSR. */
404#define SPSR_BIT (1 << 22)
405
406/* The individual PSR flag bits. */
407#define PSR_c (1 << 16)
408#define PSR_x (1 << 17)
409#define PSR_s (1 << 18)
410#define PSR_f (1 << 19)
411
412struct reloc_entry
413{
414 char *name;
415 bfd_reloc_code_real_type reloc;
416};
417
418enum vfp_reg_pos
419{
420 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
421 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
422};
423
424enum vfp_ldstm_type
425{
426 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
427};
428
429/* Bits for DEFINED field in neon_typed_alias. */
430#define NTA_HASTYPE 1
431#define NTA_HASINDEX 2
432
433struct neon_typed_alias
434{
435 unsigned char defined;
436 unsigned char index;
437 struct neon_type_el eltype;
438};
439
440/* ARM register categories. This includes coprocessor numbers and various
441 architecture extensions' registers. */
442enum arm_reg_type
443{
444 REG_TYPE_RN,
445 REG_TYPE_CP,
446 REG_TYPE_CN,
447 REG_TYPE_FN,
448 REG_TYPE_VFS,
449 REG_TYPE_VFD,
450 REG_TYPE_NQ,
451 REG_TYPE_VFSD,
452 REG_TYPE_NDQ,
453 REG_TYPE_NSDQ,
454 REG_TYPE_VFC,
455 REG_TYPE_MVF,
456 REG_TYPE_MVD,
457 REG_TYPE_MVFX,
458 REG_TYPE_MVDX,
459 REG_TYPE_MVAX,
460 REG_TYPE_DSPSC,
461 REG_TYPE_MMXWR,
462 REG_TYPE_MMXWC,
463 REG_TYPE_MMXWCG,
464 REG_TYPE_XSCALE,
465};
466
467/* Structure for a hash table entry for a register.
468 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
469 information which states whether a vector type or index is specified (for a
470 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
471struct reg_entry
472{
473 const char *name;
474 unsigned char number;
475 unsigned char type;
476 unsigned char builtin;
477 struct neon_typed_alias *neon;
478};
479
480/* Diagnostics used when we don't get a register of the expected type. */
481const char *const reg_expected_msgs[] =
482{
483 N_("ARM register expected"),
484 N_("bad or missing co-processor number"),
485 N_("co-processor register expected"),
486 N_("FPA register expected"),
487 N_("VFP single precision register expected"),
488 N_("VFP/Neon double precision register expected"),
489 N_("Neon quad precision register expected"),
490 N_("VFP single or double precision register expected"),
491 N_("Neon double or quad precision register expected"),
492 N_("VFP single, double or Neon quad precision register expected"),
493 N_("VFP system register expected"),
494 N_("Maverick MVF register expected"),
495 N_("Maverick MVD register expected"),
496 N_("Maverick MVFX register expected"),
497 N_("Maverick MVDX register expected"),
498 N_("Maverick MVAX register expected"),
499 N_("Maverick DSPSC register expected"),
500 N_("iWMMXt data register expected"),
501 N_("iWMMXt control register expected"),
502 N_("iWMMXt scalar register expected"),
503 N_("XScale accumulator register expected"),
504};
505
506/* Some well known registers that we refer to directly elsewhere. */
507#define REG_SP 13
508#define REG_LR 14
509#define REG_PC 15
510
511/* ARM instructions take 4bytes in the object file, Thumb instructions
512 take 2: */
513#define INSN_SIZE 4
514
515struct asm_opcode
516{
517 /* Basic string to match. */
518 const char *template;
519
520 /* Parameters to instruction. */
521 unsigned char operands[8];
522
523 /* Conditional tag - see opcode_lookup. */
524 unsigned int tag : 4;
525
526 /* Basic instruction code. */
527 unsigned int avalue : 28;
528
529 /* Thumb-format instruction code. */
530 unsigned int tvalue;
531
532 /* Which architecture variant provides this instruction. */
533 const arm_feature_set *avariant;
534 const arm_feature_set *tvariant;
535
536 /* Function to call to encode instruction in ARM format. */
537 void (* aencode) (void);
538
539 /* Function to call to encode instruction in Thumb format. */
540 void (* tencode) (void);
541};
542
543/* Defines for various bits that we will want to toggle. */
544#define INST_IMMEDIATE 0x02000000
545#define OFFSET_REG 0x02000000
546#define HWOFFSET_IMM 0x00400000
547#define SHIFT_BY_REG 0x00000010
548#define PRE_INDEX 0x01000000
549#define INDEX_UP 0x00800000
550#define WRITE_BACK 0x00200000
551#define LDM_TYPE_2_OR_3 0x00400000
552#define CPSI_MMOD 0x00020000
553
554#define LITERAL_MASK 0xf000f000
555#define OPCODE_MASK 0xfe1fffff
556#define V4_STR_BIT 0x00000020
557
558#define T2_SUBS_PC_LR 0xf3de8f00
559
560#define DATA_OP_SHIFT 21
561
562#define T2_OPCODE_MASK 0xfe1fffff
563#define T2_DATA_OP_SHIFT 21
564
565/* Codes to distinguish the arithmetic instructions. */
566#define OPCODE_AND 0
567#define OPCODE_EOR 1
568#define OPCODE_SUB 2
569#define OPCODE_RSB 3
570#define OPCODE_ADD 4
571#define OPCODE_ADC 5
572#define OPCODE_SBC 6
573#define OPCODE_RSC 7
574#define OPCODE_TST 8
575#define OPCODE_TEQ 9
576#define OPCODE_CMP 10
577#define OPCODE_CMN 11
578#define OPCODE_ORR 12
579#define OPCODE_MOV 13
580#define OPCODE_BIC 14
581#define OPCODE_MVN 15
582
583#define T2_OPCODE_AND 0
584#define T2_OPCODE_BIC 1
585#define T2_OPCODE_ORR 2
586#define T2_OPCODE_ORN 3
587#define T2_OPCODE_EOR 4
588#define T2_OPCODE_ADD 8
589#define T2_OPCODE_ADC 10
590#define T2_OPCODE_SBC 11
591#define T2_OPCODE_SUB 13
592#define T2_OPCODE_RSB 14
593
594#define T_OPCODE_MUL 0x4340
595#define T_OPCODE_TST 0x4200
596#define T_OPCODE_CMN 0x42c0
597#define T_OPCODE_NEG 0x4240
598#define T_OPCODE_MVN 0x43c0
599
600#define T_OPCODE_ADD_R3 0x1800
601#define T_OPCODE_SUB_R3 0x1a00
602#define T_OPCODE_ADD_HI 0x4400
603#define T_OPCODE_ADD_ST 0xb000
604#define T_OPCODE_SUB_ST 0xb080
605#define T_OPCODE_ADD_SP 0xa800
606#define T_OPCODE_ADD_PC 0xa000
607#define T_OPCODE_ADD_I8 0x3000
608#define T_OPCODE_SUB_I8 0x3800
609#define T_OPCODE_ADD_I3 0x1c00
610#define T_OPCODE_SUB_I3 0x1e00
611
612#define T_OPCODE_ASR_R 0x4100
613#define T_OPCODE_LSL_R 0x4080
614#define T_OPCODE_LSR_R 0x40c0
615#define T_OPCODE_ROR_R 0x41c0
616#define T_OPCODE_ASR_I 0x1000
617#define T_OPCODE_LSL_I 0x0000
618#define T_OPCODE_LSR_I 0x0800
619
620#define T_OPCODE_MOV_I8 0x2000
621#define T_OPCODE_CMP_I8 0x2800
622#define T_OPCODE_CMP_LR 0x4280
623#define T_OPCODE_MOV_HR 0x4600
624#define T_OPCODE_CMP_HR 0x4500
625
626#define T_OPCODE_LDR_PC 0x4800
627#define T_OPCODE_LDR_SP 0x9800
628#define T_OPCODE_STR_SP 0x9000
629#define T_OPCODE_LDR_IW 0x6800
630#define T_OPCODE_STR_IW 0x6000
631#define T_OPCODE_LDR_IH 0x8800
632#define T_OPCODE_STR_IH 0x8000
633#define T_OPCODE_LDR_IB 0x7800
634#define T_OPCODE_STR_IB 0x7000
635#define T_OPCODE_LDR_RW 0x5800
636#define T_OPCODE_STR_RW 0x5000
637#define T_OPCODE_LDR_RH 0x5a00
638#define T_OPCODE_STR_RH 0x5200
639#define T_OPCODE_LDR_RB 0x5c00
640#define T_OPCODE_STR_RB 0x5400
641
642#define T_OPCODE_PUSH 0xb400
643#define T_OPCODE_POP 0xbc00
644
645#define T_OPCODE_BRANCH 0xe000
646
647#define THUMB_SIZE 2 /* Size of thumb instruction. */
648#define THUMB_PP_PC_LR 0x0100
649#define THUMB_LOAD_BIT 0x0800
650#define THUMB2_LOAD_BIT 0x00100000
651
652#define BAD_ARGS _("bad arguments to instruction")
653#define BAD_PC _("r15 not allowed here")
654#define BAD_COND _("instruction cannot be conditional")
655#define BAD_OVERLAP _("registers may not be the same")
656#define BAD_HIREG _("lo register required")
657#define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
658#define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
659#define BAD_BRANCH _("branch must be last instruction in IT block")
660#define BAD_NOT_IT _("instruction not allowed in IT block")
661#define BAD_FPU _("selected FPU does not support instruction")
662
663static struct hash_control *arm_ops_hsh;
664static struct hash_control *arm_cond_hsh;
665static struct hash_control *arm_shift_hsh;
666static struct hash_control *arm_psr_hsh;
667static struct hash_control *arm_v7m_psr_hsh;
668static struct hash_control *arm_reg_hsh;
669static struct hash_control *arm_reloc_hsh;
670static struct hash_control *arm_barrier_opt_hsh;
671
672/* Stuff needed to resolve the label ambiguity
673 As:
674 ...
675 label: <insn>
676 may differ from:
677 ...
678 label:
679 <insn>
680*/
681
682symbolS * last_label_seen;
683static int label_is_thumb_function_name = FALSE;
684
685/* Literal pool structure. Held on a per-section
686 and per-sub-section basis. */
687
688#define MAX_LITERAL_POOL_SIZE 1024
689typedef struct literal_pool
690{
691 expressionS literals [MAX_LITERAL_POOL_SIZE];
692 unsigned int next_free_entry;
693 unsigned int id;
694 symbolS * symbol;
695 segT section;
696 subsegT sub_section;
697 struct literal_pool * next;
698} literal_pool;
699
700/* Pointer to a linked list of literal pools. */
701literal_pool * list_of_pools = NULL;
702
703/* State variables for IT block handling. */
704static bfd_boolean current_it_mask = 0;
705static int current_cc;
706
707
708/* Pure syntax. */
709
710/* This array holds the chars that always start a comment. If the
711 pre-processor is disabled, these aren't very useful. */
712const char comment_chars[] = "@";
713
714/* This array holds the chars that only start a comment at the beginning of
715 a line. If the line seems to have the form '# 123 filename'
716 .line and .file directives will appear in the pre-processed output. */
717/* Note that input_file.c hand checks for '#' at the beginning of the
718 first line of the input file. This is because the compiler outputs
719 #NO_APP at the beginning of its output. */
720/* Also note that comments like this one will always work. */
721const char line_comment_chars[] = "#";
722
723const char line_separator_chars[] = ";";
724
725/* Chars that can be used to separate mant
726 from exp in floating point numbers. */
727const char EXP_CHARS[] = "eE";
728
729/* Chars that mean this number is a floating point constant. */
730/* As in 0f12.456 */
731/* or 0d1.2345e12 */
732
733const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
734
735/* Prefix characters that indicate the start of an immediate
736 value. */
737#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
738
739/* Separator character handling. */
740
741#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
742
743static inline int
744skip_past_char (char ** str, char c)
745{
746 if (**str == c)
747 {
748 (*str)++;
749 return SUCCESS;
750 }
751 else
752 return FAIL;
753}
754#define skip_past_comma(str) skip_past_char (str, ',')
755
756/* Arithmetic expressions (possibly involving symbols). */
757
758/* Return TRUE if anything in the expression is a bignum. */
759
760static int
761walk_no_bignums (symbolS * sp)
762{
763 if (symbol_get_value_expression (sp)->X_op == O_big)
764 return 1;
765
766 if (symbol_get_value_expression (sp)->X_add_symbol)
767 {
768 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
769 || (symbol_get_value_expression (sp)->X_op_symbol
770 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
771 }
772
773 return 0;
774}
775
776static int in_my_get_expression = 0;
777
778/* Third argument to my_get_expression. */
779#define GE_NO_PREFIX 0
780#define GE_IMM_PREFIX 1
781#define GE_OPT_PREFIX 2
782/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
783 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
784#define GE_OPT_PREFIX_BIG 3
785
786static int
787my_get_expression (expressionS * ep, char ** str, int prefix_mode)
788{
789 char * save_in;
790 segT seg;
791
792 /* In unified syntax, all prefixes are optional. */
793 if (unified_syntax)
794 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
795 : GE_OPT_PREFIX;
796
797 switch (prefix_mode)
798 {
799 case GE_NO_PREFIX: break;
800 case GE_IMM_PREFIX:
801 if (!is_immediate_prefix (**str))
802 {
803 inst.error = _("immediate expression requires a # prefix");
804 return FAIL;
805 }
806 (*str)++;
807 break;
808 case GE_OPT_PREFIX:
809 case GE_OPT_PREFIX_BIG:
810 if (is_immediate_prefix (**str))
811 (*str)++;
812 break;
813 default: abort ();
814 }
815
816 memset (ep, 0, sizeof (expressionS));
817
818 save_in = input_line_pointer;
819 input_line_pointer = *str;
820 in_my_get_expression = 1;
821 seg = expression (ep);
822 in_my_get_expression = 0;
823
824 if (ep->X_op == O_illegal)
825 {
826 /* We found a bad expression in md_operand(). */
827 *str = input_line_pointer;
828 input_line_pointer = save_in;
829 if (inst.error == NULL)
830 inst.error = _("bad expression");
831 return 1;
832 }
833
834#ifdef OBJ_AOUT
835 if (seg != absolute_section
836 && seg != text_section
837 && seg != data_section
838 && seg != bss_section
839 && seg != undefined_section)
840 {
841 inst.error = _("bad segment");
842 *str = input_line_pointer;
843 input_line_pointer = save_in;
844 return 1;
845 }
846#endif
847
848 /* Get rid of any bignums now, so that we don't generate an error for which
849 we can't establish a line number later on. Big numbers are never valid
850 in instructions, which is where this routine is always called. */
851 if (prefix_mode != GE_OPT_PREFIX_BIG
852 && (ep->X_op == O_big
853 || (ep->X_add_symbol
854 && (walk_no_bignums (ep->X_add_symbol)
855 || (ep->X_op_symbol
856 && walk_no_bignums (ep->X_op_symbol))))))
857 {
858 inst.error = _("invalid constant");
859 *str = input_line_pointer;
860 input_line_pointer = save_in;
861 return 1;
862 }
863
864 *str = input_line_pointer;
865 input_line_pointer = save_in;
866 return 0;
867}
868
869/* Turn a string in input_line_pointer into a floating point constant
870 of type TYPE, and store the appropriate bytes in *LITP. The number
871 of LITTLENUMS emitted is stored in *SIZEP. An error message is
872 returned, or NULL on OK.
873
874 Note that fp constants aren't represent in the normal way on the ARM.
875 In big endian mode, things are as expected. However, in little endian
876 mode fp constants are big-endian word-wise, and little-endian byte-wise
877 within the words. For example, (double) 1.1 in big endian mode is
878 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
879 the byte sequence 99 99 f1 3f 9a 99 99 99.
880
881 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
882
883char *
884md_atof (int type, char * litP, int * sizeP)
885{
886 int prec;
887 LITTLENUM_TYPE words[MAX_LITTLENUMS];
888 char *t;
889 int i;
890
891 switch (type)
892 {
893 case 'f':
894 case 'F':
895 case 's':
896 case 'S':
897 prec = 2;
898 break;
899
900 case 'd':
901 case 'D':
902 case 'r':
903 case 'R':
904 prec = 4;
905 break;
906
907 case 'x':
908 case 'X':
909 prec = 6;
910 break;
911
912 case 'p':
913 case 'P':
914 prec = 6;
915 break;
916
917 default:
918 *sizeP = 0;
919 return _("bad call to MD_ATOF()");
920 }
921
922 t = atof_ieee (input_line_pointer, type, words);
923 if (t)
924 input_line_pointer = t;
925 *sizeP = prec * 2;
926
927 if (target_big_endian)
928 {
929 for (i = 0; i < prec; i++)
930 {
931 md_number_to_chars (litP, (valueT) words[i], 2);
932 litP += 2;
933 }
934 }
935 else
936 {
937 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
938 for (i = prec - 1; i >= 0; i--)
939 {
940 md_number_to_chars (litP, (valueT) words[i], 2);
941 litP += 2;
942 }
943 else
944 /* For a 4 byte float the order of elements in `words' is 1 0.
945 For an 8 byte float the order is 1 0 3 2. */
946 for (i = 0; i < prec; i += 2)
947 {
948 md_number_to_chars (litP, (valueT) words[i + 1], 2);
949 md_number_to_chars (litP + 2, (valueT) words[i], 2);
950 litP += 4;
951 }
952 }
953
954 return 0;
955}
956
957/* We handle all bad expressions here, so that we can report the faulty
958 instruction in the error message. */
959void
960md_operand (expressionS * expr)
961{
962 if (in_my_get_expression)
963 expr->X_op = O_illegal;
964}
965
966/* Immediate values. */
967
968/* Generic immediate-value read function for use in directives.
969 Accepts anything that 'expression' can fold to a constant.
970 *val receives the number. */
971#ifdef OBJ_ELF
972static int
973immediate_for_directive (int *val)
974{
975 expressionS exp;
976 exp.X_op = O_illegal;
977
978 if (is_immediate_prefix (*input_line_pointer))
979 {
980 input_line_pointer++;
981 expression (&exp);
982 }
983
984 if (exp.X_op != O_constant)
985 {
986 as_bad (_("expected #constant"));
987 ignore_rest_of_line ();
988 return FAIL;
989 }
990 *val = exp.X_add_number;
991 return SUCCESS;
992}
993#endif
994
995/* Register parsing. */
996
997/* Generic register parser. CCP points to what should be the
998 beginning of a register name. If it is indeed a valid register
999 name, advance CCP over it and return the reg_entry structure;
1000 otherwise return NULL. Does not issue diagnostics. */
1001
1002static struct reg_entry *
1003arm_reg_parse_multi (char **ccp)
1004{
1005 char *start = *ccp;
1006 char *p;
1007 struct reg_entry *reg;
1008
1009#ifdef REGISTER_PREFIX
1010 if (*start != REGISTER_PREFIX)
1011 return NULL;
1012 start++;
1013#endif
1014#ifdef OPTIONAL_REGISTER_PREFIX
1015 if (*start == OPTIONAL_REGISTER_PREFIX)
1016 start++;
1017#endif
1018
1019 p = start;
1020 if (!ISALPHA (*p) || !is_name_beginner (*p))
1021 return NULL;
1022
1023 do
1024 p++;
1025 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1026
1027 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1028
1029 if (!reg)
1030 return NULL;
1031
1032 *ccp = p;
1033 return reg;
1034}
1035
1036static int
1037arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1038 enum arm_reg_type type)
1039{
1040 /* Alternative syntaxes are accepted for a few register classes. */
1041 switch (type)
1042 {
1043 case REG_TYPE_MVF:
1044 case REG_TYPE_MVD:
1045 case REG_TYPE_MVFX:
1046 case REG_TYPE_MVDX:
1047 /* Generic coprocessor register names are allowed for these. */
1048 if (reg && reg->type == REG_TYPE_CN)
1049 return reg->number;
1050 break;
1051
1052 case REG_TYPE_CP:
1053 /* For backward compatibility, a bare number is valid here. */
1054 {
1055 unsigned long processor = strtoul (start, ccp, 10);
1056 if (*ccp != start && processor <= 15)
1057 return processor;
1058 }
1059
1060 case REG_TYPE_MMXWC:
1061 /* WC includes WCG. ??? I'm not sure this is true for all
1062 instructions that take WC registers. */
1063 if (reg && reg->type == REG_TYPE_MMXWCG)
1064 return reg->number;
1065 break;
1066
1067 default:
1068 break;
1069 }
1070
1071 return FAIL;
1072}
1073
1074/* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1075 return value is the register number or FAIL. */
1076
1077static int
1078arm_reg_parse (char **ccp, enum arm_reg_type type)
1079{
1080 char *start = *ccp;
1081 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1082 int ret;
1083
1084 /* Do not allow a scalar (reg+index) to parse as a register. */
1085 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1086 return FAIL;
1087
1088 if (reg && reg->type == type)
1089 return reg->number;
1090
1091 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1092 return ret;
1093
1094 *ccp = start;
1095 return FAIL;
1096}
1097
1098/* Parse a Neon type specifier. *STR should point at the leading '.'
1099 character. Does no verification at this stage that the type fits the opcode
1100 properly. E.g.,
1101
1102 .i32.i32.s16
1103 .s32.f32
1104 .u16
1105
1106 Can all be legally parsed by this function.
1107
1108 Fills in neon_type struct pointer with parsed information, and updates STR
1109 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1110 type, FAIL if not. */
1111
1112static int
1113parse_neon_type (struct neon_type *type, char **str)
1114{
1115 char *ptr = *str;
1116
1117 if (type)
1118 type->elems = 0;
1119
1120 while (type->elems < NEON_MAX_TYPE_ELS)
1121 {
1122 enum neon_el_type thistype = NT_untyped;
1123 unsigned thissize = -1u;
1124
1125 if (*ptr != '.')
1126 break;
1127
1128 ptr++;
1129
1130 /* Just a size without an explicit type. */
1131 if (ISDIGIT (*ptr))
1132 goto parsesize;
1133
1134 switch (TOLOWER (*ptr))
1135 {
1136 case 'i': thistype = NT_integer; break;
1137 case 'f': thistype = NT_float; break;
1138 case 'p': thistype = NT_poly; break;
1139 case 's': thistype = NT_signed; break;
1140 case 'u': thistype = NT_unsigned; break;
1141 case 'd':
1142 thistype = NT_float;
1143 thissize = 64;
1144 ptr++;
1145 goto done;
1146 default:
1147 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1148 return FAIL;
1149 }
1150
1151 ptr++;
1152
1153 /* .f is an abbreviation for .f32. */
1154 if (thistype == NT_float && !ISDIGIT (*ptr))
1155 thissize = 32;
1156 else
1157 {
1158 parsesize:
1159 thissize = strtoul (ptr, &ptr, 10);
1160
1161 if (thissize != 8 && thissize != 16 && thissize != 32
1162 && thissize != 64)
1163 {
1164 as_bad (_("bad size %d in type specifier"), thissize);
1165 return FAIL;
1166 }
1167 }
1168
1169 done:
1170 if (type)
1171 {
1172 type->el[type->elems].type = thistype;
1173 type->el[type->elems].size = thissize;
1174 type->elems++;
1175 }
1176 }
1177
1178 /* Empty/missing type is not a successful parse. */
1179 if (type->elems == 0)
1180 return FAIL;
1181
1182 *str = ptr;
1183
1184 return SUCCESS;
1185}
1186
1187/* Errors may be set multiple times during parsing or bit encoding
1188 (particularly in the Neon bits), but usually the earliest error which is set
1189 will be the most meaningful. Avoid overwriting it with later (cascading)
1190 errors by calling this function. */
1191
1192static void
1193first_error (const char *err)
1194{
1195 if (!inst.error)
1196 inst.error = err;
1197}
1198
1199/* Parse a single type, e.g. ".s32", leading period included. */
1200static int
1201parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1202{
1203 char *str = *ccp;
1204 struct neon_type optype;
1205
1206 if (*str == '.')
1207 {
1208 if (parse_neon_type (&optype, &str) == SUCCESS)
1209 {
1210 if (optype.elems == 1)
1211 *vectype = optype.el[0];
1212 else
1213 {
1214 first_error (_("only one type should be specified for operand"));
1215 return FAIL;
1216 }
1217 }
1218 else
1219 {
1220 first_error (_("vector type expected"));
1221 return FAIL;
1222 }
1223 }
1224 else
1225 return FAIL;
1226
1227 *ccp = str;
1228
1229 return SUCCESS;
1230}
1231
1232/* Special meanings for indices (which have a range of 0-7), which will fit into
1233 a 4-bit integer. */
1234
1235#define NEON_ALL_LANES 15
1236#define NEON_INTERLEAVE_LANES 14
1237
1238/* Parse either a register or a scalar, with an optional type. Return the
1239 register number, and optionally fill in the actual type of the register
1240 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1241 type/index information in *TYPEINFO. */
1242
1243static int
1244parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1245 enum arm_reg_type *rtype,
1246 struct neon_typed_alias *typeinfo)
1247{
1248 char *str = *ccp;
1249 struct reg_entry *reg = arm_reg_parse_multi (&str);
1250 struct neon_typed_alias atype;
1251 struct neon_type_el parsetype;
1252
1253 atype.defined = 0;
1254 atype.index = -1;
1255 atype.eltype.type = NT_invtype;
1256 atype.eltype.size = -1;
1257
1258 /* Try alternate syntax for some types of register. Note these are mutually
1259 exclusive with the Neon syntax extensions. */
1260 if (reg == NULL)
1261 {
1262 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1263 if (altreg != FAIL)
1264 *ccp = str;
1265 if (typeinfo)
1266 *typeinfo = atype;
1267 return altreg;
1268 }
1269
1270 /* Undo polymorphism when a set of register types may be accepted. */
1271 if ((type == REG_TYPE_NDQ
1272 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1273 || (type == REG_TYPE_VFSD
1274 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1275 || (type == REG_TYPE_NSDQ
1276 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1277 || reg->type == REG_TYPE_NQ))
1278 || (type == REG_TYPE_MMXWC
1279 && (reg->type == REG_TYPE_MMXWCG)))
1280 type = reg->type;
1281
1282 if (type != reg->type)
1283 return FAIL;
1284
1285 if (reg->neon)
1286 atype = *reg->neon;
1287
1288 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1289 {
1290 if ((atype.defined & NTA_HASTYPE) != 0)
1291 {
1292 first_error (_("can't redefine type for operand"));
1293 return FAIL;
1294 }
1295 atype.defined |= NTA_HASTYPE;
1296 atype.eltype = parsetype;
1297 }
1298
1299 if (skip_past_char (&str, '[') == SUCCESS)
1300 {
1301 if (type != REG_TYPE_VFD)
1302 {
1303 first_error (_("only D registers may be indexed"));
1304 return FAIL;
1305 }
1306
1307 if ((atype.defined & NTA_HASINDEX) != 0)
1308 {
1309 first_error (_("can't change index for operand"));
1310 return FAIL;
1311 }
1312
1313 atype.defined |= NTA_HASINDEX;
1314
1315 if (skip_past_char (&str, ']') == SUCCESS)
1316 atype.index = NEON_ALL_LANES;
1317 else
1318 {
1319 expressionS exp;
1320
1321 my_get_expression (&exp, &str, GE_NO_PREFIX);
1322
1323 if (exp.X_op != O_constant)
1324 {
1325 first_error (_("constant expression required"));
1326 return FAIL;
1327 }
1328
1329 if (skip_past_char (&str, ']') == FAIL)
1330 return FAIL;
1331
1332 atype.index = exp.X_add_number;
1333 }
1334 }
1335
1336 if (typeinfo)
1337 *typeinfo = atype;
1338
1339 if (rtype)
1340 *rtype = type;
1341
1342 *ccp = str;
1343
1344 return reg->number;
1345}
1346
1347/* Like arm_reg_parse, but allow allow the following extra features:
1348 - If RTYPE is non-zero, return the (possibly restricted) type of the
1349 register (e.g. Neon double or quad reg when either has been requested).
1350 - If this is a Neon vector type with additional type information, fill
1351 in the struct pointed to by VECTYPE (if non-NULL).
1352 This function will fault on encountering a scalar.
1353*/
1354
1355static int
1356arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1357 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1358{
1359 struct neon_typed_alias atype;
1360 char *str = *ccp;
1361 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1362
1363 if (reg == FAIL)
1364 return FAIL;
1365
1366 /* Do not allow a scalar (reg+index) to parse as a register. */
1367 if ((atype.defined & NTA_HASINDEX) != 0)
1368 {
1369 first_error (_("register operand expected, but got scalar"));
1370 return FAIL;
1371 }
1372
1373 if (vectype)
1374 *vectype = atype.eltype;
1375
1376 *ccp = str;
1377
1378 return reg;
1379}
1380
1381#define NEON_SCALAR_REG(X) ((X) >> 4)
1382#define NEON_SCALAR_INDEX(X) ((X) & 15)
1383
1384/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1385 have enough information to be able to do a good job bounds-checking. So, we
1386 just do easy checks here, and do further checks later. */
1387
1388static int
1389parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1390{
1391 int reg;
1392 char *str = *ccp;
1393 struct neon_typed_alias atype;
1394
1395 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1396
1397 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1398 return FAIL;
1399
1400 if (atype.index == NEON_ALL_LANES)
1401 {
1402 first_error (_("scalar must have an index"));
1403 return FAIL;
1404 }
1405 else if (atype.index >= 64 / elsize)
1406 {
1407 first_error (_("scalar index out of range"));
1408 return FAIL;
1409 }
1410
1411 if (type)
1412 *type = atype.eltype;
1413
1414 *ccp = str;
1415
1416 return reg * 16 + atype.index;
1417}
1418
1419/* Parse an ARM register list. Returns the bitmask, or FAIL. */
1420static long
1421parse_reg_list (char ** strp)
1422{
1423 char * str = * strp;
1424 long range = 0;
1425 int another_range;
1426
1427 /* We come back here if we get ranges concatenated by '+' or '|'. */
1428 do
1429 {
1430 another_range = 0;
1431
1432 if (*str == '{')
1433 {
1434 int in_range = 0;
1435 int cur_reg = -1;
1436
1437 str++;
1438 do
1439 {
1440 int reg;
1441
1442 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1443 {
1444 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1445 return FAIL;
1446 }
1447
1448 if (in_range)
1449 {
1450 int i;
1451
1452 if (reg <= cur_reg)
1453 {
1454 first_error (_("bad range in register list"));
1455 return FAIL;
1456 }
1457
1458 for (i = cur_reg + 1; i < reg; i++)
1459 {
1460 if (range & (1 << i))
1461 as_tsktsk
1462 (_("Warning: duplicated register (r%d) in register list"),
1463 i);
1464 else
1465 range |= 1 << i;
1466 }
1467 in_range = 0;
1468 }
1469
1470 if (range & (1 << reg))
1471 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1472 reg);
1473 else if (reg <= cur_reg)
1474 as_tsktsk (_("Warning: register range not in ascending order"));
1475
1476 range |= 1 << reg;
1477 cur_reg = reg;
1478 }
1479 while (skip_past_comma (&str) != FAIL
1480 || (in_range = 1, *str++ == '-'));
1481 str--;
1482
1483 if (*str++ != '}')
1484 {
1485 first_error (_("missing `}'"));
1486 return FAIL;
1487 }
1488 }
1489 else
1490 {
1491 expressionS expr;
1492
1493 if (my_get_expression (&expr, &str, GE_NO_PREFIX))
1494 return FAIL;
1495
1496 if (expr.X_op == O_constant)
1497 {
1498 if (expr.X_add_number
1499 != (expr.X_add_number & 0x0000ffff))
1500 {
1501 inst.error = _("invalid register mask");
1502 return FAIL;
1503 }
1504
1505 if ((range & expr.X_add_number) != 0)
1506 {
1507 int regno = range & expr.X_add_number;
1508
1509 regno &= -regno;
1510 regno = (1 << regno) - 1;
1511 as_tsktsk
1512 (_("Warning: duplicated register (r%d) in register list"),
1513 regno);
1514 }
1515
1516 range |= expr.X_add_number;
1517 }
1518 else
1519 {
1520 if (inst.reloc.type != 0)
1521 {
1522 inst.error = _("expression too complex");
1523 return FAIL;
1524 }
1525
1526 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
1527 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1528 inst.reloc.pc_rel = 0;
1529 }
1530 }
1531
1532 if (*str == '|' || *str == '+')
1533 {
1534 str++;
1535 another_range = 1;
1536 }
1537 }
1538 while (another_range);
1539
1540 *strp = str;
1541 return range;
1542}
1543
1544/* Types of registers in a list. */
1545
1546enum reg_list_els
1547{
1548 REGLIST_VFP_S,
1549 REGLIST_VFP_D,
1550 REGLIST_NEON_D
1551};
1552
1553/* Parse a VFP register list. If the string is invalid return FAIL.
1554 Otherwise return the number of registers, and set PBASE to the first
1555 register. Parses registers of type ETYPE.
1556 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1557 - Q registers can be used to specify pairs of D registers
1558 - { } can be omitted from around a singleton register list
1559 FIXME: This is not implemented, as it would require backtracking in
1560 some cases, e.g.:
1561 vtbl.8 d3,d4,d5
1562 This could be done (the meaning isn't really ambiguous), but doesn't
1563 fit in well with the current parsing framework.
1564 - 32 D registers may be used (also true for VFPv3).
1565 FIXME: Types are ignored in these register lists, which is probably a
1566 bug. */
1567
1568static int
1569parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1570{
1571 char *str = *ccp;
1572 int base_reg;
1573 int new_base;
1574 enum arm_reg_type regtype = 0;
1575 int max_regs = 0;
1576 int count = 0;
1577 int warned = 0;
1578 unsigned long mask = 0;
1579 int i;
1580
1581 if (*str != '{')
1582 {
1583 inst.error = _("expecting {");
1584 return FAIL;
1585 }
1586
1587 str++;
1588
1589 switch (etype)
1590 {
1591 case REGLIST_VFP_S:
1592 regtype = REG_TYPE_VFS;
1593 max_regs = 32;
1594 break;
1595
1596 case REGLIST_VFP_D:
1597 regtype = REG_TYPE_VFD;
1598 break;
1599
1600 case REGLIST_NEON_D:
1601 regtype = REG_TYPE_NDQ;
1602 break;
1603 }
1604
1605 if (etype != REGLIST_VFP_S)
1606 {
1607 /* VFPv3 allows 32 D registers. */
1608 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
1609 {
1610 max_regs = 32;
1611 if (thumb_mode)
1612 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1613 fpu_vfp_ext_v3);
1614 else
1615 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1616 fpu_vfp_ext_v3);
1617 }
1618 else
1619 max_regs = 16;
1620 }
1621
1622 base_reg = max_regs;
1623
1624 do
1625 {
1626 int setmask = 1, addregs = 1;
1627
1628 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1629
1630 if (new_base == FAIL)
1631 {
1632 first_error (_(reg_expected_msgs[regtype]));
1633 return FAIL;
1634 }
1635
1636 if (new_base >= max_regs)
1637 {
1638 first_error (_("register out of range in list"));
1639 return FAIL;
1640 }
1641
1642 /* Note: a value of 2 * n is returned for the register Q<n>. */
1643 if (regtype == REG_TYPE_NQ)
1644 {
1645 setmask = 3;
1646 addregs = 2;
1647 }
1648
1649 if (new_base < base_reg)
1650 base_reg = new_base;
1651
1652 if (mask & (setmask << new_base))
1653 {
1654 first_error (_("invalid register list"));
1655 return FAIL;
1656 }
1657
1658 if ((mask >> new_base) != 0 && ! warned)
1659 {
1660 as_tsktsk (_("register list not in ascending order"));
1661 warned = 1;
1662 }
1663
1664 mask |= setmask << new_base;
1665 count += addregs;
1666
1667 if (*str == '-') /* We have the start of a range expression */
1668 {
1669 int high_range;
1670
1671 str++;
1672
1673 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1674 == FAIL)
1675 {
1676 inst.error = gettext (reg_expected_msgs[regtype]);
1677 return FAIL;
1678 }
1679
1680 if (high_range >= max_regs)
1681 {
1682 first_error (_("register out of range in list"));
1683 return FAIL;
1684 }
1685
1686 if (regtype == REG_TYPE_NQ)
1687 high_range = high_range + 1;
1688
1689 if (high_range <= new_base)
1690 {
1691 inst.error = _("register range not in ascending order");
1692 return FAIL;
1693 }
1694
1695 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1696 {
1697 if (mask & (setmask << new_base))
1698 {
1699 inst.error = _("invalid register list");
1700 return FAIL;
1701 }
1702
1703 mask |= setmask << new_base;
1704 count += addregs;
1705 }
1706 }
1707 }
1708 while (skip_past_comma (&str) != FAIL);
1709
1710 str++;
1711
1712 /* Sanity check -- should have raised a parse error above. */
1713 if (count == 0 || count > max_regs)
1714 abort ();
1715
1716 *pbase = base_reg;
1717
1718 /* Final test -- the registers must be consecutive. */
1719 mask >>= base_reg;
1720 for (i = 0; i < count; i++)
1721 {
1722 if ((mask & (1u << i)) == 0)
1723 {
1724 inst.error = _("non-contiguous register range");
1725 return FAIL;
1726 }
1727 }
1728
1729 *ccp = str;
1730
1731 return count;
1732}
1733
1734/* True if two alias types are the same. */
1735
1736static int
1737neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1738{
1739 if (!a && !b)
1740 return 1;
1741
1742 if (!a || !b)
1743 return 0;
1744
1745 if (a->defined != b->defined)
1746 return 0;
1747
1748 if ((a->defined & NTA_HASTYPE) != 0
1749 && (a->eltype.type != b->eltype.type
1750 || a->eltype.size != b->eltype.size))
1751 return 0;
1752
1753 if ((a->defined & NTA_HASINDEX) != 0
1754 && (a->index != b->index))
1755 return 0;
1756
1757 return 1;
1758}
1759
1760/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1761 The base register is put in *PBASE.
1762 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1763 the return value.
1764 The register stride (minus one) is put in bit 4 of the return value.
1765 Bits [6:5] encode the list length (minus one).
1766 The type of the list elements is put in *ELTYPE, if non-NULL. */
1767
1768#define NEON_LANE(X) ((X) & 0xf)
1769#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1770#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1771
1772static int
1773parse_neon_el_struct_list (char **str, unsigned *pbase,
1774 struct neon_type_el *eltype)
1775{
1776 char *ptr = *str;
1777 int base_reg = -1;
1778 int reg_incr = -1;
1779 int count = 0;
1780 int lane = -1;
1781 int leading_brace = 0;
1782 enum arm_reg_type rtype = REG_TYPE_NDQ;
1783 int addregs = 1;
1784 const char *const incr_error = "register stride must be 1 or 2";
1785 const char *const type_error = "mismatched element/structure types in list";
1786 struct neon_typed_alias firsttype;
1787
1788 if (skip_past_char (&ptr, '{') == SUCCESS)
1789 leading_brace = 1;
1790
1791 do
1792 {
1793 struct neon_typed_alias atype;
1794 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1795
1796 if (getreg == FAIL)
1797 {
1798 first_error (_(reg_expected_msgs[rtype]));
1799 return FAIL;
1800 }
1801
1802 if (base_reg == -1)
1803 {
1804 base_reg = getreg;
1805 if (rtype == REG_TYPE_NQ)
1806 {
1807 reg_incr = 1;
1808 addregs = 2;
1809 }
1810 firsttype = atype;
1811 }
1812 else if (reg_incr == -1)
1813 {
1814 reg_incr = getreg - base_reg;
1815 if (reg_incr < 1 || reg_incr > 2)
1816 {
1817 first_error (_(incr_error));
1818 return FAIL;
1819 }
1820 }
1821 else if (getreg != base_reg + reg_incr * count)
1822 {
1823 first_error (_(incr_error));
1824 return FAIL;
1825 }
1826
1827 if (!neon_alias_types_same (&atype, &firsttype))
1828 {
1829 first_error (_(type_error));
1830 return FAIL;
1831 }
1832
1833 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1834 modes. */
1835 if (ptr[0] == '-')
1836 {
1837 struct neon_typed_alias htype;
1838 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1839 if (lane == -1)
1840 lane = NEON_INTERLEAVE_LANES;
1841 else if (lane != NEON_INTERLEAVE_LANES)
1842 {
1843 first_error (_(type_error));
1844 return FAIL;
1845 }
1846 if (reg_incr == -1)
1847 reg_incr = 1;
1848 else if (reg_incr != 1)
1849 {
1850 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1851 return FAIL;
1852 }
1853 ptr++;
1854 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
1855 if (hireg == FAIL)
1856 {
1857 first_error (_(reg_expected_msgs[rtype]));
1858 return FAIL;
1859 }
1860 if (!neon_alias_types_same (&htype, &firsttype))
1861 {
1862 first_error (_(type_error));
1863 return FAIL;
1864 }
1865 count += hireg + dregs - getreg;
1866 continue;
1867 }
1868
1869 /* If we're using Q registers, we can't use [] or [n] syntax. */
1870 if (rtype == REG_TYPE_NQ)
1871 {
1872 count += 2;
1873 continue;
1874 }
1875
1876 if ((atype.defined & NTA_HASINDEX) != 0)
1877 {
1878 if (lane == -1)
1879 lane = atype.index;
1880 else if (lane != atype.index)
1881 {
1882 first_error (_(type_error));
1883 return FAIL;
1884 }
1885 }
1886 else if (lane == -1)
1887 lane = NEON_INTERLEAVE_LANES;
1888 else if (lane != NEON_INTERLEAVE_LANES)
1889 {
1890 first_error (_(type_error));
1891 return FAIL;
1892 }
1893 count++;
1894 }
1895 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
1896
1897 /* No lane set by [x]. We must be interleaving structures. */
1898 if (lane == -1)
1899 lane = NEON_INTERLEAVE_LANES;
1900
1901 /* Sanity check. */
1902 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
1903 || (count > 1 && reg_incr == -1))
1904 {
1905 first_error (_("error parsing element/structure list"));
1906 return FAIL;
1907 }
1908
1909 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
1910 {
1911 first_error (_("expected }"));
1912 return FAIL;
1913 }
1914
1915 if (reg_incr == -1)
1916 reg_incr = 1;
1917
1918 if (eltype)
1919 *eltype = firsttype.eltype;
1920
1921 *pbase = base_reg;
1922 *str = ptr;
1923
1924 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
1925}
1926
1927/* Parse an explicit relocation suffix on an expression. This is
1928 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1929 arm_reloc_hsh contains no entries, so this function can only
1930 succeed if there is no () after the word. Returns -1 on error,
1931 BFD_RELOC_UNUSED if there wasn't any suffix. */
1932static int
1933parse_reloc (char **str)
1934{
1935 struct reloc_entry *r;
1936 char *p, *q;
1937
1938 if (**str != '(')
1939 return BFD_RELOC_UNUSED;
1940
1941 p = *str + 1;
1942 q = p;
1943
1944 while (*q && *q != ')' && *q != ',')
1945 q++;
1946 if (*q != ')')
1947 return -1;
1948
1949 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
1950 return -1;
1951
1952 *str = q + 1;
1953 return r->reloc;
1954}
1955
1956/* Directives: register aliases. */
1957
1958static struct reg_entry *
1959insert_reg_alias (char *str, int number, int type)
1960{
1961 struct reg_entry *new;
1962 const char *name;
1963
1964 if ((new = hash_find (arm_reg_hsh, str)) != 0)
1965 {
1966 if (new->builtin)
1967 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
1968
1969 /* Only warn about a redefinition if it's not defined as the
1970 same register. */
1971 else if (new->number != number || new->type != type)
1972 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1973
1974 return 0;
1975 }
1976
1977 name = xstrdup (str);
1978 new = xmalloc (sizeof (struct reg_entry));
1979
1980 new->name = name;
1981 new->number = number;
1982 new->type = type;
1983 new->builtin = FALSE;
1984 new->neon = NULL;
1985
1986 if (hash_insert (arm_reg_hsh, name, (PTR) new))
1987 abort ();
1988
1989 return new;
1990}
1991
1992static void
1993insert_neon_reg_alias (char *str, int number, int type,
1994 struct neon_typed_alias *atype)
1995{
1996 struct reg_entry *reg = insert_reg_alias (str, number, type);
1997
1998 if (!reg)
1999 {
2000 first_error (_("attempt to redefine typed alias"));
2001 return;
2002 }
2003
2004 if (atype)
2005 {
2006 reg->neon = xmalloc (sizeof (struct neon_typed_alias));
2007 *reg->neon = *atype;
2008 }
2009}
2010
2011/* Look for the .req directive. This is of the form:
2012
2013 new_register_name .req existing_register_name
2014
2015 If we find one, or if it looks sufficiently like one that we want to
2016 handle any error here, return non-zero. Otherwise return zero. */
2017
2018static int
2019create_register_alias (char * newname, char *p)
2020{
2021 struct reg_entry *old;
2022 char *oldname, *nbuf;
2023 size_t nlen;
2024
2025 /* The input scrubber ensures that whitespace after the mnemonic is
2026 collapsed to single spaces. */
2027 oldname = p;
2028 if (strncmp (oldname, " .req ", 6) != 0)
2029 return 0;
2030
2031 oldname += 6;
2032 if (*oldname == '\0')
2033 return 0;
2034
2035 old = hash_find (arm_reg_hsh, oldname);
2036 if (!old)
2037 {
2038 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2039 return 1;
2040 }
2041
2042 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2043 the desired alias name, and p points to its end. If not, then
2044 the desired alias name is in the global original_case_string. */
2045#ifdef TC_CASE_SENSITIVE
2046 nlen = p - newname;
2047#else
2048 newname = original_case_string;
2049 nlen = strlen (newname);
2050#endif
2051
2052 nbuf = alloca (nlen + 1);
2053 memcpy (nbuf, newname, nlen);
2054 nbuf[nlen] = '\0';
2055
2056 /* Create aliases under the new name as stated; an all-lowercase
2057 version of the new name; and an all-uppercase version of the new
2058 name. */
2059 insert_reg_alias (nbuf, old->number, old->type);
2060
2061 for (p = nbuf; *p; p++)
2062 *p = TOUPPER (*p);
2063
2064 if (strncmp (nbuf, newname, nlen))
2065 insert_reg_alias (nbuf, old->number, old->type);
2066
2067 for (p = nbuf; *p; p++)
2068 *p = TOLOWER (*p);
2069
2070 if (strncmp (nbuf, newname, nlen))
2071 insert_reg_alias (nbuf, old->number, old->type);
2072
2073 return 1;
2074}
2075
2076/* Create a Neon typed/indexed register alias using directives, e.g.:
2077 X .dn d5.s32[1]
2078 Y .qn 6.s16
2079 Z .dn d7
2080 T .dn Z[0]
2081 These typed registers can be used instead of the types specified after the
2082 Neon mnemonic, so long as all operands given have types. Types can also be
2083 specified directly, e.g.:
2084 vadd d0.s32, d1.s32, d2.s32
2085*/
2086
2087static int
2088create_neon_reg_alias (char *newname, char *p)
2089{
2090 enum arm_reg_type basetype;
2091 struct reg_entry *basereg;
2092 struct reg_entry mybasereg;
2093 struct neon_type ntype;
2094 struct neon_typed_alias typeinfo;
2095 char *namebuf, *nameend;
2096 int namelen;
2097
2098 typeinfo.defined = 0;
2099 typeinfo.eltype.type = NT_invtype;
2100 typeinfo.eltype.size = -1;
2101 typeinfo.index = -1;
2102
2103 nameend = p;
2104
2105 if (strncmp (p, " .dn ", 5) == 0)
2106 basetype = REG_TYPE_VFD;
2107 else if (strncmp (p, " .qn ", 5) == 0)
2108 basetype = REG_TYPE_NQ;
2109 else
2110 return 0;
2111
2112 p += 5;
2113
2114 if (*p == '\0')
2115 return 0;
2116
2117 basereg = arm_reg_parse_multi (&p);
2118
2119 if (basereg && basereg->type != basetype)
2120 {
2121 as_bad (_("bad type for register"));
2122 return 0;
2123 }
2124
2125 if (basereg == NULL)
2126 {
2127 expressionS exp;
2128 /* Try parsing as an integer. */
2129 my_get_expression (&exp, &p, GE_NO_PREFIX);
2130 if (exp.X_op != O_constant)
2131 {
2132 as_bad (_("expression must be constant"));
2133 return 0;
2134 }
2135 basereg = &mybasereg;
2136 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2137 : exp.X_add_number;
2138 basereg->neon = 0;
2139 }
2140
2141 if (basereg->neon)
2142 typeinfo = *basereg->neon;
2143
2144 if (parse_neon_type (&ntype, &p) == SUCCESS)
2145 {
2146 /* We got a type. */
2147 if (typeinfo.defined & NTA_HASTYPE)
2148 {
2149 as_bad (_("can't redefine the type of a register alias"));
2150 return 0;
2151 }
2152
2153 typeinfo.defined |= NTA_HASTYPE;
2154 if (ntype.elems != 1)
2155 {
2156 as_bad (_("you must specify a single type only"));
2157 return 0;
2158 }
2159 typeinfo.eltype = ntype.el[0];
2160 }
2161
2162 if (skip_past_char (&p, '[') == SUCCESS)
2163 {
2164 expressionS exp;
2165 /* We got a scalar index. */
2166
2167 if (typeinfo.defined & NTA_HASINDEX)
2168 {
2169 as_bad (_("can't redefine the index of a scalar alias"));
2170 return 0;
2171 }
2172
2173 my_get_expression (&exp, &p, GE_NO_PREFIX);
2174
2175 if (exp.X_op != O_constant)
2176 {
2177 as_bad (_("scalar index must be constant"));
2178 return 0;
2179 }
2180
2181 typeinfo.defined |= NTA_HASINDEX;
2182 typeinfo.index = exp.X_add_number;
2183
2184 if (skip_past_char (&p, ']') == FAIL)
2185 {
2186 as_bad (_("expecting ]"));
2187 return 0;
2188 }
2189 }
2190
2191 namelen = nameend - newname;
2192 namebuf = alloca (namelen + 1);
2193 strncpy (namebuf, newname, namelen);
2194 namebuf[namelen] = '\0';
2195
2196 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2197 typeinfo.defined != 0 ? &typeinfo : NULL);
2198
2199 /* Insert name in all uppercase. */
2200 for (p = namebuf; *p; p++)
2201 *p = TOUPPER (*p);
2202
2203 if (strncmp (namebuf, newname, namelen))
2204 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2205 typeinfo.defined != 0 ? &typeinfo : NULL);
2206
2207 /* Insert name in all lowercase. */
2208 for (p = namebuf; *p; p++)
2209 *p = TOLOWER (*p);
2210
2211 if (strncmp (namebuf, newname, namelen))
2212 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2213 typeinfo.defined != 0 ? &typeinfo : NULL);
2214
2215 return 1;
2216}
2217
2218/* Should never be called, as .req goes between the alias and the
2219 register name, not at the beginning of the line. */
2220static void
2221s_req (int a ATTRIBUTE_UNUSED)
2222{
2223 as_bad (_("invalid syntax for .req directive"));
2224}
2225
2226static void
2227s_dn (int a ATTRIBUTE_UNUSED)
2228{
2229 as_bad (_("invalid syntax for .dn directive"));
2230}
2231
2232static void
2233s_qn (int a ATTRIBUTE_UNUSED)
2234{
2235 as_bad (_("invalid syntax for .qn directive"));
2236}
2237
2238/* The .unreq directive deletes an alias which was previously defined
2239 by .req. For example:
2240
2241 my_alias .req r11
2242 .unreq my_alias */
2243
2244static void
2245s_unreq (int a ATTRIBUTE_UNUSED)
2246{
2247 char * name;
2248 char saved_char;
2249
2250 name = input_line_pointer;
2251
2252 while (*input_line_pointer != 0
2253 && *input_line_pointer != ' '
2254 && *input_line_pointer != '\n')
2255 ++input_line_pointer;
2256
2257 saved_char = *input_line_pointer;
2258 *input_line_pointer = 0;
2259
2260 if (!*name)
2261 as_bad (_("invalid syntax for .unreq directive"));
2262 else
2263 {
2264 struct reg_entry *reg = hash_find (arm_reg_hsh, name);
2265
2266 if (!reg)
2267 as_bad (_("unknown register alias '%s'"), name);
2268 else if (reg->builtin)
2269 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2270 name);
2271 else
2272 {
2273 hash_delete (arm_reg_hsh, name);
2274 free ((char *) reg->name);
2275 if (reg->neon)
2276 free (reg->neon);
2277 free (reg);
2278 }
2279 }
2280
2281 *input_line_pointer = saved_char;
2282 demand_empty_rest_of_line ();
2283}
2284
2285/* Directives: Instruction set selection. */
2286
2287#ifdef OBJ_ELF
2288/* This code is to handle mapping symbols as defined in the ARM ELF spec.
2289 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2290 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2291 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2292
2293static enum mstate mapstate = MAP_UNDEFINED;
2294
2295void
2296mapping_state (enum mstate state)
2297{
2298 symbolS * symbolP;
2299 const char * symname;
2300 int type;
2301
2302 if (mapstate == state)
2303 /* The mapping symbol has already been emitted.
2304 There is nothing else to do. */
2305 return;
2306
2307 mapstate = state;
2308
2309 switch (state)
2310 {
2311 case MAP_DATA:
2312 symname = "$d";
2313 type = BSF_NO_FLAGS;
2314 break;
2315 case MAP_ARM:
2316 symname = "$a";
2317 type = BSF_NO_FLAGS;
2318 break;
2319 case MAP_THUMB:
2320 symname = "$t";
2321 type = BSF_NO_FLAGS;
2322 break;
2323 case MAP_UNDEFINED:
2324 return;
2325 default:
2326 abort ();
2327 }
2328
2329 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2330
2331 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
2332 symbol_table_insert (symbolP);
2333 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2334
2335 switch (state)
2336 {
2337 case MAP_ARM:
2338 THUMB_SET_FUNC (symbolP, 0);
2339 ARM_SET_THUMB (symbolP, 0);
2340 ARM_SET_INTERWORK (symbolP, support_interwork);
2341 break;
2342
2343 case MAP_THUMB:
2344 THUMB_SET_FUNC (symbolP, 1);
2345 ARM_SET_THUMB (symbolP, 1);
2346 ARM_SET_INTERWORK (symbolP, support_interwork);
2347 break;
2348
2349 case MAP_DATA:
2350 default:
2351 return;
2352 }
2353}
2354#else
2355#define mapping_state(x) /* nothing */
2356#endif
2357
2358/* Find the real, Thumb encoded start of a Thumb function. */
2359
2360static symbolS *
2361find_real_start (symbolS * symbolP)
2362{
2363 char * real_start;
2364 const char * name = S_GET_NAME (symbolP);
2365 symbolS * new_target;
2366
2367 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2368#define STUB_NAME ".real_start_of"
2369
2370 if (name == NULL)
2371 abort ();
2372
2373 /* The compiler may generate BL instructions to local labels because
2374 it needs to perform a branch to a far away location. These labels
2375 do not have a corresponding ".real_start_of" label. We check
2376 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2377 the ".real_start_of" convention for nonlocal branches. */
2378 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2379 return symbolP;
2380
2381 real_start = ACONCAT ((STUB_NAME, name, NULL));
2382 new_target = symbol_find (real_start);
2383
2384 if (new_target == NULL)
2385 {
2386 as_warn ("Failed to find real start of function: %s\n", name);
2387 new_target = symbolP;
2388 }
2389
2390 return new_target;
2391}
2392
2393static void
2394opcode_select (int width)
2395{
2396 switch (width)
2397 {
2398 case 16:
2399 if (! thumb_mode)
2400 {
2401 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2402 as_bad (_("selected processor does not support THUMB opcodes"));
2403
2404 thumb_mode = 1;
2405 /* No need to force the alignment, since we will have been
2406 coming from ARM mode, which is word-aligned. */
2407 record_alignment (now_seg, 1);
2408 }
2409 mapping_state (MAP_THUMB);
2410 break;
2411
2412 case 32:
2413 if (thumb_mode)
2414 {
2415 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2416 as_bad (_("selected processor does not support ARM opcodes"));
2417
2418 thumb_mode = 0;
2419
2420 if (!need_pass_2)
2421 frag_align (2, 0, 0);
2422
2423 record_alignment (now_seg, 1);
2424 }
2425 mapping_state (MAP_ARM);
2426 break;
2427
2428 default:
2429 as_bad (_("invalid instruction size selected (%d)"), width);
2430 }
2431}
2432
2433static void
2434s_arm (int ignore ATTRIBUTE_UNUSED)
2435{
2436 opcode_select (32);
2437 demand_empty_rest_of_line ();
2438}
2439
2440static void
2441s_thumb (int ignore ATTRIBUTE_UNUSED)
2442{
2443 opcode_select (16);
2444 demand_empty_rest_of_line ();
2445}
2446
2447static void
2448s_code (int unused ATTRIBUTE_UNUSED)
2449{
2450 int temp;
2451
2452 temp = get_absolute_expression ();
2453 switch (temp)
2454 {
2455 case 16:
2456 case 32:
2457 opcode_select (temp);
2458 break;
2459
2460 default:
2461 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2462 }
2463}
2464
2465static void
2466s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2467{
2468 /* If we are not already in thumb mode go into it, EVEN if
2469 the target processor does not support thumb instructions.
2470 This is used by gcc/config/arm/lib1funcs.asm for example
2471 to compile interworking support functions even if the
2472 target processor should not support interworking. */
2473 if (! thumb_mode)
2474 {
2475 thumb_mode = 2;
2476 record_alignment (now_seg, 1);
2477 }
2478
2479 demand_empty_rest_of_line ();
2480}
2481
2482static void
2483s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2484{
2485 s_thumb (0);
2486
2487 /* The following label is the name/address of the start of a Thumb function.
2488 We need to know this for the interworking support. */
2489 label_is_thumb_function_name = TRUE;
2490}
2491
2492/* Perform a .set directive, but also mark the alias as
2493 being a thumb function. */
2494
2495static void
2496s_thumb_set (int equiv)
2497{
2498 /* XXX the following is a duplicate of the code for s_set() in read.c
2499 We cannot just call that code as we need to get at the symbol that
2500 is created. */
2501 char * name;
2502 char delim;
2503 char * end_name;
2504 symbolS * symbolP;
2505
2506 /* Especial apologies for the random logic:
2507 This just grew, and could be parsed much more simply!
2508 Dean - in haste. */
2509 name = input_line_pointer;
2510 delim = get_symbol_end ();
2511 end_name = input_line_pointer;
2512 *end_name = delim;
2513
2514 if (*input_line_pointer != ',')
2515 {
2516 *end_name = 0;
2517 as_bad (_("expected comma after name \"%s\""), name);
2518 *end_name = delim;
2519 ignore_rest_of_line ();
2520 return;
2521 }
2522
2523 input_line_pointer++;
2524 *end_name = 0;
2525
2526 if (name[0] == '.' && name[1] == '\0')
2527 {
2528 /* XXX - this should not happen to .thumb_set. */
2529 abort ();
2530 }
2531
2532 if ((symbolP = symbol_find (name)) == NULL
2533 && (symbolP = md_undefined_symbol (name)) == NULL)
2534 {
2535#ifndef NO_LISTING
2536 /* When doing symbol listings, play games with dummy fragments living
2537 outside the normal fragment chain to record the file and line info
2538 for this symbol. */
2539 if (listing & LISTING_SYMBOLS)
2540 {
2541 extern struct list_info_struct * listing_tail;
2542 fragS * dummy_frag = xmalloc (sizeof (fragS));
2543
2544 memset (dummy_frag, 0, sizeof (fragS));
2545 dummy_frag->fr_type = rs_fill;
2546 dummy_frag->line = listing_tail;
2547 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2548 dummy_frag->fr_symbol = symbolP;
2549 }
2550 else
2551#endif
2552 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2553
2554#ifdef OBJ_COFF
2555 /* "set" symbols are local unless otherwise specified. */
2556 SF_SET_LOCAL (symbolP);
2557#endif /* OBJ_COFF */
2558 } /* Make a new symbol. */
2559
2560 symbol_table_insert (symbolP);
2561
2562 * end_name = delim;
2563
2564 if (equiv
2565 && S_IS_DEFINED (symbolP)
2566 && S_GET_SEGMENT (symbolP) != reg_section)
2567 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2568
2569 pseudo_set (symbolP);
2570
2571 demand_empty_rest_of_line ();
2572
2573 /* XXX Now we come to the Thumb specific bit of code. */
2574
2575 THUMB_SET_FUNC (symbolP, 1);
2576 ARM_SET_THUMB (symbolP, 1);
2577#if defined OBJ_ELF || defined OBJ_COFF
2578 ARM_SET_INTERWORK (symbolP, support_interwork);
2579#endif
2580}
2581
2582/* Directives: Mode selection. */
2583
2584/* .syntax [unified|divided] - choose the new unified syntax
2585 (same for Arm and Thumb encoding, modulo slight differences in what
2586 can be represented) or the old divergent syntax for each mode. */
2587static void
2588s_syntax (int unused ATTRIBUTE_UNUSED)
2589{
2590 char *name, delim;
2591
2592 name = input_line_pointer;
2593 delim = get_symbol_end ();
2594
2595 if (!strcasecmp (name, "unified"))
2596 unified_syntax = TRUE;
2597 else if (!strcasecmp (name, "divided"))
2598 unified_syntax = FALSE;
2599 else
2600 {
2601 as_bad (_("unrecognized syntax mode \"%s\""), name);
2602 return;
2603 }
2604 *input_line_pointer = delim;
2605 demand_empty_rest_of_line ();
2606}
2607
2608/* Directives: sectioning and alignment. */
2609
2610/* Same as s_align_ptwo but align 0 => align 2. */
2611
2612static void
2613s_align (int unused ATTRIBUTE_UNUSED)
2614{
2615 int temp;
2616 bfd_boolean fill_p;
2617 long temp_fill;
2618 long max_alignment = 15;
2619
2620 temp = get_absolute_expression ();
2621 if (temp > max_alignment)
2622 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2623 else if (temp < 0)
2624 {
2625 as_bad (_("alignment negative. 0 assumed."));
2626 temp = 0;
2627 }
2628
2629 if (*input_line_pointer == ',')
2630 {
2631 input_line_pointer++;
2632 temp_fill = get_absolute_expression ();
2633 fill_p = TRUE;
2634 }
2635 else
2636 {
2637 fill_p = FALSE;
2638 temp_fill = 0;
2639 }
2640
2641 if (!temp)
2642 temp = 2;
2643
2644 /* Only make a frag if we HAVE to. */
2645 if (temp && !need_pass_2)
2646 {
2647 if (!fill_p && subseg_text_p (now_seg))
2648 frag_align_code (temp, 0);
2649 else
2650 frag_align (temp, (int) temp_fill, 0);
2651 }
2652 demand_empty_rest_of_line ();
2653
2654 record_alignment (now_seg, temp);
2655}
2656
2657static void
2658s_bss (int ignore ATTRIBUTE_UNUSED)
2659{
2660 /* We don't support putting frags in the BSS segment, we fake it by
2661 marking in_bss, then looking at s_skip for clues. */
2662 subseg_set (bss_section, 0);
2663 demand_empty_rest_of_line ();
2664 mapping_state (MAP_DATA);
2665}
2666
2667static void
2668s_even (int ignore ATTRIBUTE_UNUSED)
2669{
2670 /* Never make frag if expect extra pass. */
2671 if (!need_pass_2)
2672 frag_align (1, 0, 0);
2673
2674 record_alignment (now_seg, 1);
2675
2676 demand_empty_rest_of_line ();
2677}
2678
2679/* Directives: Literal pools. */
2680
2681static literal_pool *
2682find_literal_pool (void)
2683{
2684 literal_pool * pool;
2685
2686 for (pool = list_of_pools; pool != NULL; pool = pool->next)
2687 {
2688 if (pool->section == now_seg
2689 && pool->sub_section == now_subseg)
2690 break;
2691 }
2692
2693 return pool;
2694}
2695
2696static literal_pool *
2697find_or_make_literal_pool (void)
2698{
2699 /* Next literal pool ID number. */
2700 static unsigned int latest_pool_num = 1;
2701 literal_pool * pool;
2702
2703 pool = find_literal_pool ();
2704
2705 if (pool == NULL)
2706 {
2707 /* Create a new pool. */
2708 pool = xmalloc (sizeof (* pool));
2709 if (! pool)
2710 return NULL;
2711
2712 pool->next_free_entry = 0;
2713 pool->section = now_seg;
2714 pool->sub_section = now_subseg;
2715 pool->next = list_of_pools;
2716 pool->symbol = NULL;
2717
2718 /* Add it to the list. */
2719 list_of_pools = pool;
2720 }
2721
2722 /* New pools, and emptied pools, will have a NULL symbol. */
2723 if (pool->symbol == NULL)
2724 {
2725 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
2726 (valueT) 0, &zero_address_frag);
2727 pool->id = latest_pool_num ++;
2728 }
2729
2730 /* Done. */
2731 return pool;
2732}
2733
2734/* Add the literal in the global 'inst'
2735 structure to the relevent literal pool. */
2736
2737static int
2738add_to_lit_pool (void)
2739{
2740 literal_pool * pool;
2741 unsigned int entry;
2742
2743 pool = find_or_make_literal_pool ();
2744
2745 /* Check if this literal value is already in the pool. */
2746 for (entry = 0; entry < pool->next_free_entry; entry ++)
2747 {
2748 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
2749 && (inst.reloc.exp.X_op == O_constant)
2750 && (pool->literals[entry].X_add_number
2751 == inst.reloc.exp.X_add_number)
2752 && (pool->literals[entry].X_unsigned
2753 == inst.reloc.exp.X_unsigned))
2754 break;
2755
2756 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
2757 && (inst.reloc.exp.X_op == O_symbol)
2758 && (pool->literals[entry].X_add_number
2759 == inst.reloc.exp.X_add_number)
2760 && (pool->literals[entry].X_add_symbol
2761 == inst.reloc.exp.X_add_symbol)
2762 && (pool->literals[entry].X_op_symbol
2763 == inst.reloc.exp.X_op_symbol))
2764 break;
2765 }
2766
2767 /* Do we need to create a new entry? */
2768 if (entry == pool->next_free_entry)
2769 {
2770 if (entry >= MAX_LITERAL_POOL_SIZE)
2771 {
2772 inst.error = _("literal pool overflow");
2773 return FAIL;
2774 }
2775
2776 pool->literals[entry] = inst.reloc.exp;
2777 pool->next_free_entry += 1;
2778 }
2779
2780 inst.reloc.exp.X_op = O_symbol;
2781 inst.reloc.exp.X_add_number = ((int) entry) * 4;
2782 inst.reloc.exp.X_add_symbol = pool->symbol;
2783
2784 return SUCCESS;
2785}
2786
2787/* Can't use symbol_new here, so have to create a symbol and then at
2788 a later date assign it a value. Thats what these functions do. */
2789
2790static void
2791symbol_locate (symbolS * symbolP,
2792 const char * name, /* It is copied, the caller can modify. */
2793 segT segment, /* Segment identifier (SEG_<something>). */
2794 valueT valu, /* Symbol value. */
2795 fragS * frag) /* Associated fragment. */
2796{
2797 unsigned int name_length;
2798 char * preserved_copy_of_name;
2799
2800 name_length = strlen (name) + 1; /* +1 for \0. */
2801 obstack_grow (¬es, name, name_length);
2802 preserved_copy_of_name = obstack_finish (¬es);
2803
2804#ifdef tc_canonicalize_symbol_name
2805 preserved_copy_of_name =
2806 tc_canonicalize_symbol_name (preserved_copy_of_name);
2807#endif
2808
2809 S_SET_NAME (symbolP, preserved_copy_of_name);
2810
2811 S_SET_SEGMENT (symbolP, segment);
2812 S_SET_VALUE (symbolP, valu);
2813 symbol_clear_list_pointers (symbolP);
2814
2815 symbol_set_frag (symbolP, frag);
2816
2817 /* Link to end of symbol chain. */
2818 {
2819 extern int symbol_table_frozen;
2820
2821 if (symbol_table_frozen)
2822 abort ();
2823 }
2824
2825 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
2826
2827 obj_symbol_new_hook (symbolP);
2828
2829#ifdef tc_symbol_new_hook
2830 tc_symbol_new_hook (symbolP);
2831#endif
2832
2833#ifdef DEBUG_SYMS
2834 verify_symbol_chain (symbol_rootP, symbol_lastP);
2835#endif /* DEBUG_SYMS */
2836}
2837
2838
2839static void
2840s_ltorg (int ignored ATTRIBUTE_UNUSED)
2841{
2842 unsigned int entry;
2843 literal_pool * pool;
2844 char sym_name[20];
2845
2846 pool = find_literal_pool ();
2847 if (pool == NULL
2848 || pool->symbol == NULL
2849 || pool->next_free_entry == 0)
2850 return;
2851
2852 mapping_state (MAP_DATA);
2853
2854 /* Align pool as you have word accesses.
2855 Only make a frag if we have to. */
2856 if (!need_pass_2)
2857 frag_align (2, 0, 0);
2858
2859 record_alignment (now_seg, 2);
2860
2861 sprintf (sym_name, "$$lit_\002%x", pool->id);
2862
2863 symbol_locate (pool->symbol, sym_name, now_seg,
2864 (valueT) frag_now_fix (), frag_now);
2865 symbol_table_insert (pool->symbol);
2866
2867 ARM_SET_THUMB (pool->symbol, thumb_mode);
2868
2869#if defined OBJ_COFF || defined OBJ_ELF
2870 ARM_SET_INTERWORK (pool->symbol, support_interwork);
2871#endif
2872
2873 for (entry = 0; entry < pool->next_free_entry; entry ++)
2874 /* First output the expression in the instruction to the pool. */
2875 emit_expr (&(pool->literals[entry]), 4); /* .word */
2876
2877 /* Mark the pool as empty. */
2878 pool->next_free_entry = 0;
2879 pool->symbol = NULL;
2880}
2881
2882#ifdef OBJ_ELF
2883/* Forward declarations for functions below, in the MD interface
2884 section. */
2885static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
2886static valueT create_unwind_entry (int);
2887static void start_unwind_section (const segT, int);
2888static void add_unwind_opcode (valueT, int);
2889static void flush_pending_unwind (void);
2890
2891/* Directives: Data. */
2892
2893static void
2894s_arm_elf_cons (int nbytes)
2895{
2896 expressionS exp;
2897
2898#ifdef md_flush_pending_output
2899 md_flush_pending_output ();
2900#endif
2901
2902 if (is_it_end_of_statement ())
2903 {
2904 demand_empty_rest_of_line ();
2905 return;
2906 }
2907
2908#ifdef md_cons_align
2909 md_cons_align (nbytes);
2910#endif
2911
2912 mapping_state (MAP_DATA);
2913 do
2914 {
2915 int reloc;
2916 char *base = input_line_pointer;
2917
2918 expression (& exp);
2919
2920 if (exp.X_op != O_symbol)
2921 emit_expr (&exp, (unsigned int) nbytes);
2922 else
2923 {
2924 char *before_reloc = input_line_pointer;
2925 reloc = parse_reloc (&input_line_pointer);
2926 if (reloc == -1)
2927 {
2928 as_bad (_("unrecognized relocation suffix"));
2929 ignore_rest_of_line ();
2930 return;
2931 }
2932 else if (reloc == BFD_RELOC_UNUSED)
2933 emit_expr (&exp, (unsigned int) nbytes);
2934 else
2935 {
2936 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
2937 int size = bfd_get_reloc_size (howto);
2938
2939 if (reloc == BFD_RELOC_ARM_PLT32)
2940 {
2941 as_bad (_("(plt) is only valid on branch targets"));
2942 reloc = BFD_RELOC_UNUSED;
2943 size = 0;
2944 }
2945
2946 if (size > nbytes)
2947 as_bad (_("%s relocations do not fit in %d bytes"),
2948 howto->name, nbytes);
2949 else
2950 {
2951 /* We've parsed an expression stopping at O_symbol.
2952 But there may be more expression left now that we
2953 have parsed the relocation marker. Parse it again.
2954 XXX Surely there is a cleaner way to do this. */
2955 char *p = input_line_pointer;
2956 int offset;
2957 char *save_buf = alloca (input_line_pointer - base);
2958 memcpy (save_buf, base, input_line_pointer - base);
2959 memmove (base + (input_line_pointer - before_reloc),
2960 base, before_reloc - base);
2961
2962 input_line_pointer = base + (input_line_pointer-before_reloc);
2963 expression (&exp);
2964 memcpy (base, save_buf, p - base);
2965
2966 offset = nbytes - size;
2967 p = frag_more ((int) nbytes);
2968 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
2969 size, &exp, 0, reloc);
2970 }
2971 }
2972 }
2973 }
2974 while (*input_line_pointer++ == ',');
2975
2976 /* Put terminator back into stream. */
2977 input_line_pointer --;
2978 demand_empty_rest_of_line ();
2979}
2980
2981
2982/* Parse a .rel31 directive. */
2983
2984static void
2985s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
2986{
2987 expressionS exp;
2988 char *p;
2989 valueT highbit;
2990
2991 highbit = 0;
2992 if (*input_line_pointer == '1')
2993 highbit = 0x80000000;
2994 else if (*input_line_pointer != '0')
2995 as_bad (_("expected 0 or 1"));
2996
2997 input_line_pointer++;
2998 if (*input_line_pointer != ',')
2999 as_bad (_("missing comma"));
3000 input_line_pointer++;
3001
3002#ifdef md_flush_pending_output
3003 md_flush_pending_output ();
3004#endif
3005
3006#ifdef md_cons_align
3007 md_cons_align (4);
3008#endif
3009
3010 mapping_state (MAP_DATA);
3011
3012 expression (&exp);
3013
3014 p = frag_more (4);
3015 md_number_to_chars (p, highbit, 4);
3016 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3017 BFD_RELOC_ARM_PREL31);
3018
3019 demand_empty_rest_of_line ();
3020}
3021
3022/* Directives: AEABI stack-unwind tables. */
3023
3024/* Parse an unwind_fnstart directive. Simply records the current location. */
3025
3026static void
3027s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3028{
3029 demand_empty_rest_of_line ();
3030 /* Mark the start of the function. */
3031 unwind.proc_start = expr_build_dot ();
3032
3033 /* Reset the rest of the unwind info. */
3034 unwind.opcode_count = 0;
3035 unwind.table_entry = NULL;
3036 unwind.personality_routine = NULL;
3037 unwind.personality_index = -1;
3038 unwind.frame_size = 0;
3039 unwind.fp_offset = 0;
3040 unwind.fp_reg = 13;
3041 unwind.fp_used = 0;
3042 unwind.sp_restored = 0;
3043}
3044
3045
3046/* Parse a handlerdata directive. Creates the exception handling table entry
3047 for the function. */
3048
3049static void
3050s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3051{
3052 demand_empty_rest_of_line ();
3053 if (unwind.table_entry)
3054 as_bad (_("dupicate .handlerdata directive"));
3055
3056 create_unwind_entry (1);
3057}
3058
3059/* Parse an unwind_fnend directive. Generates the index table entry. */
3060
3061static void
3062s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3063{
3064 long where;
3065 char *ptr;
3066 valueT val;
3067
3068 demand_empty_rest_of_line ();
3069
3070 /* Add eh table entry. */
3071 if (unwind.table_entry == NULL)
3072 val = create_unwind_entry (0);
3073 else
3074 val = 0;
3075
3076 /* Add index table entry. This is two words. */
3077 start_unwind_section (unwind.saved_seg, 1);
3078 frag_align (2, 0, 0);
3079 record_alignment (now_seg, 2);
3080
3081 ptr = frag_more (8);
3082 where = frag_now_fix () - 8;
3083
3084 /* Self relative offset of the function start. */
3085 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3086 BFD_RELOC_ARM_PREL31);
3087
3088 /* Indicate dependency on EHABI-defined personality routines to the
3089 linker, if it hasn't been done already. */
3090 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3091 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3092 {
3093 static const char *const name[] = {
3094 "__aeabi_unwind_cpp_pr0",
3095 "__aeabi_unwind_cpp_pr1",
3096 "__aeabi_unwind_cpp_pr2"
3097 };
3098 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3099 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3100 marked_pr_dependency |= 1 << unwind.personality_index;
3101 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3102 = marked_pr_dependency;
3103 }
3104
3105 if (val)
3106 /* Inline exception table entry. */
3107 md_number_to_chars (ptr + 4, val, 4);
3108 else
3109 /* Self relative offset of the table entry. */
3110 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3111 BFD_RELOC_ARM_PREL31);
3112
3113 /* Restore the original section. */
3114 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3115}
3116
3117
3118/* Parse an unwind_cantunwind directive. */
3119
3120static void
3121s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3122{
3123 demand_empty_rest_of_line ();
3124 if (unwind.personality_routine || unwind.personality_index != -1)
3125 as_bad (_("personality routine specified for cantunwind frame"));
3126
3127 unwind.personality_index = -2;
3128}
3129
3130
3131/* Parse a personalityindex directive. */
3132
3133static void
3134s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3135{
3136 expressionS exp;
3137
3138 if (unwind.personality_routine || unwind.personality_index != -1)
3139 as_bad (_("duplicate .personalityindex directive"));
3140
3141 expression (&exp);
3142
3143 if (exp.X_op != O_constant
3144 || exp.X_add_number < 0 || exp.X_add_number > 15)
3145 {
3146 as_bad (_("bad personality routine number"));
3147 ignore_rest_of_line ();
3148 return;
3149 }
3150
3151 unwind.personality_index = exp.X_add_number;
3152
3153 demand_empty_rest_of_line ();
3154}
3155
3156
3157/* Parse a personality directive. */
3158
3159static void
3160s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3161{
3162 char *name, *p, c;
3163
3164 if (unwind.personality_routine || unwind.personality_index != -1)
3165 as_bad (_("duplicate .personality directive"));
3166
3167 name = input_line_pointer;
3168 c = get_symbol_end ();
3169 p = input_line_pointer;
3170 unwind.personality_routine = symbol_find_or_make (name);
3171 *p = c;
3172 demand_empty_rest_of_line ();
3173}
3174
3175
3176/* Parse a directive saving core registers. */
3177
3178static void
3179s_arm_unwind_save_core (void)
3180{
3181 valueT op;
3182 long range;
3183 int n;
3184
3185 range = parse_reg_list (&input_line_pointer);
3186 if (range == FAIL)
3187 {
3188 as_bad (_("expected register list"));
3189 ignore_rest_of_line ();
3190 return;
3191 }
3192
3193 demand_empty_rest_of_line ();
3194
3195 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3196 into .unwind_save {..., sp...}. We aren't bothered about the value of
3197 ip because it is clobbered by calls. */
3198 if (unwind.sp_restored && unwind.fp_reg == 12
3199 && (range & 0x3000) == 0x1000)
3200 {
3201 unwind.opcode_count--;
3202 unwind.sp_restored = 0;
3203 range = (range | 0x2000) & ~0x1000;
3204 unwind.pending_offset = 0;
3205 }
3206
3207 /* Pop r4-r15. */
3208 if (range & 0xfff0)
3209 {
3210 /* See if we can use the short opcodes. These pop a block of up to 8
3211 registers starting with r4, plus maybe r14. */
3212 for (n = 0; n < 8; n++)
3213 {
3214 /* Break at the first non-saved register. */
3215 if ((range & (1 << (n + 4))) == 0)
3216 break;
3217 }
3218 /* See if there are any other bits set. */
3219 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3220 {
3221 /* Use the long form. */
3222 op = 0x8000 | ((range >> 4) & 0xfff);
3223 add_unwind_opcode (op, 2);
3224 }
3225 else
3226 {
3227 /* Use the short form. */
3228 if (range & 0x4000)
3229 op = 0xa8; /* Pop r14. */
3230 else
3231 op = 0xa0; /* Do not pop r14. */
3232 op |= (n - 1);
3233 add_unwind_opcode (op, 1);
3234 }
3235 }
3236
3237 /* Pop r0-r3. */
3238 if (range & 0xf)
3239 {
3240 op = 0xb100 | (range & 0xf);
3241 add_unwind_opcode (op, 2);
3242 }
3243
3244 /* Record the number of bytes pushed. */
3245 for (n = 0; n < 16; n++)
3246 {
3247 if (range & (1 << n))
3248 unwind.frame_size += 4;
3249 }
3250}
3251
3252
3253/* Parse a directive saving FPA registers. */
3254
3255static void
3256s_arm_unwind_save_fpa (int reg)
3257{
3258 expressionS exp;
3259 int num_regs;
3260 valueT op;
3261
3262 /* Get Number of registers to transfer. */
3263 if (skip_past_comma (&input_line_pointer) != FAIL)
3264 expression (&exp);
3265 else
3266 exp.X_op = O_illegal;
3267
3268 if (exp.X_op != O_constant)
3269 {
3270 as_bad (_("expected , <constant>"));
3271 ignore_rest_of_line ();
3272 return;
3273 }
3274
3275 num_regs = exp.X_add_number;
3276
3277 if (num_regs < 1 || num_regs > 4)
3278 {
3279 as_bad (_("number of registers must be in the range [1:4]"));
3280 ignore_rest_of_line ();
3281 return;
3282 }
3283
3284 demand_empty_rest_of_line ();
3285
3286 if (reg == 4)
3287 {
3288 /* Short form. */
3289 op = 0xb4 | (num_regs - 1);
3290 add_unwind_opcode (op, 1);
3291 }
3292 else
3293 {
3294 /* Long form. */
3295 op = 0xc800 | (reg << 4) | (num_regs - 1);
3296 add_unwind_opcode (op, 2);
3297 }
3298 unwind.frame_size += num_regs * 12;
3299}
3300
3301
3302/* Parse a directive saving VFP registers for ARMv6 and above. */
3303
3304static void
3305s_arm_unwind_save_vfp_armv6 (void)
3306{
3307 int count;
3308 unsigned int start;
3309 valueT op;
3310 int num_vfpv3_regs = 0;
3311 int num_regs_below_16;
3312
3313 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3314 if (count == FAIL)
3315 {
3316 as_bad (_("expected register list"));
3317 ignore_rest_of_line ();
3318 return;
3319 }
3320
3321 demand_empty_rest_of_line ();
3322
3323 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3324 than FSTMX/FLDMX-style ones). */
3325
3326 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3327 if (start >= 16)
3328 num_vfpv3_regs = count;
3329 else if (start + count > 16)
3330 num_vfpv3_regs = start + count - 16;
3331
3332 if (num_vfpv3_regs > 0)
3333 {
3334 int start_offset = start > 16 ? start - 16 : 0;
3335 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3336 add_unwind_opcode (op, 2);
3337 }
3338
3339 /* Generate opcode for registers numbered in the range 0 .. 15. */
3340 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3341 assert (num_regs_below_16 + num_vfpv3_regs == count);
3342 if (num_regs_below_16 > 0)
3343 {
3344 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3345 add_unwind_opcode (op, 2);
3346 }
3347
3348 unwind.frame_size += count * 8;
3349}
3350
3351
3352/* Parse a directive saving VFP registers for pre-ARMv6. */
3353
3354static void
3355s_arm_unwind_save_vfp (void)
3356{
3357 int count;
3358 unsigned int reg;
3359 valueT op;
3360
3361 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3362 if (count == FAIL)
3363 {
3364 as_bad (_("expected register list"));
3365 ignore_rest_of_line ();
3366 return;
3367 }
3368
3369 demand_empty_rest_of_line ();
3370
3371 if (reg == 8)
3372 {
3373 /* Short form. */
3374 op = 0xb8 | (count - 1);
3375 add_unwind_opcode (op, 1);
3376 }
3377 else
3378 {
3379 /* Long form. */
3380 op = 0xb300 | (reg << 4) | (count - 1);
3381 add_unwind_opcode (op, 2);
3382 }
3383 unwind.frame_size += count * 8 + 4;
3384}
3385
3386
3387/* Parse a directive saving iWMMXt data registers. */
3388
3389static void
3390s_arm_unwind_save_mmxwr (void)
3391{
3392 int reg;
3393 int hi_reg;
3394 int i;
3395 unsigned mask = 0;
3396 valueT op;
3397
3398 if (*input_line_pointer == '{')
3399 input_line_pointer++;
3400
3401 do
3402 {
3403 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3404
3405 if (reg == FAIL)
3406 {
3407 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
3408 goto error;
3409 }
3410
3411 if (mask >> reg)
3412 as_tsktsk (_("register list not in ascending order"));
3413 mask |= 1 << reg;
3414
3415 if (*input_line_pointer == '-')
3416 {
3417 input_line_pointer++;
3418 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3419 if (hi_reg == FAIL)
3420 {
3421 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
3422 goto error;
3423 }
3424 else if (reg >= hi_reg)
3425 {
3426 as_bad (_("bad register range"));
3427 goto error;
3428 }
3429 for (; reg < hi_reg; reg++)
3430 mask |= 1 << reg;
3431 }
3432 }
3433 while (skip_past_comma (&input_line_pointer) != FAIL);
3434
3435 if (*input_line_pointer == '}')
3436 input_line_pointer++;
3437
3438 demand_empty_rest_of_line ();
3439
3440 /* Generate any deferred opcodes because we're going to be looking at
3441 the list. */
3442 flush_pending_unwind ();
3443
3444 for (i = 0; i < 16; i++)
3445 {
3446 if (mask & (1 << i))
3447 unwind.frame_size += 8;
3448 }
3449
3450 /* Attempt to combine with a previous opcode. We do this because gcc
3451 likes to output separate unwind directives for a single block of
3452 registers. */
3453 if (unwind.opcode_count > 0)
3454 {
3455 i = unwind.opcodes[unwind.opcode_count - 1];
3456 if ((i & 0xf8) == 0xc0)
3457 {
3458 i &= 7;
3459 /* Only merge if the blocks are contiguous. */
3460 if (i < 6)
3461 {
3462 if ((mask & 0xfe00) == (1 << 9))
3463 {
3464 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3465 unwind.opcode_count--;
3466 }
3467 }
3468 else if (i == 6 && unwind.opcode_count >= 2)
3469 {
3470 i = unwind.opcodes[unwind.opcode_count - 2];
3471 reg = i >> 4;
3472 i &= 0xf;
3473
3474 op = 0xffff << (reg - 1);
3475 if (reg > 0
3476 && ((mask & op) == (1u << (reg - 1))))
3477 {
3478 op = (1 << (reg + i + 1)) - 1;
3479 op &= ~((1 << reg) - 1);
3480 mask |= op;
3481 unwind.opcode_count -= 2;
3482 }
3483 }
3484 }
3485 }
3486
3487 hi_reg = 15;
3488 /* We want to generate opcodes in the order the registers have been
3489 saved, ie. descending order. */
3490 for (reg = 15; reg >= -1; reg--)
3491 {
3492 /* Save registers in blocks. */
3493 if (reg < 0
3494 || !(mask & (1 << reg)))
3495 {
3496 /* We found an unsaved reg. Generate opcodes to save the
3497 preceeding block. */
3498 if (reg != hi_reg)
3499 {
3500 if (reg == 9)
3501 {
3502 /* Short form. */
3503 op = 0xc0 | (hi_reg - 10);
3504 add_unwind_opcode (op, 1);
3505 }
3506 else
3507 {
3508 /* Long form. */
3509 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3510 add_unwind_opcode (op, 2);
3511 }
3512 }
3513 hi_reg = reg - 1;
3514 }
3515 }
3516
3517 return;
3518error:
3519 ignore_rest_of_line ();
3520}
3521
3522static void
3523s_arm_unwind_save_mmxwcg (void)
3524{
3525 int reg;
3526 int hi_reg;
3527 unsigned mask = 0;
3528 valueT op;
3529
3530 if (*input_line_pointer == '{')
3531 input_line_pointer++;
3532
3533 do
3534 {
3535 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
3536
3537 if (reg == FAIL)
3538 {
3539 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
3540 goto error;
3541 }
3542
3543 reg -= 8;
3544 if (mask >> reg)
3545 as_tsktsk (_("register list not in ascending order"));
3546 mask |= 1 << reg;
3547
3548 if (*input_line_pointer == '-')
3549 {
3550 input_line_pointer++;
3551 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
3552 if (hi_reg == FAIL)
3553 {
3554 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
3555 goto error;
3556 }
3557 else if (reg >= hi_reg)
3558 {
3559 as_bad (_("bad register range"));
3560 goto error;
3561 }
3562 for (; reg < hi_reg; reg++)
3563 mask |= 1 << reg;
3564 }
3565 }
3566 while (skip_past_comma (&input_line_pointer) != FAIL);
3567
3568 if (*input_line_pointer == '}')
3569 input_line_pointer++;
3570
3571 demand_empty_rest_of_line ();
3572
3573 /* Generate any deferred opcodes because we're going to be looking at
3574 the list. */
3575 flush_pending_unwind ();
3576
3577 for (reg = 0; reg < 16; reg++)
3578 {
3579 if (mask & (1 << reg))
3580 unwind.frame_size += 4;
3581 }
3582 op = 0xc700 | mask;
3583 add_unwind_opcode (op, 2);
3584 return;
3585error:
3586 ignore_rest_of_line ();
3587}
3588
3589
3590/* Parse an unwind_save directive.
3591 If the argument is non-zero, this is a .vsave directive. */
3592
3593static void
3594s_arm_unwind_save (int arch_v6)
3595{
3596 char *peek;
3597 struct reg_entry *reg;
3598 bfd_boolean had_brace = FALSE;
3599
3600 /* Figure out what sort of save we have. */
3601 peek = input_line_pointer;
3602
3603 if (*peek == '{')
3604 {
3605 had_brace = TRUE;
3606 peek++;
3607 }
3608
3609 reg = arm_reg_parse_multi (&peek);
3610
3611 if (!reg)
3612 {
3613 as_bad (_("register expected"));
3614 ignore_rest_of_line ();
3615 return;
3616 }
3617
3618 switch (reg->type)
3619 {
3620 case REG_TYPE_FN:
3621 if (had_brace)
3622 {
3623 as_bad (_("FPA .unwind_save does not take a register list"));
3624 ignore_rest_of_line ();
3625 return;
3626 }
3627 s_arm_unwind_save_fpa (reg->number);
3628 return;
3629
3630 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
3631 case REG_TYPE_VFD:
3632 if (arch_v6)
3633 s_arm_unwind_save_vfp_armv6 ();
3634 else
3635 s_arm_unwind_save_vfp ();
3636 return;
3637 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
3638 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
3639
3640 default:
3641 as_bad (_(".unwind_save does not support this kind of register"));
3642 ignore_rest_of_line ();
3643 }
3644}
3645
3646
3647/* Parse an unwind_movsp directive. */
3648
3649static void
3650s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
3651{
3652 int reg;
3653 valueT op;
3654 int offset;
3655
3656 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
3657 if (reg == FAIL)
3658 {
3659 as_bad (_(reg_expected_msgs[REG_TYPE_RN]));
3660 ignore_rest_of_line ();
3661 return;
3662 }
3663
3664 /* Optional constant. */
3665 if (skip_past_comma (&input_line_pointer) != FAIL)
3666 {
3667 if (immediate_for_directive (&offset) == FAIL)
3668 return;
3669 }
3670 else
3671 offset = 0;
3672
3673 demand_empty_rest_of_line ();
3674
3675 if (reg == REG_SP || reg == REG_PC)
3676 {
3677 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3678 return;
3679 }
3680
3681 if (unwind.fp_reg != REG_SP)
3682 as_bad (_("unexpected .unwind_movsp directive"));
3683
3684 /* Generate opcode to restore the value. */
3685 op = 0x90 | reg;
3686 add_unwind_opcode (op, 1);
3687
3688 /* Record the information for later. */
3689 unwind.fp_reg = reg;
3690 unwind.fp_offset = unwind.frame_size - offset;
3691 unwind.sp_restored = 1;
3692}
3693
3694/* Parse an unwind_pad directive. */
3695
3696static void
3697s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
3698{
3699 int offset;
3700
3701 if (immediate_for_directive (&offset) == FAIL)
3702 return;
3703
3704 if (offset & 3)
3705 {
3706 as_bad (_("stack increment must be multiple of 4"));
3707 ignore_rest_of_line ();
3708 return;
3709 }
3710
3711 /* Don't generate any opcodes, just record the details for later. */
3712 unwind.frame_size += offset;
3713 unwind.pending_offset += offset;
3714
3715 demand_empty_rest_of_line ();
3716}
3717
3718/* Parse an unwind_setfp directive. */
3719
3720static void
3721s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
3722{
3723 int sp_reg;
3724 int fp_reg;
3725 int offset;
3726
3727 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
3728 if (skip_past_comma (&input_line_pointer) == FAIL)
3729 sp_reg = FAIL;
3730 else
3731 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
3732
3733 if (fp_reg == FAIL || sp_reg == FAIL)
3734 {
3735 as_bad (_("expected <reg>, <reg>"));
3736 ignore_rest_of_line ();
3737 return;
3738 }
3739
3740 /* Optional constant. */
3741 if (skip_past_comma (&input_line_pointer) != FAIL)
3742 {
3743 if (immediate_for_directive (&offset) == FAIL)
3744 return;
3745 }
3746 else
3747 offset = 0;
3748
3749 demand_empty_rest_of_line ();
3750
3751 if (sp_reg != 13 && sp_reg != unwind.fp_reg)
3752 {
3753 as_bad (_("register must be either sp or set by a previous"
3754 "unwind_movsp directive"));
3755 return;
3756 }
3757
3758 /* Don't generate any opcodes, just record the information for later. */
3759 unwind.fp_reg = fp_reg;
3760 unwind.fp_used = 1;
3761 if (sp_reg == 13)
3762 unwind.fp_offset = unwind.frame_size - offset;
3763 else
3764 unwind.fp_offset -= offset;
3765}
3766
3767/* Parse an unwind_raw directive. */
3768
3769static void
3770s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
3771{
3772 expressionS exp;
3773 /* This is an arbitrary limit. */
3774 unsigned char op[16];
3775 int count;
3776
3777 expression (&exp);
3778 if (exp.X_op == O_constant
3779 && skip_past_comma (&input_line_pointer) != FAIL)
3780 {
3781 unwind.frame_size += exp.X_add_number;
3782 expression (&exp);
3783 }
3784 else
3785 exp.X_op = O_illegal;
3786
3787 if (exp.X_op != O_constant)
3788 {
3789 as_bad (_("expected <offset>, <opcode>"));
3790 ignore_rest_of_line ();
3791 return;
3792 }
3793
3794 count = 0;
3795
3796 /* Parse the opcode. */
3797 for (;;)
3798 {
3799 if (count >= 16)
3800 {
3801 as_bad (_("unwind opcode too long"));
3802 ignore_rest_of_line ();
3803 }
3804 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
3805 {
3806 as_bad (_("invalid unwind opcode"));
3807 ignore_rest_of_line ();
3808 return;
3809 }
3810 op[count++] = exp.X_add_number;
3811
3812 /* Parse the next byte. */
3813 if (skip_past_comma (&input_line_pointer) == FAIL)
3814 break;
3815
3816 expression (&exp);
3817 }
3818
3819 /* Add the opcode bytes in reverse order. */
3820 while (count--)
3821 add_unwind_opcode (op[count], 1);
3822
3823 demand_empty_rest_of_line ();
3824}
3825
3826
3827/* Parse a .eabi_attribute directive. */
3828
3829static void
3830s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
3831{
3832 s_vendor_attribute (OBJ_ATTR_PROC);
3833}
3834#endif /* OBJ_ELF */
3835
3836static void s_arm_arch (int);
3837static void s_arm_object_arch (int);
3838static void s_arm_cpu (int);
3839static void s_arm_fpu (int);
3840
3841#ifdef TE_PE
3842
3843static void
3844pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
3845{
3846 expressionS exp;
3847
3848 do
3849 {
3850 expression (&exp);
3851 if (exp.X_op == O_symbol)
3852 exp.X_op = O_secrel;
3853
3854 emit_expr (&exp, 4);
3855 }
3856 while (*input_line_pointer++ == ',');
3857
3858 input_line_pointer--;
3859 demand_empty_rest_of_line ();
3860}
3861#endif /* TE_PE */
3862
3863/* This table describes all the machine specific pseudo-ops the assembler
3864 has to support. The fields are:
3865 pseudo-op name without dot
3866 function to call to execute this pseudo-op
3867 Integer arg to pass to the function. */
3868
3869const pseudo_typeS md_pseudo_table[] =
3870{
3871 /* Never called because '.req' does not start a line. */
3872 { "req", s_req, 0 },
3873 /* Following two are likewise never called. */
3874 { "dn", s_dn, 0 },
3875 { "qn", s_qn, 0 },
3876 { "unreq", s_unreq, 0 },
3877 { "bss", s_bss, 0 },
3878 { "align", s_align, 0 },
3879 { "arm", s_arm, 0 },
3880 { "thumb", s_thumb, 0 },
3881 { "code", s_code, 0 },
3882 { "force_thumb", s_force_thumb, 0 },
3883 { "thumb_func", s_thumb_func, 0 },
3884 { "thumb_set", s_thumb_set, 0 },
3885 { "even", s_even, 0 },
3886 { "ltorg", s_ltorg, 0 },
3887 { "pool", s_ltorg, 0 },
3888 { "syntax", s_syntax, 0 },
3889 { "cpu", s_arm_cpu, 0 },
3890 { "arch", s_arm_arch, 0 },
3891 { "object_arch", s_arm_object_arch, 0 },
3892 { "fpu", s_arm_fpu, 0 },
3893#ifdef OBJ_ELF
3894 { "word", s_arm_elf_cons, 4 },
3895 { "long", s_arm_elf_cons, 4 },
3896 { "rel31", s_arm_rel31, 0 },
3897 { "fnstart", s_arm_unwind_fnstart, 0 },
3898 { "fnend", s_arm_unwind_fnend, 0 },
3899 { "cantunwind", s_arm_unwind_cantunwind, 0 },
3900 { "personality", s_arm_unwind_personality, 0 },
3901 { "personalityindex", s_arm_unwind_personalityindex, 0 },
3902 { "handlerdata", s_arm_unwind_handlerdata, 0 },
3903 { "save", s_arm_unwind_save, 0 },
3904 { "vsave", s_arm_unwind_save, 1 },
3905 { "movsp", s_arm_unwind_movsp, 0 },
3906 { "pad", s_arm_unwind_pad, 0 },
3907 { "setfp", s_arm_unwind_setfp, 0 },
3908 { "unwind_raw", s_arm_unwind_raw, 0 },
3909 { "eabi_attribute", s_arm_eabi_attribute, 0 },
3910#else
3911 { "word", cons, 4},
3912
3913 /* These are used for dwarf. */
3914 {"2byte", cons, 2},
3915 {"4byte", cons, 4},
3916 {"8byte", cons, 8},
3917 /* These are used for dwarf2. */
3918 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
3919 { "loc", dwarf2_directive_loc, 0 },
3920 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
3921#endif
3922 { "extend", float_cons, 'x' },
3923 { "ldouble", float_cons, 'x' },
3924 { "packed", float_cons, 'p' },
3925#ifdef TE_PE
3926 {"secrel32", pe_directive_secrel, 0},
3927#endif
3928 { 0, 0, 0 }
3929};
3930
3931/* Parser functions used exclusively in instruction operands. */
3932
3933/* Generic immediate-value read function for use in insn parsing.
3934 STR points to the beginning of the immediate (the leading #);
3935 VAL receives the value; if the value is outside [MIN, MAX]
3936 issue an error. PREFIX_OPT is true if the immediate prefix is
3937 optional. */
3938
3939static int
3940parse_immediate (char **str, int *val, int min, int max,
3941 bfd_boolean prefix_opt)
3942{
3943 expressionS exp;
3944 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
3945 if (exp.X_op != O_constant)
3946 {
3947 inst.error = _("constant expression required");
3948 return FAIL;
3949 }
3950
3951 if (exp.X_add_number < min || exp.X_add_number > max)
3952 {
3953 inst.error = _("immediate value out of range");
3954 return FAIL;
3955 }
3956
3957 *val = exp.X_add_number;
3958 return SUCCESS;
3959}
3960
3961/* Less-generic immediate-value read function with the possibility of loading a
3962 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
3963 instructions. Puts the result directly in inst.operands[i]. */
3964
3965static int
3966parse_big_immediate (char **str, int i)
3967{
3968 expressionS exp;
3969 char *ptr = *str;
3970
3971 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
3972
3973 if (exp.X_op == O_constant)
3974 {
3975 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
3976 /* If we're on a 64-bit host, then a 64-bit number can be returned using
3977 O_constant. We have to be careful not to break compilation for
3978 32-bit X_add_number, though. */
3979 if ((exp.X_add_number & ~0xffffffffl) != 0)
3980 {
3981 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
3982 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
3983 inst.operands[i].regisimm = 1;
3984 }
3985 }
3986 else if (exp.X_op == O_big
3987 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32
3988 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64)
3989 {
3990 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
3991 /* Bignums have their least significant bits in
3992 generic_bignum[0]. Make sure we put 32 bits in imm and
3993 32 bits in reg, in a (hopefully) portable way. */
3994 assert (parts != 0);
3995 inst.operands[i].imm = 0;
3996 for (j = 0; j < parts; j++, idx++)
3997 inst.operands[i].imm |= generic_bignum[idx]
3998 << (LITTLENUM_NUMBER_OF_BITS * j);
3999 inst.operands[i].reg = 0;
4000 for (j = 0; j < parts; j++, idx++)
4001 inst.operands[i].reg |= generic_bignum[idx]
4002 << (LITTLENUM_NUMBER_OF_BITS * j);
4003 inst.operands[i].regisimm = 1;
4004 }
4005 else
4006 return FAIL;
4007
4008 *str = ptr;
4009
4010 return SUCCESS;
4011}
4012
4013/* Returns the pseudo-register number of an FPA immediate constant,
4014 or FAIL if there isn't a valid constant here. */
4015
4016static int
4017parse_fpa_immediate (char ** str)
4018{
4019 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4020 char * save_in;
4021 expressionS exp;
4022 int i;
4023 int j;
4024
4025 /* First try and match exact strings, this is to guarantee
4026 that some formats will work even for cross assembly. */
4027
4028 for (i = 0; fp_const[i]; i++)
4029 {
4030 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4031 {
4032 char *start = *str;
4033
4034 *str += strlen (fp_const[i]);
4035 if (is_end_of_line[(unsigned char) **str])
4036 return i + 8;
4037 *str = start;
4038 }
4039 }
4040
4041 /* Just because we didn't get a match doesn't mean that the constant
4042 isn't valid, just that it is in a format that we don't
4043 automatically recognize. Try parsing it with the standard
4044 expression routines. */
4045
4046 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4047
4048 /* Look for a raw floating point number. */
4049 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4050 && is_end_of_line[(unsigned char) *save_in])
4051 {
4052 for (i = 0; i < NUM_FLOAT_VALS; i++)
4053 {
4054 for (j = 0; j < MAX_LITTLENUMS; j++)
4055 {
4056 if (words[j] != fp_values[i][j])
4057 break;
4058 }
4059
4060 if (j == MAX_LITTLENUMS)
4061 {
4062 *str = save_in;
4063 return i + 8;
4064 }
4065 }
4066 }
4067
4068 /* Try and parse a more complex expression, this will probably fail
4069 unless the code uses a floating point prefix (eg "0f"). */
4070 save_in = input_line_pointer;
4071 input_line_pointer = *str;
4072 if (expression (&exp) == absolute_section
4073 && exp.X_op == O_big
4074 && exp.X_add_number < 0)
4075 {
4076 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4077 Ditto for 15. */
4078 if (gen_to_words (words, 5, (long) 15) == 0)
4079 {
4080 for (i = 0; i < NUM_FLOAT_VALS; i++)
4081 {
4082 for (j = 0; j < MAX_LITTLENUMS; j++)
4083 {
4084 if (words[j] != fp_values[i][j])
4085 break;
4086 }
4087
4088 if (j == MAX_LITTLENUMS)
4089 {
4090 *str = input_line_pointer;
4091 input_line_pointer = save_in;
4092 return i + 8;
4093 }
4094 }
4095 }
4096 }
4097
4098 *str = input_line_pointer;
4099 input_line_pointer = save_in;
4100 inst.error = _("invalid FPA immediate expression");
4101 return FAIL;
4102}
4103
4104/* Returns 1 if a number has "quarter-precision" float format
4105 0baBbbbbbc defgh000 00000000 00000000. */
4106
4107static int
4108is_quarter_float (unsigned imm)
4109{
4110 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4111 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4112}
4113
4114/* Parse an 8-bit "quarter-precision" floating point number of the form:
4115 0baBbbbbbc defgh000 00000000 00000000.
4116 The zero and minus-zero cases need special handling, since they can't be
4117 encoded in the "quarter-precision" float format, but can nonetheless be
4118 loaded as integer constants. */
4119
4120static unsigned
4121parse_qfloat_immediate (char **ccp, int *immed)
4122{
4123 char *str = *ccp;
4124 char *fpnum;
4125 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4126 int found_fpchar = 0;
4127
4128 skip_past_char (&str, '#');
4129
4130 /* We must not accidentally parse an integer as a floating-point number. Make
4131 sure that the value we parse is not an integer by checking for special
4132 characters '.' or 'e'.
4133 FIXME: This is a horrible hack, but doing better is tricky because type
4134 information isn't in a very usable state at parse time. */
4135 fpnum = str;
4136 skip_whitespace (fpnum);
4137
4138 if (strncmp (fpnum, "0x", 2) == 0)
4139 return FAIL;
4140 else
4141 {
4142 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4143 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4144 {
4145 found_fpchar = 1;
4146 break;
4147 }
4148
4149 if (!found_fpchar)
4150 return FAIL;
4151 }
4152
4153 if ((str = atof_ieee (str, 's', words)) != NULL)
4154 {
4155 unsigned fpword = 0;
4156 int i;
4157
4158 /* Our FP word must be 32 bits (single-precision FP). */
4159 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4160 {
4161 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4162 fpword |= words[i];
4163 }
4164
4165 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4166 *immed = fpword;
4167 else
4168 return FAIL;
4169
4170 *ccp = str;
4171
4172 return SUCCESS;
4173 }
4174
4175 return FAIL;
4176}
4177
4178/* Shift operands. */
4179enum shift_kind
4180{
4181 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4182};
4183
4184struct asm_shift_name
4185{
4186 const char *name;
4187 enum shift_kind kind;
4188};
4189
4190/* Third argument to parse_shift. */
4191enum parse_shift_mode
4192{
4193 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4194 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4195 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4196 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4197 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4198};
4199
4200/* Parse a <shift> specifier on an ARM data processing instruction.
4201 This has three forms:
4202
4203 (LSL|LSR|ASL|ASR|ROR) Rs
4204 (LSL|LSR|ASL|ASR|ROR) #imm
4205 RRX
4206
4207 Note that ASL is assimilated to LSL in the instruction encoding, and
4208 RRX to ROR #0 (which cannot be written as such). */
4209
4210static int
4211parse_shift (char **str, int i, enum parse_shift_mode mode)
4212{
4213 const struct asm_shift_name *shift_name;
4214 enum shift_kind shift;
4215 char *s = *str;
4216 char *p = s;
4217 int reg;
4218
4219 for (p = *str; ISALPHA (*p); p++)
4220 ;
4221
4222 if (p == *str)
4223 {
4224 inst.error = _("shift expression expected");
4225 return FAIL;
4226 }
4227
4228 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str);
4229
4230 if (shift_name == NULL)
4231 {
4232 inst.error = _("shift expression expected");
4233 return FAIL;
4234 }
4235
4236 shift = shift_name->kind;
4237
4238 switch (mode)
4239 {
4240 case NO_SHIFT_RESTRICT:
4241 case SHIFT_IMMEDIATE: break;
4242
4243 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4244 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4245 {
4246 inst.error = _("'LSL' or 'ASR' required");
4247 return FAIL;
4248 }
4249 break;
4250
4251 case SHIFT_LSL_IMMEDIATE:
4252 if (shift != SHIFT_LSL)
4253 {
4254 inst.error = _("'LSL' required");
4255 return FAIL;
4256 }
4257 break;
4258
4259 case SHIFT_ASR_IMMEDIATE:
4260 if (shift != SHIFT_ASR)
4261 {
4262 inst.error = _("'ASR' required");
4263 return FAIL;
4264 }
4265 break;
4266
4267 default: abort ();
4268 }
4269
4270 if (shift != SHIFT_RRX)
4271 {
4272 /* Whitespace can appear here if the next thing is a bare digit. */
4273 skip_whitespace (p);
4274
4275 if (mode == NO_SHIFT_RESTRICT
4276 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4277 {
4278 inst.operands[i].imm = reg;
4279 inst.operands[i].immisreg = 1;
4280 }
4281 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4282 return FAIL;
4283 }
4284 inst.operands[i].shift_kind = shift;
4285 inst.operands[i].shifted = 1;
4286 *str = p;
4287 return SUCCESS;
4288}
4289
4290/* Parse a <shifter_operand> for an ARM data processing instruction:
4291
4292 #<immediate>
4293 #<immediate>, <rotate>
4294 <Rm>
4295 <Rm>, <shift>
4296
4297 where <shift> is defined by parse_shift above, and <rotate> is a
4298 multiple of 2 between 0 and 30. Validation of immediate operands
4299 is deferred to md_apply_fix. */
4300
4301static int
4302parse_shifter_operand (char **str, int i)
4303{
4304 int value;
4305 expressionS expr;
4306
4307 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4308 {
4309 inst.operands[i].reg = value;
4310 inst.operands[i].isreg = 1;
4311
4312 /* parse_shift will override this if appropriate */
4313 inst.reloc.exp.X_op = O_constant;
4314 inst.reloc.exp.X_add_number = 0;
4315
4316 if (skip_past_comma (str) == FAIL)
4317 return SUCCESS;
4318
4319 /* Shift operation on register. */
4320 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4321 }
4322
4323 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4324 return FAIL;
4325
4326 if (skip_past_comma (str) == SUCCESS)
4327 {
4328 /* #x, y -- ie explicit rotation by Y. */
4329 if (my_get_expression (&expr, str, GE_NO_PREFIX))
4330 return FAIL;
4331
4332 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4333 {
4334 inst.error = _("constant expression expected");
4335 return FAIL;
4336 }
4337
4338 value = expr.X_add_number;
4339 if (value < 0 || value > 30 || value % 2 != 0)
4340 {
4341 inst.error = _("invalid rotation");
4342 return FAIL;
4343 }
4344 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4345 {
4346 inst.error = _("invalid constant");
4347 return FAIL;
4348 }
4349
4350 /* Convert to decoded value. md_apply_fix will put it back. */
4351 inst.reloc.exp.X_add_number
4352 = (((inst.reloc.exp.X_add_number << (32 - value))
4353 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
4354 }
4355
4356 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4357 inst.reloc.pc_rel = 0;
4358 return SUCCESS;
4359}
4360
4361/* Group relocation information. Each entry in the table contains the
4362 textual name of the relocation as may appear in assembler source
4363 and must end with a colon.
4364 Along with this textual name are the relocation codes to be used if
4365 the corresponding instruction is an ALU instruction (ADD or SUB only),
4366 an LDR, an LDRS, or an LDC. */
4367
4368struct group_reloc_table_entry
4369{
4370 const char *name;
4371 int alu_code;
4372 int ldr_code;
4373 int ldrs_code;
4374 int ldc_code;
4375};
4376
4377typedef enum
4378{
4379 /* Varieties of non-ALU group relocation. */
4380
4381 GROUP_LDR,
4382 GROUP_LDRS,
4383 GROUP_LDC
4384} group_reloc_type;
4385
4386static struct group_reloc_table_entry group_reloc_table[] =
4387 { /* Program counter relative: */
4388 { "pc_g0_nc",
4389 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4390 0, /* LDR */
4391 0, /* LDRS */
4392 0 }, /* LDC */
4393 { "pc_g0",
4394 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4395 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4396 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4397 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4398 { "pc_g1_nc",
4399 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4400 0, /* LDR */
4401 0, /* LDRS */
4402 0 }, /* LDC */
4403 { "pc_g1",
4404 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4405 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4406 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4407 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4408 { "pc_g2",
4409 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4410 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4411 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4412 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4413 /* Section base relative */
4414 { "sb_g0_nc",
4415 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4416 0, /* LDR */
4417 0, /* LDRS */
4418 0 }, /* LDC */
4419 { "sb_g0",
4420 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4421 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4422 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4423 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4424 { "sb_g1_nc",
4425 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4426 0, /* LDR */
4427 0, /* LDRS */
4428 0 }, /* LDC */
4429 { "sb_g1",
4430 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4431 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4432 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4433 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4434 { "sb_g2",
4435 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4436 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4437 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4438 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4439
4440/* Given the address of a pointer pointing to the textual name of a group
4441 relocation as may appear in assembler source, attempt to find its details
4442 in group_reloc_table. The pointer will be updated to the character after
4443 the trailing colon. On failure, FAIL will be returned; SUCCESS
4444 otherwise. On success, *entry will be updated to point at the relevant
4445 group_reloc_table entry. */
4446
4447static int
4448find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
4449{
4450 unsigned int i;
4451 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
4452 {
4453 int length = strlen (group_reloc_table[i].name);
4454
4455 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 &&
4456 (*str)[length] == ':')
4457 {
4458 *out = &group_reloc_table[i];
4459 *str += (length + 1);
4460 return SUCCESS;
4461 }
4462 }
4463
4464 return FAIL;
4465}
4466
4467/* Parse a <shifter_operand> for an ARM data processing instruction
4468 (as for parse_shifter_operand) where group relocations are allowed:
4469
4470 #<immediate>
4471 #<immediate>, <rotate>
4472 #:<group_reloc>:<expression>
4473 <Rm>
4474 <Rm>, <shift>
4475
4476 where <group_reloc> is one of the strings defined in group_reloc_table.
4477 The hashes are optional.
4478
4479 Everything else is as for parse_shifter_operand. */
4480
4481static parse_operand_result
4482parse_shifter_operand_group_reloc (char **str, int i)
4483{
4484 /* Determine if we have the sequence of characters #: or just :
4485 coming next. If we do, then we check for a group relocation.
4486 If we don't, punt the whole lot to parse_shifter_operand. */
4487
4488 if (((*str)[0] == '#' && (*str)[1] == ':')
4489 || (*str)[0] == ':')
4490 {
4491 struct group_reloc_table_entry *entry;
4492
4493 if ((*str)[0] == '#')
4494 (*str) += 2;
4495 else
4496 (*str)++;
4497
4498 /* Try to parse a group relocation. Anything else is an error. */
4499 if (find_group_reloc_table_entry (str, &entry) == FAIL)
4500 {
4501 inst.error = _("unknown group relocation");
4502 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4503 }
4504
4505 /* We now have the group relocation table entry corresponding to
4506 the name in the assembler source. Next, we parse the expression. */
4507 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
4508 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4509
4510 /* Record the relocation type (always the ALU variant here). */
4511 inst.reloc.type = entry->alu_code;
4512 assert (inst.reloc.type != 0);
4513
4514 return PARSE_OPERAND_SUCCESS;
4515 }
4516 else
4517 return parse_shifter_operand (str, i) == SUCCESS
4518 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
4519
4520 /* Never reached. */
4521}
4522
4523/* Parse all forms of an ARM address expression. Information is written
4524 to inst.operands[i] and/or inst.reloc.
4525
4526 Preindexed addressing (.preind=1):
4527
4528 [Rn, #offset] .reg=Rn .reloc.exp=offset
4529 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4530 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4531 .shift_kind=shift .reloc.exp=shift_imm
4532
4533 These three may have a trailing ! which causes .writeback to be set also.
4534
4535 Postindexed addressing (.postind=1, .writeback=1):
4536
4537 [Rn], #offset .reg=Rn .reloc.exp=offset
4538 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4539 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4540 .shift_kind=shift .reloc.exp=shift_imm
4541
4542 Unindexed addressing (.preind=0, .postind=0):
4543
4544 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4545
4546 Other:
4547
4548 [Rn]{!} shorthand for [Rn,#0]{!}
4549 =immediate .isreg=0 .reloc.exp=immediate
4550 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4551
4552 It is the caller's responsibility to check for addressing modes not
4553 supported by the instruction, and to set inst.reloc.type. */
4554
4555static parse_operand_result
4556parse_address_main (char **str, int i, int group_relocations,
4557 group_reloc_type group_type)
4558{
4559 char *p = *str;
4560 int reg;
4561
4562 if (skip_past_char (&p, '[') == FAIL)
4563 {
4564 if (skip_past_char (&p, '=') == FAIL)
4565 {
4566 /* bare address - translate to PC-relative offset */
4567 inst.reloc.pc_rel = 1;
4568 inst.operands[i].reg = REG_PC;
4569 inst.operands[i].isreg = 1;
4570 inst.operands[i].preind = 1;
4571 }
4572 /* else a load-constant pseudo op, no special treatment needed here */
4573
4574 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4575 return PARSE_OPERAND_FAIL;
4576
4577 *str = p;
4578 return PARSE_OPERAND_SUCCESS;
4579 }
4580
4581 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
4582 {
4583 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
4584 return PARSE_OPERAND_FAIL;
4585 }
4586 inst.operands[i].reg = reg;
4587 inst.operands[i].isreg = 1;
4588
4589 if (skip_past_comma (&p) == SUCCESS)
4590 {
4591 inst.operands[i].preind = 1;
4592
4593 if (*p == '+') p++;
4594 else if (*p == '-') p++, inst.operands[i].negative = 1;
4595
4596 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4597 {
4598 inst.operands[i].imm = reg;
4599 inst.operands[i].immisreg = 1;
4600
4601 if (skip_past_comma (&p) == SUCCESS)
4602 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4603 return PARSE_OPERAND_FAIL;
4604 }
4605 else if (skip_past_char (&p, ':') == SUCCESS)
4606 {
4607 /* FIXME: '@' should be used here, but it's filtered out by generic
4608 code before we get to see it here. This may be subject to
4609 change. */
4610 expressionS exp;
4611 my_get_expression (&exp, &p, GE_NO_PREFIX);
4612 if (exp.X_op != O_constant)
4613 {
4614 inst.error = _("alignment must be constant");
4615 return PARSE_OPERAND_FAIL;
4616 }
4617 inst.operands[i].imm = exp.X_add_number << 8;
4618 inst.operands[i].immisalign = 1;
4619 /* Alignments are not pre-indexes. */
4620 inst.operands[i].preind = 0;
4621 }
4622 else
4623 {
4624 if (inst.operands[i].negative)
4625 {
4626 inst.operands[i].negative = 0;
4627 p--;
4628 }
4629
4630 if (group_relocations &&
4631 ((*p == '#' && *(p + 1) == ':') || *p == ':'))
4632
4633 {
4634 struct group_reloc_table_entry *entry;
4635
4636 /* Skip over the #: or : sequence. */
4637 if (*p == '#')
4638 p += 2;
4639 else
4640 p++;
4641
4642 /* Try to parse a group relocation. Anything else is an
4643 error. */
4644 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
4645 {
4646 inst.error = _("unknown group relocation");
4647 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4648 }
4649
4650 /* We now have the group relocation table entry corresponding to
4651 the name in the assembler source. Next, we parse the
4652 expression. */
4653 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4654 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4655
4656 /* Record the relocation type. */
4657 switch (group_type)
4658 {
4659 case GROUP_LDR:
4660 inst.reloc.type = entry->ldr_code;
4661 break;
4662
4663 case GROUP_LDRS:
4664 inst.reloc.type = entry->ldrs_code;
4665 break;
4666
4667 case GROUP_LDC:
4668 inst.reloc.type = entry->ldc_code;
4669 break;
4670
4671 default:
4672 assert (0);
4673 }
4674
4675 if (inst.reloc.type == 0)
4676 {
4677 inst.error = _("this group relocation is not allowed on this instruction");
4678 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4679 }
4680 }
4681 else
4682 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4683 return PARSE_OPERAND_FAIL;
4684 }
4685 }
4686
4687 if (skip_past_char (&p, ']') == FAIL)
4688 {
4689 inst.error = _("']' expected");
4690 return PARSE_OPERAND_FAIL;
4691 }
4692
4693 if (skip_past_char (&p, '!') == SUCCESS)
4694 inst.operands[i].writeback = 1;
4695
4696 else if (skip_past_comma (&p) == SUCCESS)
4697 {
4698 if (skip_past_char (&p, '{') == SUCCESS)
4699 {
4700 /* [Rn], {expr} - unindexed, with option */
4701 if (parse_immediate (&p, &inst.operands[i].imm,
4702 0, 255, TRUE) == FAIL)
4703 return PARSE_OPERAND_FAIL;
4704
4705 if (skip_past_char (&p, '}') == FAIL)
4706 {
4707 inst.error = _("'}' expected at end of 'option' field");
4708 return PARSE_OPERAND_FAIL;
4709 }
4710 if (inst.operands[i].preind)
4711 {
4712 inst.error = _("cannot combine index with option");
4713 return PARSE_OPERAND_FAIL;
4714 }
4715 *str = p;
4716 return PARSE_OPERAND_SUCCESS;
4717 }
4718 else
4719 {
4720 inst.operands[i].postind = 1;
4721 inst.operands[i].writeback = 1;
4722
4723 if (inst.operands[i].preind)
4724 {
4725 inst.error = _("cannot combine pre- and post-indexing");
4726 return PARSE_OPERAND_FAIL;
4727 }
4728
4729 if (*p == '+') p++;
4730 else if (*p == '-') p++, inst.operands[i].negative = 1;
4731
4732 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4733 {
4734 /* We might be using the immediate for alignment already. If we
4735 are, OR the register number into the low-order bits. */
4736 if (inst.operands[i].immisalign)
4737 inst.operands[i].imm |= reg;
4738 else
4739 inst.operands[i].imm = reg;
4740 inst.operands[i].immisreg = 1;
4741
4742 if (skip_past_comma (&p) == SUCCESS)
4743 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4744 return PARSE_OPERAND_FAIL;
4745 }
4746 else
4747 {
4748 if (inst.operands[i].negative)
4749 {
4750 inst.operands[i].negative = 0;
4751 p--;
4752 }
4753 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4754 return PARSE_OPERAND_FAIL;
4755 }
4756 }
4757 }
4758
4759 /* If at this point neither .preind nor .postind is set, we have a
4760 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4761 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
4762 {
4763 inst.operands[i].preind = 1;
4764 inst.reloc.exp.X_op = O_constant;
4765 inst.reloc.exp.X_add_number = 0;
4766 }
4767 *str = p;
4768 return PARSE_OPERAND_SUCCESS;
4769}
4770
4771static int
4772parse_address (char **str, int i)
4773{
4774 return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS
4775 ? SUCCESS : FAIL;
4776}
4777
4778static parse_operand_result
4779parse_address_group_reloc (char **str, int i, group_reloc_type type)
4780{
4781 return parse_address_main (str, i, 1, type);
4782}
4783
4784/* Parse an operand for a MOVW or MOVT instruction. */
4785static int
4786parse_half (char **str)
4787{
4788 char * p;
4789
4790 p = *str;
4791 skip_past_char (&p, '#');
4792 if (strncasecmp (p, ":lower16:", 9) == 0)
4793 inst.reloc.type = BFD_RELOC_ARM_MOVW;
4794 else if (strncasecmp (p, ":upper16:", 9) == 0)
4795 inst.reloc.type = BFD_RELOC_ARM_MOVT;
4796
4797 if (inst.reloc.type != BFD_RELOC_UNUSED)
4798 {
4799 p += 9;
4800 skip_whitespace(p);
4801 }
4802
4803 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4804 return FAIL;
4805
4806 if (inst.reloc.type == BFD_RELOC_UNUSED)
4807 {
4808 if (inst.reloc.exp.X_op != O_constant)
4809 {
4810 inst.error = _("constant expression expected");
4811 return FAIL;
4812 }
4813 if (inst.reloc.exp.X_add_number < 0
4814 || inst.reloc.exp.X_add_number > 0xffff)
4815 {
4816 inst.error = _("immediate value out of range");
4817 return FAIL;
4818 }
4819 }
4820 *str = p;
4821 return SUCCESS;
4822}
4823
4824/* Miscellaneous. */
4825
4826/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4827 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4828static int
4829parse_psr (char **str)
4830{
4831 char *p;
4832 unsigned long psr_field;
4833 const struct asm_psr *psr;
4834 char *start;
4835
4836 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4837 feature for ease of use and backwards compatibility. */
4838 p = *str;
4839 if (strncasecmp (p, "SPSR", 4) == 0)
4840 psr_field = SPSR_BIT;
4841 else if (strncasecmp (p, "CPSR", 4) == 0)
4842 psr_field = 0;
4843 else
4844 {
4845 start = p;
4846 do
4847 p++;
4848 while (ISALNUM (*p) || *p == '_');
4849
4850 psr = hash_find_n (arm_v7m_psr_hsh, start, p - start);
4851 if (!psr)
4852 return FAIL;
4853
4854 *str = p;
4855 return psr->field;
4856 }
4857
4858 p += 4;
4859 if (*p == '_')
4860 {
4861 /* A suffix follows. */
4862 p++;
4863 start = p;
4864
4865 do
4866 p++;
4867 while (ISALNUM (*p) || *p == '_');
4868
4869 psr = hash_find_n (arm_psr_hsh, start, p - start);
4870 if (!psr)
4871 goto error;
4872
4873 psr_field |= psr->field;
4874 }
4875 else
4876 {
4877 if (ISALNUM (*p))
4878 goto error; /* Garbage after "[CS]PSR". */
4879
4880 psr_field |= (PSR_c | PSR_f);
4881 }
4882 *str = p;
4883 return psr_field;
4884
4885 error:
4886 inst.error = _("flag for {c}psr instruction expected");
4887 return FAIL;
4888}
4889
4890/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4891 value suitable for splatting into the AIF field of the instruction. */
4892
4893static int
4894parse_cps_flags (char **str)
4895{
4896 int val = 0;
4897 int saw_a_flag = 0;
4898 char *s = *str;
4899
4900 for (;;)
4901 switch (*s++)
4902 {
4903 case '\0': case ',':
4904 goto done;
4905
4906 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
4907 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
4908 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
4909
4910 default:
4911 inst.error = _("unrecognized CPS flag");
4912 return FAIL;
4913 }
4914
4915 done:
4916 if (saw_a_flag == 0)
4917 {
4918 inst.error = _("missing CPS flags");
4919 return FAIL;
4920 }
4921
4922 *str = s - 1;
4923 return val;
4924}
4925
4926/* Parse an endian specifier ("BE" or "LE", case insensitive);
4927 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4928
4929static int
4930parse_endian_specifier (char **str)
4931{
4932 int little_endian;
4933 char *s = *str;
4934
4935 if (strncasecmp (s, "BE", 2))
4936 little_endian = 0;
4937 else if (strncasecmp (s, "LE", 2))
4938 little_endian = 1;
4939 else
4940 {
4941 inst.error = _("valid endian specifiers are be or le");
4942 return FAIL;
4943 }
4944
4945 if (ISALNUM (s[2]) || s[2] == '_')
4946 {
4947 inst.error = _("valid endian specifiers are be or le");
4948 return FAIL;
4949 }
4950
4951 *str = s + 2;
4952 return little_endian;
4953}
4954
4955/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
4956 value suitable for poking into the rotate field of an sxt or sxta
4957 instruction, or FAIL on error. */
4958
4959static int
4960parse_ror (char **str)
4961{
4962 int rot;
4963 char *s = *str;
4964
4965 if (strncasecmp (s, "ROR", 3) == 0)
4966 s += 3;
4967 else
4968 {
4969 inst.error = _("missing rotation field after comma");
4970 return FAIL;
4971 }
4972
4973 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
4974 return FAIL;
4975
4976 switch (rot)
4977 {
4978 case 0: *str = s; return 0x0;
4979 case 8: *str = s; return 0x1;
4980 case 16: *str = s; return 0x2;
4981 case 24: *str = s; return 0x3;
4982
4983 default:
4984 inst.error = _("rotation can only be 0, 8, 16, or 24");
4985 return FAIL;
4986 }
4987}
4988
4989/* Parse a conditional code (from conds[] below). The value returned is in the
4990 range 0 .. 14, or FAIL. */
4991static int
4992parse_cond (char **str)
4993{
4994 char *p, *q;
4995 const struct asm_cond *c;
4996
4997 p = q = *str;
4998 while (ISALPHA (*q))
4999 q++;
5000
5001 c = hash_find_n (arm_cond_hsh, p, q - p);
5002 if (!c)
5003 {
5004 inst.error = _("condition required");
5005 return FAIL;
5006 }
5007
5008 *str = q;
5009 return c->value;
5010}
5011
5012/* Parse an option for a barrier instruction. Returns the encoding for the
5013 option, or FAIL. */
5014static int
5015parse_barrier (char **str)
5016{
5017 char *p, *q;
5018 const struct asm_barrier_opt *o;
5019
5020 p = q = *str;
5021 while (ISALPHA (*q))
5022 q++;
5023
5024 o = hash_find_n (arm_barrier_opt_hsh, p, q - p);
5025 if (!o)
5026 return FAIL;
5027
5028 *str = q;
5029 return o->value;
5030}
5031
5032/* Parse the operands of a table branch instruction. Similar to a memory
5033 operand. */
5034static int
5035parse_tb (char **str)
5036{
5037 char * p = *str;
5038 int reg;
5039
5040 if (skip_past_char (&p, '[') == FAIL)
5041 {
5042 inst.error = _("'[' expected");
5043 return FAIL;
5044 }
5045
5046 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5047 {
5048 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5049 return FAIL;
5050 }
5051 inst.operands[0].reg = reg;
5052
5053 if (skip_past_comma (&p) == FAIL)
5054 {
5055 inst.error = _("',' expected");
5056 return FAIL;
5057 }
5058
5059 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5060 {
5061 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5062 return FAIL;
5063 }
5064 inst.operands[0].imm = reg;
5065
5066 if (skip_past_comma (&p) == SUCCESS)
5067 {
5068 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5069 return FAIL;
5070 if (inst.reloc.exp.X_add_number != 1)
5071 {
5072 inst.error = _("invalid shift");
5073 return FAIL;
5074 }
5075 inst.operands[0].shifted = 1;
5076 }
5077
5078 if (skip_past_char (&p, ']') == FAIL)
5079 {
5080 inst.error = _("']' expected");
5081 return FAIL;
5082 }
5083 *str = p;
5084 return SUCCESS;
5085}
5086
5087/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5088 information on the types the operands can take and how they are encoded.
5089 Up to four operands may be read; this function handles setting the
5090 ".present" field for each read operand itself.
5091 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5092 else returns FAIL. */
5093
5094static int
5095parse_neon_mov (char **str, int *which_operand)
5096{
5097 int i = *which_operand, val;
5098 enum arm_reg_type rtype;
5099 char *ptr = *str;
5100 struct neon_type_el optype;
5101
5102 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5103 {
5104 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5105 inst.operands[i].reg = val;
5106 inst.operands[i].isscalar = 1;
5107 inst.operands[i].vectype = optype;
5108 inst.operands[i++].present = 1;
5109
5110 if (skip_past_comma (&ptr) == FAIL)
5111 goto wanted_comma;
5112
5113 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5114 goto wanted_arm;
5115
5116 inst.operands[i].reg = val;
5117 inst.operands[i].isreg = 1;
5118 inst.operands[i].present = 1;
5119 }
5120 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5121 != FAIL)
5122 {
5123 /* Cases 0, 1, 2, 3, 5 (D only). */
5124 if (skip_past_comma (&ptr) == FAIL)
5125 goto wanted_comma;
5126
5127 inst.operands[i].reg = val;
5128 inst.operands[i].isreg = 1;
5129 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5130 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5131 inst.operands[i].isvec = 1;
5132 inst.operands[i].vectype = optype;
5133 inst.operands[i++].present = 1;
5134
5135 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5136 {
5137 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5138 Case 13: VMOV <Sd>, <Rm> */
5139 inst.operands[i].reg = val;
5140 inst.operands[i].isreg = 1;
5141 inst.operands[i].present = 1;
5142
5143 if (rtype == REG_TYPE_NQ)
5144 {
5145 first_error (_("can't use Neon quad register here"));
5146 return FAIL;
5147 }
5148 else if (rtype != REG_TYPE_VFS)
5149 {
5150 i++;
5151 if (skip_past_comma (&ptr) == FAIL)
5152 goto wanted_comma;
5153 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5154 goto wanted_arm;
5155 inst.operands[i].reg = val;
5156 inst.operands[i].isreg = 1;
5157 inst.operands[i].present = 1;
5158 }
5159 }
5160 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5161 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5162 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5163 Case 10: VMOV.F32 <Sd>, #<imm>
5164 Case 11: VMOV.F64 <Dd>, #<imm> */
5165 inst.operands[i].immisfloat = 1;
5166 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5167 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5168 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5169 ;
5170 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5171 &optype)) != FAIL)
5172 {
5173 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5174 Case 1: VMOV<c><q> <Dd>, <Dm>
5175 Case 8: VMOV.F32 <Sd>, <Sm>
5176 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5177
5178 inst.operands[i].reg = val;
5179 inst.operands[i].isreg = 1;
5180 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5181 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5182 inst.operands[i].isvec = 1;
5183 inst.operands[i].vectype = optype;
5184 inst.operands[i].present = 1;
5185
5186 if (skip_past_comma (&ptr) == SUCCESS)
5187 {
5188 /* Case 15. */
5189 i++;
5190
5191 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5192 goto wanted_arm;
5193
5194 inst.operands[i].reg = val;
5195 inst.operands[i].isreg = 1;
5196 inst.operands[i++].present = 1;
5197
5198 if (skip_past_comma (&ptr) == FAIL)
5199 goto wanted_comma;
5200
5201 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5202 goto wanted_arm;
5203
5204 inst.operands[i].reg = val;
5205 inst.operands[i].isreg = 1;
5206 inst.operands[i++].present = 1;
5207 }
5208 }
5209 else
5210 {
5211 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5212 return FAIL;
5213 }
5214 }
5215 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5216 {
5217 /* Cases 6, 7. */
5218 inst.operands[i].reg = val;
5219 inst.operands[i].isreg = 1;
5220 inst.operands[i++].present = 1;
5221
5222 if (skip_past_comma (&ptr) == FAIL)
5223 goto wanted_comma;
5224
5225 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5226 {
5227 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5228 inst.operands[i].reg = val;
5229 inst.operands[i].isscalar = 1;
5230 inst.operands[i].present = 1;
5231 inst.operands[i].vectype = optype;
5232 }
5233 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5234 {
5235 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5236 inst.operands[i].reg = val;
5237 inst.operands[i].isreg = 1;
5238 inst.operands[i++].present = 1;
5239
5240 if (skip_past_comma (&ptr) == FAIL)
5241 goto wanted_comma;
5242
5243 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
5244 == FAIL)
5245 {
5246 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
5247 return FAIL;
5248 }
5249
5250 inst.operands[i].reg = val;
5251 inst.operands[i].isreg = 1;
5252 inst.operands[i].isvec = 1;
5253 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5254 inst.operands[i].vectype = optype;
5255 inst.operands[i].present = 1;
5256
5257 if (rtype == REG_TYPE_VFS)
5258 {
5259 /* Case 14. */
5260 i++;
5261 if (skip_past_comma (&ptr) == FAIL)
5262 goto wanted_comma;
5263 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
5264 &optype)) == FAIL)
5265 {
5266 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
5267 return FAIL;
5268 }
5269 inst.operands[i].reg = val;
5270 inst.operands[i].isreg = 1;
5271 inst.operands[i].isvec = 1;
5272 inst.operands[i].issingle = 1;
5273 inst.operands[i].vectype = optype;
5274 inst.operands[i].present = 1;
5275 }
5276 }
5277 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
5278 != FAIL)
5279 {
5280 /* Case 13. */
5281 inst.operands[i].reg = val;
5282 inst.operands[i].isreg = 1;
5283 inst.operands[i].isvec = 1;
5284 inst.operands[i].issingle = 1;
5285 inst.operands[i].vectype = optype;
5286 inst.operands[i++].present = 1;
5287 }
5288 }
5289 else
5290 {
5291 first_error (_("parse error"));
5292 return FAIL;
5293 }
5294
5295 /* Successfully parsed the operands. Update args. */
5296 *which_operand = i;
5297 *str = ptr;
5298 return SUCCESS;
5299
5300 wanted_comma:
5301 first_error (_("expected comma"));
5302 return FAIL;
5303
5304 wanted_arm:
5305 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
5306 return FAIL;
5307}
5308
5309/* Matcher codes for parse_operands. */
5310enum operand_parse_code
5311{
5312 OP_stop, /* end of line */
5313
5314 OP_RR, /* ARM register */
5315 OP_RRnpc, /* ARM register, not r15 */
5316 OP_RRnpcb, /* ARM register, not r15, in square brackets */
5317 OP_RRw, /* ARM register, not r15, optional trailing ! */
5318 OP_RCP, /* Coprocessor number */
5319 OP_RCN, /* Coprocessor register */
5320 OP_RF, /* FPA register */
5321 OP_RVS, /* VFP single precision register */
5322 OP_RVD, /* VFP double precision register (0..15) */
5323 OP_RND, /* Neon double precision register (0..31) */
5324 OP_RNQ, /* Neon quad precision register */
5325 OP_RVSD, /* VFP single or double precision register */
5326 OP_RNDQ, /* Neon double or quad precision register */
5327 OP_RNSDQ, /* Neon single, double or quad precision register */
5328 OP_RNSC, /* Neon scalar D[X] */
5329 OP_RVC, /* VFP control register */
5330 OP_RMF, /* Maverick F register */
5331 OP_RMD, /* Maverick D register */
5332 OP_RMFX, /* Maverick FX register */
5333 OP_RMDX, /* Maverick DX register */
5334 OP_RMAX, /* Maverick AX register */
5335 OP_RMDS, /* Maverick DSPSC register */
5336 OP_RIWR, /* iWMMXt wR register */
5337 OP_RIWC, /* iWMMXt wC register */
5338 OP_RIWG, /* iWMMXt wCG register */
5339 OP_RXA, /* XScale accumulator register */
5340
5341 OP_REGLST, /* ARM register list */
5342 OP_VRSLST, /* VFP single-precision register list */
5343 OP_VRDLST, /* VFP double-precision register list */
5344 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
5345 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
5346 OP_NSTRLST, /* Neon element/structure list */
5347
5348 OP_NILO, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5349 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
5350 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
5351 OP_RR_RNSC, /* ARM reg or Neon scalar. */
5352 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
5353 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
5354 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
5355 OP_VMOV, /* Neon VMOV operands. */
5356 OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN. */
5357 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
5358 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5359
5360 OP_I0, /* immediate zero */
5361 OP_I7, /* immediate value 0 .. 7 */
5362 OP_I15, /* 0 .. 15 */
5363 OP_I16, /* 1 .. 16 */
5364 OP_I16z, /* 0 .. 16 */
5365 OP_I31, /* 0 .. 31 */
5366 OP_I31w, /* 0 .. 31, optional trailing ! */
5367 OP_I32, /* 1 .. 32 */
5368 OP_I32z, /* 0 .. 32 */
5369 OP_I63, /* 0 .. 63 */
5370 OP_I63s, /* -64 .. 63 */
5371 OP_I64, /* 1 .. 64 */
5372 OP_I64z, /* 0 .. 64 */
5373 OP_I255, /* 0 .. 255 */
5374
5375 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
5376 OP_I7b, /* 0 .. 7 */
5377 OP_I15b, /* 0 .. 15 */
5378 OP_I31b, /* 0 .. 31 */
5379
5380 OP_SH, /* shifter operand */
5381 OP_SHG, /* shifter operand with possible group relocation */
5382 OP_ADDR, /* Memory address expression (any mode) */
5383 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
5384 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
5385 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
5386 OP_EXP, /* arbitrary expression */
5387 OP_EXPi, /* same, with optional immediate prefix */
5388 OP_EXPr, /* same, with optional relocation suffix */
5389 OP_HALF, /* 0 .. 65535 or low/high reloc. */
5390
5391 OP_CPSF, /* CPS flags */
5392 OP_ENDI, /* Endianness specifier */
5393 OP_PSR, /* CPSR/SPSR mask for msr */
5394 OP_COND, /* conditional code */
5395 OP_TB, /* Table branch. */
5396
5397 OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */
5398 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
5399
5400 OP_RRnpc_I0, /* ARM register or literal 0 */
5401 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
5402 OP_RR_EXi, /* ARM register or expression with imm prefix */
5403 OP_RF_IF, /* FPA register or immediate */
5404 OP_RIWR_RIWC, /* iWMMXt R or C reg */
5405 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
5406
5407 /* Optional operands. */
5408 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
5409 OP_oI31b, /* 0 .. 31 */
5410 OP_oI32b, /* 1 .. 32 */
5411 OP_oIffffb, /* 0 .. 65535 */
5412 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
5413
5414 OP_oRR, /* ARM register */
5415 OP_oRRnpc, /* ARM register, not the PC */
5416 OP_oRRw, /* ARM register, not r15, optional trailing ! */
5417 OP_oRND, /* Optional Neon double precision register */
5418 OP_oRNQ, /* Optional Neon quad precision register */
5419 OP_oRNDQ, /* Optional Neon double or quad precision register */
5420 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
5421 OP_oSHll, /* LSL immediate */
5422 OP_oSHar, /* ASR immediate */
5423 OP_oSHllar, /* LSL or ASR immediate */
5424 OP_oROR, /* ROR 0/8/16/24 */
5425 OP_oBARRIER, /* Option argument for a barrier instruction. */
5426
5427 OP_FIRST_OPTIONAL = OP_oI7b
5428};
5429
5430/* Generic instruction operand parser. This does no encoding and no
5431 semantic validation; it merely squirrels values away in the inst
5432 structure. Returns SUCCESS or FAIL depending on whether the
5433 specified grammar matched. */
5434static int
5435parse_operands (char *str, const unsigned char *pattern)
5436{
5437 unsigned const char *upat = pattern;
5438 char *backtrack_pos = 0;
5439 const char *backtrack_error = 0;
5440 int i, val, backtrack_index = 0;
5441 enum arm_reg_type rtype;
5442 parse_operand_result result;
5443
5444#define po_char_or_fail(chr) do { \
5445 if (skip_past_char (&str, chr) == FAIL) \
5446 goto bad_args; \
5447} while (0)
5448
5449#define po_reg_or_fail(regtype) do { \
5450 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5451 &inst.operands[i].vectype); \
5452 if (val == FAIL) \
5453 { \
5454 first_error (_(reg_expected_msgs[regtype])); \
5455 goto failure; \
5456 } \
5457 inst.operands[i].reg = val; \
5458 inst.operands[i].isreg = 1; \
5459 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5460 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5461 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5462 || rtype == REG_TYPE_VFD \
5463 || rtype == REG_TYPE_NQ); \
5464} while (0)
5465
5466#define po_reg_or_goto(regtype, label) do { \
5467 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5468 &inst.operands[i].vectype); \
5469 if (val == FAIL) \
5470 goto label; \
5471 \
5472 inst.operands[i].reg = val; \
5473 inst.operands[i].isreg = 1; \
5474 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5475 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5476 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5477 || rtype == REG_TYPE_VFD \
5478 || rtype == REG_TYPE_NQ); \
5479} while (0)
5480
5481#define po_imm_or_fail(min, max, popt) do { \
5482 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5483 goto failure; \
5484 inst.operands[i].imm = val; \
5485} while (0)
5486
5487#define po_scalar_or_goto(elsz, label) do { \
5488 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5489 if (val == FAIL) \
5490 goto label; \
5491 inst.operands[i].reg = val; \
5492 inst.operands[i].isscalar = 1; \
5493} while (0)
5494
5495#define po_misc_or_fail(expr) do { \
5496 if (expr) \
5497 goto failure; \
5498} while (0)
5499
5500#define po_misc_or_fail_no_backtrack(expr) do { \
5501 result = expr; \
5502 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5503 backtrack_pos = 0; \
5504 if (result != PARSE_OPERAND_SUCCESS) \
5505 goto failure; \
5506} while (0)
5507
5508 skip_whitespace (str);
5509
5510 for (i = 0; upat[i] != OP_stop; i++)
5511 {
5512 if (upat[i] >= OP_FIRST_OPTIONAL)
5513 {
5514 /* Remember where we are in case we need to backtrack. */
5515 assert (!backtrack_pos);
5516 backtrack_pos = str;
5517 backtrack_error = inst.error;
5518 backtrack_index = i;
5519 }
5520
5521 if (i > 0 && (i > 1 || inst.operands[0].present))
5522 po_char_or_fail (',');
5523
5524 switch (upat[i])
5525 {
5526 /* Registers */
5527 case OP_oRRnpc:
5528 case OP_RRnpc:
5529 case OP_oRR:
5530 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
5531 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
5532 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
5533 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
5534 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
5535 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
5536 case OP_oRND:
5537 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
5538 case OP_RVC:
5539 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
5540 break;
5541 /* Also accept generic coprocessor regs for unknown registers. */
5542 coproc_reg:
5543 po_reg_or_fail (REG_TYPE_CN);
5544 break;
5545 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
5546 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
5547 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
5548 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
5549 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
5550 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
5551 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
5552 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
5553 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
5554 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
5555 case OP_oRNQ:
5556 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
5557 case OP_oRNDQ:
5558 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
5559 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
5560 case OP_oRNSDQ:
5561 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
5562
5563 /* Neon scalar. Using an element size of 8 means that some invalid
5564 scalars are accepted here, so deal with those in later code. */
5565 case OP_RNSC: po_scalar_or_goto (8, failure); break;
5566
5567 /* WARNING: We can expand to two operands here. This has the potential
5568 to totally confuse the backtracking mechanism! It will be OK at
5569 least as long as we don't try to use optional args as well,
5570 though. */
5571 case OP_NILO:
5572 {
5573 po_reg_or_goto (REG_TYPE_NDQ, try_imm);
5574 inst.operands[i].present = 1;
5575 i++;
5576 skip_past_comma (&str);
5577 po_reg_or_goto (REG_TYPE_NDQ, one_reg_only);
5578 break;
5579 one_reg_only:
5580 /* Optional register operand was omitted. Unfortunately, it's in
5581 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5582 here (this is a bit grotty). */
5583 inst.operands[i] = inst.operands[i-1];
5584 inst.operands[i-1].present = 0;
5585 break;
5586 try_imm:
5587 /* There's a possibility of getting a 64-bit immediate here, so
5588 we need special handling. */
5589 if (parse_big_immediate (&str, i) == FAIL)
5590 {
5591 inst.error = _("immediate value is out of range");
5592 goto failure;
5593 }
5594 }
5595 break;
5596
5597 case OP_RNDQ_I0:
5598 {
5599 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
5600 break;
5601 try_imm0:
5602 po_imm_or_fail (0, 0, TRUE);
5603 }
5604 break;
5605
5606 case OP_RVSD_I0:
5607 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
5608 break;
5609
5610 case OP_RR_RNSC:
5611 {
5612 po_scalar_or_goto (8, try_rr);
5613 break;
5614 try_rr:
5615 po_reg_or_fail (REG_TYPE_RN);
5616 }
5617 break;
5618
5619 case OP_RNSDQ_RNSC:
5620 {
5621 po_scalar_or_goto (8, try_nsdq);
5622 break;
5623 try_nsdq:
5624 po_reg_or_fail (REG_TYPE_NSDQ);
5625 }
5626 break;
5627
5628 case OP_RNDQ_RNSC:
5629 {
5630 po_scalar_or_goto (8, try_ndq);
5631 break;
5632 try_ndq:
5633 po_reg_or_fail (REG_TYPE_NDQ);
5634 }
5635 break;
5636
5637 case OP_RND_RNSC:
5638 {
5639 po_scalar_or_goto (8, try_vfd);
5640 break;
5641 try_vfd:
5642 po_reg_or_fail (REG_TYPE_VFD);
5643 }
5644 break;
5645
5646 case OP_VMOV:
5647 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5648 not careful then bad things might happen. */
5649 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
5650 break;
5651
5652 case OP_RNDQ_IMVNb:
5653 {
5654 po_reg_or_goto (REG_TYPE_NDQ, try_mvnimm);
5655 break;
5656 try_mvnimm:
5657 /* There's a possibility of getting a 64-bit immediate here, so
5658 we need special handling. */
5659 if (parse_big_immediate (&str, i) == FAIL)
5660 {
5661 inst.error = _("immediate value is out of range");
5662 goto failure;
5663 }
5664 }
5665 break;
5666
5667 case OP_RNDQ_I63b:
5668 {
5669 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
5670 break;
5671 try_shimm:
5672 po_imm_or_fail (0, 63, TRUE);
5673 }
5674 break;
5675
5676 case OP_RRnpcb:
5677 po_char_or_fail ('[');
5678 po_reg_or_fail (REG_TYPE_RN);
5679 po_char_or_fail (']');
5680 break;
5681
5682 case OP_RRw:
5683 case OP_oRRw:
5684 po_reg_or_fail (REG_TYPE_RN);
5685 if (skip_past_char (&str, '!') == SUCCESS)
5686 inst.operands[i].writeback = 1;
5687 break;
5688
5689 /* Immediates */
5690 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
5691 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
5692 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
5693 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
5694 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
5695 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
5696 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
5697 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
5698 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
5699 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
5700 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
5701 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
5702
5703 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
5704 case OP_oI7b:
5705 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
5706 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
5707 case OP_oI31b:
5708 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
5709 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
5710 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
5711
5712 /* Immediate variants */
5713 case OP_oI255c:
5714 po_char_or_fail ('{');
5715 po_imm_or_fail (0, 255, TRUE);
5716 po_char_or_fail ('}');
5717 break;
5718
5719 case OP_I31w:
5720 /* The expression parser chokes on a trailing !, so we have
5721 to find it first and zap it. */
5722 {
5723 char *s = str;
5724 while (*s && *s != ',')
5725 s++;
5726 if (s[-1] == '!')
5727 {
5728 s[-1] = '\0';
5729 inst.operands[i].writeback = 1;
5730 }
5731 po_imm_or_fail (0, 31, TRUE);
5732 if (str == s - 1)
5733 str = s;
5734 }
5735 break;
5736
5737 /* Expressions */
5738 case OP_EXPi: EXPi:
5739 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5740 GE_OPT_PREFIX));
5741 break;
5742
5743 case OP_EXP:
5744 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5745 GE_NO_PREFIX));
5746 break;
5747
5748 case OP_EXPr: EXPr:
5749 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5750 GE_NO_PREFIX));
5751 if (inst.reloc.exp.X_op == O_symbol)
5752 {
5753 val = parse_reloc (&str);
5754 if (val == -1)
5755 {
5756 inst.error = _("unrecognized relocation suffix");
5757 goto failure;
5758 }
5759 else if (val != BFD_RELOC_UNUSED)
5760 {
5761 inst.operands[i].imm = val;
5762 inst.operands[i].hasreloc = 1;
5763 }
5764 }
5765 break;
5766
5767 /* Operand for MOVW or MOVT. */
5768 case OP_HALF:
5769 po_misc_or_fail (parse_half (&str));
5770 break;
5771
5772 /* Register or expression */
5773 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
5774 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
5775
5776 /* Register or immediate */
5777 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
5778 I0: po_imm_or_fail (0, 0, FALSE); break;
5779
5780 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
5781 IF:
5782 if (!is_immediate_prefix (*str))
5783 goto bad_args;
5784 str++;
5785 val = parse_fpa_immediate (&str);
5786 if (val == FAIL)
5787 goto failure;
5788 /* FPA immediates are encoded as registers 8-15.
5789 parse_fpa_immediate has already applied the offset. */
5790 inst.operands[i].reg = val;
5791 inst.operands[i].isreg = 1;
5792 break;
5793
5794 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
5795 I32z: po_imm_or_fail (0, 32, FALSE); break;
5796
5797 /* Two kinds of register */
5798 case OP_RIWR_RIWC:
5799 {
5800 struct reg_entry *rege = arm_reg_parse_multi (&str);
5801 if (!rege
5802 || (rege->type != REG_TYPE_MMXWR
5803 && rege->type != REG_TYPE_MMXWC
5804 && rege->type != REG_TYPE_MMXWCG))
5805 {
5806 inst.error = _("iWMMXt data or control register expected");
5807 goto failure;
5808 }
5809 inst.operands[i].reg = rege->number;
5810 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
5811 }
5812 break;
5813
5814 case OP_RIWC_RIWG:
5815 {
5816 struct reg_entry *rege = arm_reg_parse_multi (&str);
5817 if (!rege
5818 || (rege->type != REG_TYPE_MMXWC
5819 && rege->type != REG_TYPE_MMXWCG))
5820 {
5821 inst.error = _("iWMMXt control register expected");
5822 goto failure;
5823 }
5824 inst.operands[i].reg = rege->number;
5825 inst.operands[i].isreg = 1;
5826 }
5827 break;
5828
5829 /* Misc */
5830 case OP_CPSF: val = parse_cps_flags (&str); break;
5831 case OP_ENDI: val = parse_endian_specifier (&str); break;
5832 case OP_oROR: val = parse_ror (&str); break;
5833 case OP_PSR: val = parse_psr (&str); break;
5834 case OP_COND: val = parse_cond (&str); break;
5835 case OP_oBARRIER:val = parse_barrier (&str); break;
5836
5837 case OP_RVC_PSR:
5838 po_reg_or_goto (REG_TYPE_VFC, try_psr);
5839 inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */
5840 break;
5841 try_psr:
5842 val = parse_psr (&str);
5843 break;
5844
5845 case OP_APSR_RR:
5846 po_reg_or_goto (REG_TYPE_RN, try_apsr);
5847 break;
5848 try_apsr:
5849 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5850 instruction). */
5851 if (strncasecmp (str, "APSR_", 5) == 0)
5852 {
5853 unsigned found = 0;
5854 str += 5;
5855 while (found < 15)
5856 switch (*str++)
5857 {
5858 case 'c': found = (found & 1) ? 16 : found | 1; break;
5859 case 'n': found = (found & 2) ? 16 : found | 2; break;
5860 case 'z': found = (found & 4) ? 16 : found | 4; break;
5861 case 'v': found = (found & 8) ? 16 : found | 8; break;
5862 default: found = 16;
5863 }
5864 if (found != 15)
5865 goto failure;
5866 inst.operands[i].isvec = 1;
5867 }
5868 else
5869 goto failure;
5870 break;
5871
5872 case OP_TB:
5873 po_misc_or_fail (parse_tb (&str));
5874 break;
5875
5876 /* Register lists */
5877 case OP_REGLST:
5878 val = parse_reg_list (&str);
5879 if (*str == '^')
5880 {
5881 inst.operands[1].writeback = 1;
5882 str++;
5883 }
5884 break;
5885
5886 case OP_VRSLST:
5887 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
5888 break;
5889
5890 case OP_VRDLST:
5891 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
5892 break;
5893
5894 case OP_VRSDLST:
5895 /* Allow Q registers too. */
5896 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5897 REGLIST_NEON_D);
5898 if (val == FAIL)
5899 {
5900 inst.error = NULL;
5901 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5902 REGLIST_VFP_S);
5903 inst.operands[i].issingle = 1;
5904 }
5905 break;
5906
5907 case OP_NRDLST:
5908 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5909 REGLIST_NEON_D);
5910 break;
5911
5912 case OP_NSTRLST:
5913 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
5914 &inst.operands[i].vectype);
5915 break;
5916
5917 /* Addressing modes */
5918 case OP_ADDR:
5919 po_misc_or_fail (parse_address (&str, i));
5920 break;
5921
5922 case OP_ADDRGLDR:
5923 po_misc_or_fail_no_backtrack (
5924 parse_address_group_reloc (&str, i, GROUP_LDR));
5925 break;
5926
5927 case OP_ADDRGLDRS:
5928 po_misc_or_fail_no_backtrack (
5929 parse_address_group_reloc (&str, i, GROUP_LDRS));
5930 break;
5931
5932 case OP_ADDRGLDC:
5933 po_misc_or_fail_no_backtrack (
5934 parse_address_group_reloc (&str, i, GROUP_LDC));
5935 break;
5936
5937 case OP_SH:
5938 po_misc_or_fail (parse_shifter_operand (&str, i));
5939 break;
5940
5941 case OP_SHG:
5942 po_misc_or_fail_no_backtrack (
5943 parse_shifter_operand_group_reloc (&str, i));
5944 break;
5945
5946 case OP_oSHll:
5947 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
5948 break;
5949
5950 case OP_oSHar:
5951 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
5952 break;
5953
5954 case OP_oSHllar:
5955 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
5956 break;
5957
5958 default:
5959 as_fatal ("unhandled operand code %d", upat[i]);
5960 }
5961
5962 /* Various value-based sanity checks and shared operations. We
5963 do not signal immediate failures for the register constraints;
5964 this allows a syntax error to take precedence. */
5965 switch (upat[i])
5966 {
5967 case OP_oRRnpc:
5968 case OP_RRnpc:
5969 case OP_RRnpcb:
5970 case OP_RRw:
5971 case OP_oRRw:
5972 case OP_RRnpc_I0:
5973 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
5974 inst.error = BAD_PC;
5975 break;
5976
5977 case OP_CPSF:
5978 case OP_ENDI:
5979 case OP_oROR:
5980 case OP_PSR:
5981 case OP_RVC_PSR:
5982 case OP_COND:
5983 case OP_oBARRIER:
5984 case OP_REGLST:
5985 case OP_VRSLST:
5986 case OP_VRDLST:
5987 case OP_VRSDLST:
5988 case OP_NRDLST:
5989 case OP_NSTRLST:
5990 if (val == FAIL)
5991 goto failure;
5992 inst.operands[i].imm = val;
5993 break;
5994
5995 default:
5996 break;
5997 }
5998
5999 /* If we get here, this operand was successfully parsed. */
6000 inst.operands[i].present = 1;
6001 continue;
6002
6003 bad_args:
6004 inst.error = BAD_ARGS;
6005
6006 failure:
6007 if (!backtrack_pos)
6008 {
6009 /* The parse routine should already have set inst.error, but set a
6010 defaut here just in case. */
6011 if (!inst.error)
6012 inst.error = _("syntax error");
6013 return FAIL;
6014 }
6015
6016 /* Do not backtrack over a trailing optional argument that
6017 absorbed some text. We will only fail again, with the
6018 'garbage following instruction' error message, which is
6019 probably less helpful than the current one. */
6020 if (backtrack_index == i && backtrack_pos != str
6021 && upat[i+1] == OP_stop)
6022 {
6023 if (!inst.error)
6024 inst.error = _("syntax error");
6025 return FAIL;
6026 }
6027
6028 /* Try again, skipping the optional argument at backtrack_pos. */
6029 str = backtrack_pos;
6030 inst.error = backtrack_error;
6031 inst.operands[backtrack_index].present = 0;
6032 i = backtrack_index;
6033 backtrack_pos = 0;
6034 }
6035
6036 /* Check that we have parsed all the arguments. */
6037 if (*str != '\0' && !inst.error)
6038 inst.error = _("garbage following instruction");
6039
6040 return inst.error ? FAIL : SUCCESS;
6041}
6042
6043#undef po_char_or_fail
6044#undef po_reg_or_fail
6045#undef po_reg_or_goto
6046#undef po_imm_or_fail
6047#undef po_scalar_or_fail
6048
6049/* Shorthand macro for instruction encoding functions issuing errors. */
6050#define constraint(expr, err) do { \
6051 if (expr) \
6052 { \
6053 inst.error = err; \
6054 return; \
6055 } \
6056} while (0)
6057
6058/* Functions for operand encoding. ARM, then Thumb. */
6059
6060#define rotate_left(v, n) (v << n | v >> (32 - n))
6061
6062/* If VAL can be encoded in the immediate field of an ARM instruction,
6063 return the encoded form. Otherwise, return FAIL. */
6064
6065static unsigned int
6066encode_arm_immediate (unsigned int val)
6067{
6068 unsigned int a, i;
6069
6070 for (i = 0; i < 32; i += 2)
6071 if ((a = rotate_left (val, i)) <= 0xff)
6072 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6073
6074 return FAIL;
6075}
6076
6077/* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6078 return the encoded form. Otherwise, return FAIL. */
6079static unsigned int
6080encode_thumb32_immediate (unsigned int val)
6081{
6082 unsigned int a, i;
6083
6084 if (val <= 0xff)
6085 return val;
6086
6087 for (i = 1; i <= 24; i++)
6088 {
6089 a = val >> i;
6090 if ((val & ~(0xff << i)) == 0)
6091 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6092 }
6093
6094 a = val & 0xff;
6095 if (val == ((a << 16) | a))
6096 return 0x100 | a;
6097 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6098 return 0x300 | a;
6099
6100 a = val & 0xff00;
6101 if (val == ((a << 16) | a))
6102 return 0x200 | (a >> 8);
6103
6104 return FAIL;
6105}
6106/* Encode a VFP SP or DP register number into inst.instruction. */
6107
6108static void
6109encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6110{
6111 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6112 && reg > 15)
6113 {
6114 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
6115 {
6116 if (thumb_mode)
6117 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6118 fpu_vfp_ext_v3);
6119 else
6120 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6121 fpu_vfp_ext_v3);
6122 }
6123 else
6124 {
6125 first_error (_("D register out of range for selected VFP version"));
6126 return;
6127 }
6128 }
6129
6130 switch (pos)
6131 {
6132 case VFP_REG_Sd:
6133 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6134 break;
6135
6136 case VFP_REG_Sn:
6137 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6138 break;
6139
6140 case VFP_REG_Sm:
6141 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6142 break;
6143
6144 case VFP_REG_Dd:
6145 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
6146 break;
6147
6148 case VFP_REG_Dn:
6149 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
6150 break;
6151
6152 case VFP_REG_Dm:
6153 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
6154 break;
6155
6156 default:
6157 abort ();
6158 }
6159}
6160
6161/* Encode a <shift> in an ARM-format instruction. The immediate,
6162 if any, is handled by md_apply_fix. */
6163static void
6164encode_arm_shift (int i)
6165{
6166 if (inst.operands[i].shift_kind == SHIFT_RRX)
6167 inst.instruction |= SHIFT_ROR << 5;
6168 else
6169 {
6170 inst.instruction |= inst.operands[i].shift_kind << 5;
6171 if (inst.operands[i].immisreg)
6172 {
6173 inst.instruction |= SHIFT_BY_REG;
6174 inst.instruction |= inst.operands[i].imm << 8;
6175 }
6176 else
6177 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
6178 }
6179}
6180
6181static void
6182encode_arm_shifter_operand (int i)
6183{
6184 if (inst.operands[i].isreg)
6185 {
6186 inst.instruction |= inst.operands[i].reg;
6187 encode_arm_shift (i);
6188 }
6189 else
6190 inst.instruction |= INST_IMMEDIATE;
6191}
6192
6193/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6194static void
6195encode_arm_addr_mode_common (int i, bfd_boolean is_t)
6196{
6197 assert (inst.operands[i].isreg);
6198 inst.instruction |= inst.operands[i].reg << 16;
6199
6200 if (inst.operands[i].preind)
6201 {
6202 if (is_t)
6203 {
6204 inst.error = _("instruction does not accept preindexed addressing");
6205 return;
6206 }
6207 inst.instruction |= PRE_INDEX;
6208 if (inst.operands[i].writeback)
6209 inst.instruction |= WRITE_BACK;
6210
6211 }
6212 else if (inst.operands[i].postind)
6213 {
6214 assert (inst.operands[i].writeback);
6215 if (is_t)
6216 inst.instruction |= WRITE_BACK;
6217 }
6218 else /* unindexed - only for coprocessor */
6219 {
6220 inst.error = _("instruction does not accept unindexed addressing");
6221 return;
6222 }
6223
6224 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
6225 && (((inst.instruction & 0x000f0000) >> 16)
6226 == ((inst.instruction & 0x0000f000) >> 12)))
6227 as_warn ((inst.instruction & LOAD_BIT)
6228 ? _("destination register same as write-back base")
6229 : _("source register same as write-back base"));
6230}
6231
6232/* inst.operands[i] was set up by parse_address. Encode it into an
6233 ARM-format mode 2 load or store instruction. If is_t is true,
6234 reject forms that cannot be used with a T instruction (i.e. not
6235 post-indexed). */
6236static void
6237encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
6238{
6239 encode_arm_addr_mode_common (i, is_t);
6240
6241 if (inst.operands[i].immisreg)
6242 {
6243 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
6244 inst.instruction |= inst.operands[i].imm;
6245 if (!inst.operands[i].negative)
6246 inst.instruction |= INDEX_UP;
6247 if (inst.operands[i].shifted)
6248 {
6249 if (inst.operands[i].shift_kind == SHIFT_RRX)
6250 inst.instruction |= SHIFT_ROR << 5;
6251 else
6252 {
6253 inst.instruction |= inst.operands[i].shift_kind << 5;
6254 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
6255 }
6256 }
6257 }
6258 else /* immediate offset in inst.reloc */
6259 {
6260 if (inst.reloc.type == BFD_RELOC_UNUSED)
6261 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
6262 }
6263}
6264
6265/* inst.operands[i] was set up by parse_address. Encode it into an
6266 ARM-format mode 3 load or store instruction. Reject forms that
6267 cannot be used with such instructions. If is_t is true, reject
6268 forms that cannot be used with a T instruction (i.e. not
6269 post-indexed). */
6270static void
6271encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
6272{
6273 if (inst.operands[i].immisreg && inst.operands[i].shifted)
6274 {
6275 inst.error = _("instruction does not accept scaled register index");
6276 return;
6277 }
6278
6279 encode_arm_addr_mode_common (i, is_t);
6280
6281 if (inst.operands[i].immisreg)
6282 {
6283 inst.instruction |= inst.operands[i].imm;
6284 if (!inst.operands[i].negative)
6285 inst.instruction |= INDEX_UP;
6286 }
6287 else /* immediate offset in inst.reloc */
6288 {
6289 inst.instruction |= HWOFFSET_IMM;
6290 if (inst.reloc.type == BFD_RELOC_UNUSED)
6291 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
6292 }
6293}
6294
6295/* inst.operands[i] was set up by parse_address. Encode it into an
6296 ARM-format instruction. Reject all forms which cannot be encoded
6297 into a coprocessor load/store instruction. If wb_ok is false,
6298 reject use of writeback; if unind_ok is false, reject use of
6299 unindexed addressing. If reloc_override is not 0, use it instead
6300 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6301 (in which case it is preserved). */
6302
6303static int
6304encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
6305{
6306 inst.instruction |= inst.operands[i].reg << 16;
6307
6308 assert (!(inst.operands[i].preind && inst.operands[i].postind));
6309
6310 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
6311 {
6312 assert (!inst.operands[i].writeback);
6313 if (!unind_ok)
6314 {
6315 inst.error = _("instruction does not support unindexed addressing");
6316 return FAIL;
6317 }
6318 inst.instruction |= inst.operands[i].imm;
6319 inst.instruction |= INDEX_UP;
6320 return SUCCESS;
6321 }
6322
6323 if (inst.operands[i].preind)
6324 inst.instruction |= PRE_INDEX;
6325
6326 if (inst.operands[i].writeback)
6327 {
6328 if (inst.operands[i].reg == REG_PC)
6329 {
6330 inst.error = _("pc may not be used with write-back");
6331 return FAIL;
6332 }
6333 if (!wb_ok)
6334 {
6335 inst.error = _("instruction does not support writeback");
6336 return FAIL;
6337 }
6338 inst.instruction |= WRITE_BACK;
6339 }
6340
6341 if (reloc_override)
6342 inst.reloc.type = reloc_override;
6343 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
6344 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
6345 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
6346 {
6347 if (thumb_mode)
6348 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
6349 else
6350 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
6351 }
6352
6353 return SUCCESS;
6354}
6355
6356/* inst.reloc.exp describes an "=expr" load pseudo-operation.
6357 Determine whether it can be performed with a move instruction; if
6358 it can, convert inst.instruction to that move instruction and
6359 return 1; if it can't, convert inst.instruction to a literal-pool
6360 load and return 0. If this is not a valid thing to do in the
6361 current context, set inst.error and return 1.
6362
6363 inst.operands[i] describes the destination register. */
6364
6365static int
6366move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
6367{
6368 unsigned long tbit;
6369
6370 if (thumb_p)
6371 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
6372 else
6373 tbit = LOAD_BIT;
6374
6375 if ((inst.instruction & tbit) == 0)
6376 {
6377 inst.error = _("invalid pseudo operation");
6378 return 1;
6379 }
6380 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
6381 {
6382 inst.error = _("constant expression expected");
6383 return 1;
6384 }
6385 if (inst.reloc.exp.X_op == O_constant)
6386 {
6387 if (thumb_p)
6388 {
6389 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
6390 {
6391 /* This can be done with a mov(1) instruction. */
6392 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
6393 inst.instruction |= inst.reloc.exp.X_add_number;
6394 return 1;
6395 }
6396 }
6397 else
6398 {
6399 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
6400 if (value != FAIL)
6401 {
6402 /* This can be done with a mov instruction. */
6403 inst.instruction &= LITERAL_MASK;
6404 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
6405 inst.instruction |= value & 0xfff;
6406 return 1;
6407 }
6408
6409 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
6410 if (value != FAIL)
6411 {
6412 /* This can be done with a mvn instruction. */
6413 inst.instruction &= LITERAL_MASK;
6414 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
6415 inst.instruction |= value & 0xfff;
6416 return 1;
6417 }
6418 }
6419 }
6420
6421 if (add_to_lit_pool () == FAIL)
6422 {
6423 inst.error = _("literal pool insertion failed");
6424 return 1;
6425 }
6426 inst.operands[1].reg = REG_PC;
6427 inst.operands[1].isreg = 1;
6428 inst.operands[1].preind = 1;
6429 inst.reloc.pc_rel = 1;
6430 inst.reloc.type = (thumb_p
6431 ? BFD_RELOC_ARM_THUMB_OFFSET
6432 : (mode_3
6433 ? BFD_RELOC_ARM_HWLITERAL
6434 : BFD_RELOC_ARM_LITERAL));
6435 return 0;
6436}
6437
6438/* Functions for instruction encoding, sorted by subarchitecture.
6439 First some generics; their names are taken from the conventional
6440 bit positions for register arguments in ARM format instructions. */
6441
6442static void
6443do_noargs (void)
6444{
6445}
6446
6447static void
6448do_rd (void)
6449{
6450 inst.instruction |= inst.operands[0].reg << 12;
6451}
6452
6453static void
6454do_rd_rm (void)
6455{
6456 inst.instruction |= inst.operands[0].reg << 12;
6457 inst.instruction |= inst.operands[1].reg;
6458}
6459
6460static void
6461do_rd_rn (void)
6462{
6463 inst.instruction |= inst.operands[0].reg << 12;
6464 inst.instruction |= inst.operands[1].reg << 16;
6465}
6466
6467static void
6468do_rn_rd (void)
6469{
6470 inst.instruction |= inst.operands[0].reg << 16;
6471 inst.instruction |= inst.operands[1].reg << 12;
6472}
6473
6474static void
6475do_rd_rm_rn (void)
6476{
6477 unsigned Rn = inst.operands[2].reg;
6478 /* Enforce restrictions on SWP instruction. */
6479 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
6480 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
6481 _("Rn must not overlap other operands"));
6482 inst.instruction |= inst.operands[0].reg << 12;
6483 inst.instruction |= inst.operands[1].reg;
6484 inst.instruction |= Rn << 16;
6485}
6486
6487static void
6488do_rd_rn_rm (void)
6489{
6490 inst.instruction |= inst.operands[0].reg << 12;
6491 inst.instruction |= inst.operands[1].reg << 16;
6492 inst.instruction |= inst.operands[2].reg;
6493}
6494
6495static void
6496do_rm_rd_rn (void)
6497{
6498 inst.instruction |= inst.operands[0].reg;
6499 inst.instruction |= inst.operands[1].reg << 12;
6500 inst.instruction |= inst.operands[2].reg << 16;
6501}
6502
6503static void
6504do_imm0 (void)
6505{
6506 inst.instruction |= inst.operands[0].imm;
6507}
6508
6509static void
6510do_rd_cpaddr (void)
6511{
6512 inst.instruction |= inst.operands[0].reg << 12;
6513 encode_arm_cp_address (1, TRUE, TRUE, 0);
6514}
6515
6516/* ARM instructions, in alphabetical order by function name (except
6517 that wrapper functions appear immediately after the function they
6518 wrap). */
6519
6520/* This is a pseudo-op of the form "adr rd, label" to be converted
6521 into a relative address of the form "add rd, pc, #label-.-8". */
6522
6523static void
6524do_adr (void)
6525{
6526 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
6527
6528 /* Frag hacking will turn this into a sub instruction if the offset turns
6529 out to be negative. */
6530 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
6531 inst.reloc.pc_rel = 1;
6532 inst.reloc.exp.X_add_number -= 8;
6533}
6534
6535/* This is a pseudo-op of the form "adrl rd, label" to be converted
6536 into a relative address of the form:
6537 add rd, pc, #low(label-.-8)"
6538 add rd, rd, #high(label-.-8)" */
6539
6540static void
6541do_adrl (void)
6542{
6543 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
6544
6545 /* Frag hacking will turn this into a sub instruction if the offset turns
6546 out to be negative. */
6547 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
6548 inst.reloc.pc_rel = 1;
6549 inst.size = INSN_SIZE * 2;
6550 inst.reloc.exp.X_add_number -= 8;
6551}
6552
6553static void
6554do_arit (void)
6555{
6556 if (!inst.operands[1].present)
6557 inst.operands[1].reg = inst.operands[0].reg;
6558 inst.instruction |= inst.operands[0].reg << 12;
6559 inst.instruction |= inst.operands[1].reg << 16;
6560 encode_arm_shifter_operand (2);
6561}
6562
6563static void
6564do_barrier (void)
6565{
6566 if (inst.operands[0].present)
6567 {
6568 constraint ((inst.instruction & 0xf0) != 0x40
6569 && inst.operands[0].imm != 0xf,
6570 "bad barrier type");
6571 inst.instruction |= inst.operands[0].imm;
6572 }
6573 else
6574 inst.instruction |= 0xf;
6575}
6576
6577static void
6578do_bfc (void)
6579{
6580 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
6581 constraint (msb > 32, _("bit-field extends past end of register"));
6582 /* The instruction encoding stores the LSB and MSB,
6583 not the LSB and width. */
6584 inst.instruction |= inst.operands[0].reg << 12;
6585 inst.instruction |= inst.operands[1].imm << 7;
6586 inst.instruction |= (msb - 1) << 16;
6587}
6588
6589static void
6590do_bfi (void)
6591{
6592 unsigned int msb;
6593
6594 /* #0 in second position is alternative syntax for bfc, which is
6595 the same instruction but with REG_PC in the Rm field. */
6596 if (!inst.operands[1].isreg)
6597 inst.operands[1].reg = REG_PC;
6598
6599 msb = inst.operands[2].imm + inst.operands[3].imm;
6600 constraint (msb > 32, _("bit-field extends past end of register"));
6601 /* The instruction encoding stores the LSB and MSB,
6602 not the LSB and width. */
6603 inst.instruction |= inst.operands[0].reg << 12;
6604 inst.instruction |= inst.operands[1].reg;
6605 inst.instruction |= inst.operands[2].imm << 7;
6606 inst.instruction |= (msb - 1) << 16;
6607}
6608
6609static void
6610do_bfx (void)
6611{
6612 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
6613 _("bit-field extends past end of register"));
6614 inst.instruction |= inst.operands[0].reg << 12;
6615 inst.instruction |= inst.operands[1].reg;
6616 inst.instruction |= inst.operands[2].imm << 7;
6617 inst.instruction |= (inst.operands[3].imm - 1) << 16;
6618}
6619
6620/* ARM V5 breakpoint instruction (argument parse)
6621 BKPT <16 bit unsigned immediate>
6622 Instruction is not conditional.
6623 The bit pattern given in insns[] has the COND_ALWAYS condition,
6624 and it is an error if the caller tried to override that. */
6625
6626static void
6627do_bkpt (void)
6628{
6629 /* Top 12 of 16 bits to bits 19:8. */
6630 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
6631
6632 /* Bottom 4 of 16 bits to bits 3:0. */
6633 inst.instruction |= inst.operands[0].imm & 0xf;
6634}
6635
6636static void
6637encode_branch (int default_reloc)
6638{
6639 if (inst.operands[0].hasreloc)
6640 {
6641 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
6642 _("the only suffix valid here is '(plt)'"));
6643 inst.reloc.type = BFD_RELOC_ARM_PLT32;
6644 }
6645 else
6646 {
6647 inst.reloc.type = default_reloc;
6648 }
6649 inst.reloc.pc_rel = 1;
6650}
6651
6652static void
6653do_branch (void)
6654{
6655#ifdef OBJ_ELF
6656 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6657 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
6658 else
6659#endif
6660 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
6661}
6662
6663static void
6664do_bl (void)
6665{
6666#ifdef OBJ_ELF
6667 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6668 {
6669 if (inst.cond == COND_ALWAYS)
6670 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
6671 else
6672 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
6673 }
6674 else
6675#endif
6676 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
6677}
6678
6679/* ARM V5 branch-link-exchange instruction (argument parse)
6680 BLX <target_addr> ie BLX(1)
6681 BLX{<condition>} <Rm> ie BLX(2)
6682 Unfortunately, there are two different opcodes for this mnemonic.
6683 So, the insns[].value is not used, and the code here zaps values
6684 into inst.instruction.
6685 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6686
6687static void
6688do_blx (void)
6689{
6690 if (inst.operands[0].isreg)
6691 {
6692 /* Arg is a register; the opcode provided by insns[] is correct.
6693 It is not illegal to do "blx pc", just useless. */
6694 if (inst.operands[0].reg == REG_PC)
6695 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6696
6697 inst.instruction |= inst.operands[0].reg;
6698 }
6699 else
6700 {
6701 /* Arg is an address; this instruction cannot be executed
6702 conditionally, and the opcode must be adjusted. */
6703 constraint (inst.cond != COND_ALWAYS, BAD_COND);
6704 inst.instruction = 0xfa000000;
6705#ifdef OBJ_ELF
6706 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6707 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
6708 else
6709#endif
6710 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
6711 }
6712}
6713
6714static void
6715do_bx (void)
6716{
6717 if (inst.operands[0].reg == REG_PC)
6718 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6719
6720 inst.instruction |= inst.operands[0].reg;
6721}
6722
6723
6724/* ARM v5TEJ. Jump to Jazelle code. */
6725
6726static void
6727do_bxj (void)
6728{
6729 if (inst.operands[0].reg == REG_PC)
6730 as_tsktsk (_("use of r15 in bxj is not really useful"));
6731
6732 inst.instruction |= inst.operands[0].reg;
6733}
6734
6735/* Co-processor data operation:
6736 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6737 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6738static void
6739do_cdp (void)
6740{
6741 inst.instruction |= inst.operands[0].reg << 8;
6742 inst.instruction |= inst.operands[1].imm << 20;
6743 inst.instruction |= inst.operands[2].reg << 12;
6744 inst.instruction |= inst.operands[3].reg << 16;
6745 inst.instruction |= inst.operands[4].reg;
6746 inst.instruction |= inst.operands[5].imm << 5;
6747}
6748
6749static void
6750do_cmp (void)
6751{
6752 inst.instruction |= inst.operands[0].reg << 16;
6753 encode_arm_shifter_operand (1);
6754}
6755
6756/* Transfer between coprocessor and ARM registers.
6757 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6758 MRC2
6759 MCR{cond}
6760 MCR2
6761
6762 No special properties. */
6763
6764static void
6765do_co_reg (void)
6766{
6767 inst.instruction |= inst.operands[0].reg << 8;
6768 inst.instruction |= inst.operands[1].imm << 21;
6769 inst.instruction |= inst.operands[2].reg << 12;
6770 inst.instruction |= inst.operands[3].reg << 16;
6771 inst.instruction |= inst.operands[4].reg;
6772 inst.instruction |= inst.operands[5].imm << 5;
6773}
6774
6775/* Transfer between coprocessor register and pair of ARM registers.
6776 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6777 MCRR2
6778 MRRC{cond}
6779 MRRC2
6780
6781 Two XScale instructions are special cases of these:
6782
6783 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6784 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6785
6786 Result unpredicatable if Rd or Rn is R15. */
6787
6788static void
6789do_co_reg2c (void)
6790{
6791 inst.instruction |= inst.operands[0].reg << 8;
6792 inst.instruction |= inst.operands[1].imm << 4;
6793 inst.instruction |= inst.operands[2].reg << 12;
6794 inst.instruction |= inst.operands[3].reg << 16;
6795 inst.instruction |= inst.operands[4].reg;
6796}
6797
6798static void
6799do_cpsi (void)
6800{
6801 inst.instruction |= inst.operands[0].imm << 6;
6802 if (inst.operands[1].present)
6803 {
6804 inst.instruction |= CPSI_MMOD;
6805 inst.instruction |= inst.operands[1].imm;
6806 }
6807}
6808
6809static void
6810do_dbg (void)
6811{
6812 inst.instruction |= inst.operands[0].imm;
6813}
6814
6815static void
6816do_it (void)
6817{
6818 /* There is no IT instruction in ARM mode. We
6819 process it but do not generate code for it. */
6820 inst.size = 0;
6821}
6822
6823static void
6824do_ldmstm (void)
6825{
6826 int base_reg = inst.operands[0].reg;
6827 int range = inst.operands[1].imm;
6828
6829 inst.instruction |= base_reg << 16;
6830 inst.instruction |= range;
6831
6832 if (inst.operands[1].writeback)
6833 inst.instruction |= LDM_TYPE_2_OR_3;
6834
6835 if (inst.operands[0].writeback)
6836 {
6837 inst.instruction |= WRITE_BACK;
6838 /* Check for unpredictable uses of writeback. */
6839 if (inst.instruction & LOAD_BIT)
6840 {
6841 /* Not allowed in LDM type 2. */
6842 if ((inst.instruction & LDM_TYPE_2_OR_3)
6843 && ((range & (1 << REG_PC)) == 0))
6844 as_warn (_("writeback of base register is UNPREDICTABLE"));
6845 /* Only allowed if base reg not in list for other types. */
6846 else if (range & (1 << base_reg))
6847 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6848 }
6849 else /* STM. */
6850 {
6851 /* Not allowed for type 2. */
6852 if (inst.instruction & LDM_TYPE_2_OR_3)
6853 as_warn (_("writeback of base register is UNPREDICTABLE"));
6854 /* Only allowed if base reg not in list, or first in list. */
6855 else if ((range & (1 << base_reg))
6856 && (range & ((1 << base_reg) - 1)))
6857 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6858 }
6859 }
6860}
6861
6862/* ARMv5TE load-consecutive (argument parse)
6863 Mode is like LDRH.
6864
6865 LDRccD R, mode
6866 STRccD R, mode. */
6867
6868static void
6869do_ldrd (void)
6870{
6871 constraint (inst.operands[0].reg % 2 != 0,
6872 _("first destination register must be even"));
6873 constraint (inst.operands[1].present
6874 && inst.operands[1].reg != inst.operands[0].reg + 1,
6875 _("can only load two consecutive registers"));
6876 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
6877 constraint (!inst.operands[2].isreg, _("'[' expected"));
6878
6879 if (!inst.operands[1].present)
6880 inst.operands[1].reg = inst.operands[0].reg + 1;
6881
6882 if (inst.instruction & LOAD_BIT)
6883 {
6884 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6885 register and the first register written; we have to diagnose
6886 overlap between the base and the second register written here. */
6887
6888 if (inst.operands[2].reg == inst.operands[1].reg
6889 && (inst.operands[2].writeback || inst.operands[2].postind))
6890 as_warn (_("base register written back, and overlaps "
6891 "second destination register"));
6892
6893 /* For an index-register load, the index register must not overlap the
6894 destination (even if not write-back). */
6895 else if (inst.operands[2].immisreg
6896 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
6897 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
6898 as_warn (_("index register overlaps destination register"));
6899 }
6900
6901 inst.instruction |= inst.operands[0].reg << 12;
6902 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
6903}
6904
6905static void
6906do_ldrex (void)
6907{
6908 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
6909 || inst.operands[1].postind || inst.operands[1].writeback
6910 || inst.operands[1].immisreg || inst.operands[1].shifted
6911 || inst.operands[1].negative
6912 /* This can arise if the programmer has written
6913 strex rN, rM, foo
6914 or if they have mistakenly used a register name as the last
6915 operand, eg:
6916 strex rN, rM, rX
6917 It is very difficult to distinguish between these two cases
6918 because "rX" might actually be a label. ie the register
6919 name has been occluded by a symbol of the same name. So we
6920 just generate a general 'bad addressing mode' type error
6921 message and leave it up to the programmer to discover the
6922 true cause and fix their mistake. */
6923 || (inst.operands[1].reg == REG_PC),
6924 BAD_ADDR_MODE);
6925
6926 constraint (inst.reloc.exp.X_op != O_constant
6927 || inst.reloc.exp.X_add_number != 0,
6928 _("offset must be zero in ARM encoding"));
6929
6930 inst.instruction |= inst.operands[0].reg << 12;
6931 inst.instruction |= inst.operands[1].reg << 16;
6932 inst.reloc.type = BFD_RELOC_UNUSED;
6933}
6934
6935static void
6936do_ldrexd (void)
6937{
6938 constraint (inst.operands[0].reg % 2 != 0,
6939 _("even register required"));
6940 constraint (inst.operands[1].present
6941 && inst.operands[1].reg != inst.operands[0].reg + 1,
6942 _("can only load two consecutive registers"));
6943 /* If op 1 were present and equal to PC, this function wouldn't
6944 have been called in the first place. */
6945 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
6946
6947 inst.instruction |= inst.operands[0].reg << 12;
6948 inst.instruction |= inst.operands[2].reg << 16;
6949}
6950
6951static void
6952do_ldst (void)
6953{
6954 inst.instruction |= inst.operands[0].reg << 12;
6955 if (!inst.operands[1].isreg)
6956 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
6957 return;
6958 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
6959}
6960
6961static void
6962do_ldstt (void)
6963{
6964 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6965 reject [Rn,...]. */
6966 if (inst.operands[1].preind)
6967 {
6968 constraint (inst.reloc.exp.X_op != O_constant ||
6969 inst.reloc.exp.X_add_number != 0,
6970 _("this instruction requires a post-indexed address"));
6971
6972 inst.operands[1].preind = 0;
6973 inst.operands[1].postind = 1;
6974 inst.operands[1].writeback = 1;
6975 }
6976 inst.instruction |= inst.operands[0].reg << 12;
6977 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
6978}
6979
6980/* Halfword and signed-byte load/store operations. */
6981
6982static void
6983do_ldstv4 (void)
6984{
6985 inst.instruction |= inst.operands[0].reg << 12;
6986 if (!inst.operands[1].isreg)
6987 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
6988 return;
6989 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
6990}
6991
6992static void
6993do_ldsttv4 (void)
6994{
6995 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6996 reject [Rn,...]. */
6997 if (inst.operands[1].preind)
6998 {
6999 constraint (inst.reloc.exp.X_op != O_constant ||
7000 inst.reloc.exp.X_add_number != 0,
7001 _("this instruction requires a post-indexed address"));
7002
7003 inst.operands[1].preind = 0;
7004 inst.operands[1].postind = 1;
7005 inst.operands[1].writeback = 1;
7006 }
7007 inst.instruction |= inst.operands[0].reg << 12;
7008 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
7009}
7010
7011/* Co-processor register load/store.
7012 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7013static void
7014do_lstc (void)
7015{
7016 inst.instruction |= inst.operands[0].reg << 8;
7017 inst.instruction |= inst.operands[1].reg << 12;
7018 encode_arm_cp_address (2, TRUE, TRUE, 0);
7019}
7020
7021static void
7022do_mlas (void)
7023{
7024 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7025 if (inst.operands[0].reg == inst.operands[1].reg
7026 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
7027 && !(inst.instruction & 0x00400000))
7028 as_tsktsk (_("Rd and Rm should be different in mla"));
7029
7030 inst.instruction |= inst.operands[0].reg << 16;
7031 inst.instruction |= inst.operands[1].reg;
7032 inst.instruction |= inst.operands[2].reg << 8;
7033 inst.instruction |= inst.operands[3].reg << 12;
7034}
7035
7036static void
7037do_mov (void)
7038{
7039 inst.instruction |= inst.operands[0].reg << 12;
7040 encode_arm_shifter_operand (1);
7041}
7042
7043/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7044static void
7045do_mov16 (void)
7046{
7047 bfd_vma imm;
7048 bfd_boolean top;
7049
7050 top = (inst.instruction & 0x00400000) != 0;
7051 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
7052 _(":lower16: not allowed this instruction"));
7053 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
7054 _(":upper16: not allowed instruction"));
7055 inst.instruction |= inst.operands[0].reg << 12;
7056 if (inst.reloc.type == BFD_RELOC_UNUSED)
7057 {
7058 imm = inst.reloc.exp.X_add_number;
7059 /* The value is in two pieces: 0:11, 16:19. */
7060 inst.instruction |= (imm & 0x00000fff);
7061 inst.instruction |= (imm & 0x0000f000) << 4;
7062 }
7063}
7064
7065static void do_vfp_nsyn_opcode (const char *);
7066
7067static int
7068do_vfp_nsyn_mrs (void)
7069{
7070 if (inst.operands[0].isvec)
7071 {
7072 if (inst.operands[1].reg != 1)
7073 first_error (_("operand 1 must be FPSCR"));
7074 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
7075 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
7076 do_vfp_nsyn_opcode ("fmstat");
7077 }
7078 else if (inst.operands[1].isvec)
7079 do_vfp_nsyn_opcode ("fmrx");
7080 else
7081 return FAIL;
7082
7083 return SUCCESS;
7084}
7085
7086static int
7087do_vfp_nsyn_msr (void)
7088{
7089 if (inst.operands[0].isvec)
7090 do_vfp_nsyn_opcode ("fmxr");
7091 else
7092 return FAIL;
7093
7094 return SUCCESS;
7095}
7096
7097static void
7098do_mrs (void)
7099{
7100 if (do_vfp_nsyn_mrs () == SUCCESS)
7101 return;
7102
7103 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7104 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
7105 != (PSR_c|PSR_f),
7106 _("'CPSR' or 'SPSR' expected"));
7107 inst.instruction |= inst.operands[0].reg << 12;
7108 inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
7109}
7110
7111/* Two possible forms:
7112 "{C|S}PSR_<field>, Rm",
7113 "{C|S}PSR_f, #expression". */
7114
7115static void
7116do_msr (void)
7117{
7118 if (do_vfp_nsyn_msr () == SUCCESS)
7119 return;
7120
7121 inst.instruction |= inst.operands[0].imm;
7122 if (inst.operands[1].isreg)
7123 inst.instruction |= inst.operands[1].reg;
7124 else
7125 {
7126 inst.instruction |= INST_IMMEDIATE;
7127 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7128 inst.reloc.pc_rel = 0;
7129 }
7130}
7131
7132static void
7133do_mul (void)
7134{
7135 if (!inst.operands[2].present)
7136 inst.operands[2].reg = inst.operands[0].reg;
7137 inst.instruction |= inst.operands[0].reg << 16;
7138 inst.instruction |= inst.operands[1].reg;
7139 inst.instruction |= inst.operands[2].reg << 8;
7140
7141 if (inst.operands[0].reg == inst.operands[1].reg
7142 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
7143 as_tsktsk (_("Rd and Rm should be different in mul"));
7144}
7145
7146/* Long Multiply Parser
7147 UMULL RdLo, RdHi, Rm, Rs
7148 SMULL RdLo, RdHi, Rm, Rs
7149 UMLAL RdLo, RdHi, Rm, Rs
7150 SMLAL RdLo, RdHi, Rm, Rs. */
7151
7152static void
7153do_mull (void)
7154{
7155 inst.instruction |= inst.operands[0].reg << 12;
7156 inst.instruction |= inst.operands[1].reg << 16;
7157 inst.instruction |= inst.operands[2].reg;
7158 inst.instruction |= inst.operands[3].reg << 8;
7159
7160 /* rdhi, rdlo and rm must all be different. */
7161 if (inst.operands[0].reg == inst.operands[1].reg
7162 || inst.operands[0].reg == inst.operands[2].reg
7163 || inst.operands[1].reg == inst.operands[2].reg)
7164 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7165}
7166
7167static void
7168do_nop (void)
7169{
7170 if (inst.operands[0].present)
7171 {
7172 /* Architectural NOP hints are CPSR sets with no bits selected. */
7173 inst.instruction &= 0xf0000000;
7174 inst.instruction |= 0x0320f000 + inst.operands[0].imm;
7175 }
7176}
7177
7178/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7179 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7180 Condition defaults to COND_ALWAYS.
7181 Error if Rd, Rn or Rm are R15. */
7182
7183static void
7184do_pkhbt (void)
7185{
7186 inst.instruction |= inst.operands[0].reg << 12;
7187 inst.instruction |= inst.operands[1].reg << 16;
7188 inst.instruction |= inst.operands[2].reg;
7189 if (inst.operands[3].present)
7190 encode_arm_shift (3);
7191}
7192
7193/* ARM V6 PKHTB (Argument Parse). */
7194
7195static void
7196do_pkhtb (void)
7197{
7198 if (!inst.operands[3].present)
7199 {
7200 /* If the shift specifier is omitted, turn the instruction
7201 into pkhbt rd, rm, rn. */
7202 inst.instruction &= 0xfff00010;
7203 inst.instruction |= inst.operands[0].reg << 12;
7204 inst.instruction |= inst.operands[1].reg;
7205 inst.instruction |= inst.operands[2].reg << 16;
7206 }
7207 else
7208 {
7209 inst.instruction |= inst.operands[0].reg << 12;
7210 inst.instruction |= inst.operands[1].reg << 16;
7211 inst.instruction |= inst.operands[2].reg;
7212 encode_arm_shift (3);
7213 }
7214}
7215
7216/* ARMv5TE: Preload-Cache
7217
7218 PLD <addr_mode>
7219
7220 Syntactically, like LDR with B=1, W=0, L=1. */
7221
7222static void
7223do_pld (void)
7224{
7225 constraint (!inst.operands[0].isreg,
7226 _("'[' expected after PLD mnemonic"));
7227 constraint (inst.operands[0].postind,
7228 _("post-indexed expression used in preload instruction"));
7229 constraint (inst.operands[0].writeback,
7230 _("writeback used in preload instruction"));
7231 constraint (!inst.operands[0].preind,
7232 _("unindexed addressing used in preload instruction"));
7233 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
7234}
7235
7236/* ARMv7: PLI <addr_mode> */
7237static void
7238do_pli (void)
7239{
7240 constraint (!inst.operands[0].isreg,
7241 _("'[' expected after PLI mnemonic"));
7242 constraint (inst.operands[0].postind,
7243 _("post-indexed expression used in preload instruction"));
7244 constraint (inst.operands[0].writeback,
7245 _("writeback used in preload instruction"));
7246 constraint (!inst.operands[0].preind,
7247 _("unindexed addressing used in preload instruction"));
7248 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
7249 inst.instruction &= ~PRE_INDEX;
7250}
7251
7252static void
7253do_push_pop (void)
7254{
7255 inst.operands[1] = inst.operands[0];
7256 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
7257 inst.operands[0].isreg = 1;
7258 inst.operands[0].writeback = 1;
7259 inst.operands[0].reg = REG_SP;
7260 do_ldmstm ();
7261}
7262
7263/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7264 word at the specified address and the following word
7265 respectively.
7266 Unconditionally executed.
7267 Error if Rn is R15. */
7268
7269static void
7270do_rfe (void)
7271{
7272 inst.instruction |= inst.operands[0].reg << 16;
7273 if (inst.operands[0].writeback)
7274 inst.instruction |= WRITE_BACK;
7275}
7276
7277/* ARM V6 ssat (argument parse). */
7278
7279static void
7280do_ssat (void)
7281{
7282 inst.instruction |= inst.operands[0].reg << 12;
7283 inst.instruction |= (inst.operands[1].imm - 1) << 16;
7284 inst.instruction |= inst.operands[2].reg;
7285
7286 if (inst.operands[3].present)
7287 encode_arm_shift (3);
7288}
7289
7290/* ARM V6 usat (argument parse). */
7291
7292static void
7293do_usat (void)
7294{
7295 inst.instruction |= inst.operands[0].reg << 12;
7296 inst.instruction |= inst.operands[1].imm << 16;
7297 inst.instruction |= inst.operands[2].reg;
7298
7299 if (inst.operands[3].present)
7300 encode_arm_shift (3);
7301}
7302
7303/* ARM V6 ssat16 (argument parse). */
7304
7305static void
7306do_ssat16 (void)
7307{
7308 inst.instruction |= inst.operands[0].reg << 12;
7309 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
7310 inst.instruction |= inst.operands[2].reg;
7311}
7312
7313static void
7314do_usat16 (void)
7315{
7316 inst.instruction |= inst.operands[0].reg << 12;
7317 inst.instruction |= inst.operands[1].imm << 16;
7318 inst.instruction |= inst.operands[2].reg;
7319}
7320
7321/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7322 preserving the other bits.
7323
7324 setend <endian_specifier>, where <endian_specifier> is either
7325 BE or LE. */
7326
7327static void
7328do_setend (void)
7329{
7330 if (inst.operands[0].imm)
7331 inst.instruction |= 0x200;
7332}
7333
7334static void
7335do_shift (void)
7336{
7337 unsigned int Rm = (inst.operands[1].present
7338 ? inst.operands[1].reg
7339 : inst.operands[0].reg);
7340
7341 inst.instruction |= inst.operands[0].reg << 12;
7342 inst.instruction |= Rm;
7343 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
7344 {
7345 inst.instruction |= inst.operands[2].reg << 8;
7346 inst.instruction |= SHIFT_BY_REG;
7347 }
7348 else
7349 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7350}
7351
7352static void
7353do_smc (void)
7354{
7355 inst.reloc.type = BFD_RELOC_ARM_SMC;
7356 inst.reloc.pc_rel = 0;
7357}
7358
7359static void
7360do_swi (void)
7361{
7362 inst.reloc.type = BFD_RELOC_ARM_SWI;
7363 inst.reloc.pc_rel = 0;
7364}
7365
7366/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7367 SMLAxy{cond} Rd,Rm,Rs,Rn
7368 SMLAWy{cond} Rd,Rm,Rs,Rn
7369 Error if any register is R15. */
7370
7371static void
7372do_smla (void)
7373{
7374 inst.instruction |= inst.operands[0].reg << 16;
7375 inst.instruction |= inst.operands[1].reg;
7376 inst.instruction |= inst.operands[2].reg << 8;
7377 inst.instruction |= inst.operands[3].reg << 12;
7378}
7379
7380/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7381 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7382 Error if any register is R15.
7383 Warning if Rdlo == Rdhi. */
7384
7385static void
7386do_smlal (void)
7387{
7388 inst.instruction |= inst.operands[0].reg << 12;
7389 inst.instruction |= inst.operands[1].reg << 16;
7390 inst.instruction |= inst.operands[2].reg;
7391 inst.instruction |= inst.operands[3].reg << 8;
7392
7393 if (inst.operands[0].reg == inst.operands[1].reg)
7394 as_tsktsk (_("rdhi and rdlo must be different"));
7395}
7396
7397/* ARM V5E (El Segundo) signed-multiply (argument parse)
7398 SMULxy{cond} Rd,Rm,Rs
7399 Error if any register is R15. */
7400
7401static void
7402do_smul (void)
7403{
7404 inst.instruction |= inst.operands[0].reg << 16;
7405 inst.instruction |= inst.operands[1].reg;
7406 inst.instruction |= inst.operands[2].reg << 8;
7407}
7408
7409/* ARM V6 srs (argument parse). The variable fields in the encoding are
7410 the same for both ARM and Thumb-2. */
7411
7412static void
7413do_srs (void)
7414{
7415 int reg;
7416
7417 if (inst.operands[0].present)
7418 {
7419 reg = inst.operands[0].reg;
7420 constraint (reg != 13, _("SRS base register must be r13"));
7421 }
7422 else
7423 reg = 13;
7424
7425 inst.instruction |= reg << 16;
7426 inst.instruction |= inst.operands[1].imm;
7427 if (inst.operands[0].writeback || inst.operands[1].writeback)
7428 inst.instruction |= WRITE_BACK;
7429}
7430
7431/* ARM V6 strex (argument parse). */
7432
7433static void
7434do_strex (void)
7435{
7436 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
7437 || inst.operands[2].postind || inst.operands[2].writeback
7438 || inst.operands[2].immisreg || inst.operands[2].shifted
7439 || inst.operands[2].negative
7440 /* See comment in do_ldrex(). */
7441 || (inst.operands[2].reg == REG_PC),
7442 BAD_ADDR_MODE);
7443
7444 constraint (inst.operands[0].reg == inst.operands[1].reg
7445 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
7446
7447 constraint (inst.reloc.exp.X_op != O_constant
7448 || inst.reloc.exp.X_add_number != 0,
7449 _("offset must be zero in ARM encoding"));
7450
7451 inst.instruction |= inst.operands[0].reg << 12;
7452 inst.instruction |= inst.operands[1].reg;
7453 inst.instruction |= inst.operands[2].reg << 16;
7454 inst.reloc.type = BFD_RELOC_UNUSED;
7455}
7456
7457static void
7458do_strexd (void)
7459{
7460 constraint (inst.operands[1].reg % 2 != 0,
7461 _("even register required"));
7462 constraint (inst.operands[2].present
7463 && inst.operands[2].reg != inst.operands[1].reg + 1,
7464 _("can only store two consecutive registers"));
7465 /* If op 2 were present and equal to PC, this function wouldn't
7466 have been called in the first place. */
7467 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
7468
7469 constraint (inst.operands[0].reg == inst.operands[1].reg
7470 || inst.operands[0].reg == inst.operands[1].reg + 1
7471 || inst.operands[0].reg == inst.operands[3].reg,
7472 BAD_OVERLAP);
7473
7474 inst.instruction |= inst.operands[0].reg << 12;
7475 inst.instruction |= inst.operands[1].reg;
7476 inst.instruction |= inst.operands[3].reg << 16;
7477}
7478
7479/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7480 extends it to 32-bits, and adds the result to a value in another
7481 register. You can specify a rotation by 0, 8, 16, or 24 bits
7482 before extracting the 16-bit value.
7483 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7484 Condition defaults to COND_ALWAYS.
7485 Error if any register uses R15. */
7486
7487static void
7488do_sxtah (void)
7489{
7490 inst.instruction |= inst.operands[0].reg << 12;
7491 inst.instruction |= inst.operands[1].reg << 16;
7492 inst.instruction |= inst.operands[2].reg;
7493 inst.instruction |= inst.operands[3].imm << 10;
7494}
7495
7496/* ARM V6 SXTH.
7497
7498 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7499 Condition defaults to COND_ALWAYS.
7500 Error if any register uses R15. */
7501
7502static void
7503do_sxth (void)
7504{
7505 inst.instruction |= inst.operands[0].reg << 12;
7506 inst.instruction |= inst.operands[1].reg;
7507 inst.instruction |= inst.operands[2].imm << 10;
7508}
7509
7510/* VFP instructions. In a logical order: SP variant first, monad
7511 before dyad, arithmetic then move then load/store. */
7512
7513static void
7514do_vfp_sp_monadic (void)
7515{
7516 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7517 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
7518}
7519
7520static void
7521do_vfp_sp_dyadic (void)
7522{
7523 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7524 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
7525 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
7526}
7527
7528static void
7529do_vfp_sp_compare_z (void)
7530{
7531 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7532}
7533
7534static void
7535do_vfp_dp_sp_cvt (void)
7536{
7537 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7538 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
7539}
7540
7541static void
7542do_vfp_sp_dp_cvt (void)
7543{
7544 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7545 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
7546}
7547
7548static void
7549do_vfp_reg_from_sp (void)
7550{
7551 inst.instruction |= inst.operands[0].reg << 12;
7552 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
7553}
7554
7555static void
7556do_vfp_reg2_from_sp2 (void)
7557{
7558 constraint (inst.operands[2].imm != 2,
7559 _("only two consecutive VFP SP registers allowed here"));
7560 inst.instruction |= inst.operands[0].reg << 12;
7561 inst.instruction |= inst.operands[1].reg << 16;
7562 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
7563}
7564
7565static void
7566do_vfp_sp_from_reg (void)
7567{
7568 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
7569 inst.instruction |= inst.operands[1].reg << 12;
7570}
7571
7572static void
7573do_vfp_sp2_from_reg2 (void)
7574{
7575 constraint (inst.operands[0].imm != 2,
7576 _("only two consecutive VFP SP registers allowed here"));
7577 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
7578 inst.instruction |= inst.operands[1].reg << 12;
7579 inst.instruction |= inst.operands[2].reg << 16;
7580}
7581
7582static void
7583do_vfp_sp_ldst (void)
7584{
7585 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7586 encode_arm_cp_address (1, FALSE, TRUE, 0);
7587}
7588
7589static void
7590do_vfp_dp_ldst (void)
7591{
7592 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7593 encode_arm_cp_address (1, FALSE, TRUE, 0);
7594}
7595
7596
7597static void
7598vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
7599{
7600 if (inst.operands[0].writeback)
7601 inst.instruction |= WRITE_BACK;
7602 else
7603 constraint (ldstm_type != VFP_LDSTMIA,
7604 _("this addressing mode requires base-register writeback"));
7605 inst.instruction |= inst.operands[0].reg << 16;
7606 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
7607 inst.instruction |= inst.operands[1].imm;
7608}
7609
7610static void
7611vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
7612{
7613 int count;
7614
7615 if (inst.operands[0].writeback)
7616 inst.instruction |= WRITE_BACK;
7617 else
7618 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
7619 _("this addressing mode requires base-register writeback"));
7620
7621 inst.instruction |= inst.operands[0].reg << 16;
7622 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7623
7624 count = inst.operands[1].imm << 1;
7625 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
7626 count += 1;
7627
7628 inst.instruction |= count;
7629}
7630
7631static void
7632do_vfp_sp_ldstmia (void)
7633{
7634 vfp_sp_ldstm (VFP_LDSTMIA);
7635}
7636
7637static void
7638do_vfp_sp_ldstmdb (void)
7639{
7640 vfp_sp_ldstm (VFP_LDSTMDB);
7641}
7642
7643static void
7644do_vfp_dp_ldstmia (void)
7645{
7646 vfp_dp_ldstm (VFP_LDSTMIA);
7647}
7648
7649static void
7650do_vfp_dp_ldstmdb (void)
7651{
7652 vfp_dp_ldstm (VFP_LDSTMDB);
7653}
7654
7655static void
7656do_vfp_xp_ldstmia (void)
7657{
7658 vfp_dp_ldstm (VFP_LDSTMIAX);
7659}
7660
7661static void
7662do_vfp_xp_ldstmdb (void)
7663{
7664 vfp_dp_ldstm (VFP_LDSTMDBX);
7665}
7666
7667static void
7668do_vfp_dp_rd_rm (void)
7669{
7670 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7671 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
7672}
7673
7674static void
7675do_vfp_dp_rn_rd (void)
7676{
7677 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
7678 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7679}
7680
7681static void
7682do_vfp_dp_rd_rn (void)
7683{
7684 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7685 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
7686}
7687
7688static void
7689do_vfp_dp_rd_rn_rm (void)
7690{
7691 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7692 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
7693 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
7694}
7695
7696static void
7697do_vfp_dp_rd (void)
7698{
7699 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7700}
7701
7702static void
7703do_vfp_dp_rm_rd_rn (void)
7704{
7705 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
7706 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7707 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
7708}
7709
7710/* VFPv3 instructions. */
7711static void
7712do_vfp_sp_const (void)
7713{
7714 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7715 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
7716 inst.instruction |= (inst.operands[1].imm & 0x0f);
7717}
7718
7719static void
7720do_vfp_dp_const (void)
7721{
7722 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7723 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
7724 inst.instruction |= (inst.operands[1].imm & 0x0f);
7725}
7726
7727static void
7728vfp_conv (int srcsize)
7729{
7730 unsigned immbits = srcsize - inst.operands[1].imm;
7731 inst.instruction |= (immbits & 1) << 5;
7732 inst.instruction |= (immbits >> 1);
7733}
7734
7735static void
7736do_vfp_sp_conv_16 (void)
7737{
7738 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7739 vfp_conv (16);
7740}
7741
7742static void
7743do_vfp_dp_conv_16 (void)
7744{
7745 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7746 vfp_conv (16);
7747}
7748
7749static void
7750do_vfp_sp_conv_32 (void)
7751{
7752 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7753 vfp_conv (32);
7754}
7755
7756static void
7757do_vfp_dp_conv_32 (void)
7758{
7759 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7760 vfp_conv (32);
7761}
7762
7763
7764/* FPA instructions. Also in a logical order. */
7765
7766static void
7767do_fpa_cmp (void)
7768{
7769 inst.instruction |= inst.operands[0].reg << 16;
7770 inst.instruction |= inst.operands[1].reg;
7771}
7772
7773static void
7774do_fpa_ldmstm (void)
7775{
7776 inst.instruction |= inst.operands[0].reg << 12;
7777 switch (inst.operands[1].imm)
7778 {
7779 case 1: inst.instruction |= CP_T_X; break;
7780 case 2: inst.instruction |= CP_T_Y; break;
7781 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
7782 case 4: break;
7783 default: abort ();
7784 }
7785
7786 if (inst.instruction & (PRE_INDEX | INDEX_UP))
7787 {
7788 /* The instruction specified "ea" or "fd", so we can only accept
7789 [Rn]{!}. The instruction does not really support stacking or
7790 unstacking, so we have to emulate these by setting appropriate
7791 bits and offsets. */
7792 constraint (inst.reloc.exp.X_op != O_constant
7793 || inst.reloc.exp.X_add_number != 0,
7794 _("this instruction does not support indexing"));
7795
7796 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
7797 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
7798
7799 if (!(inst.instruction & INDEX_UP))
7800 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
7801
7802 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
7803 {
7804 inst.operands[2].preind = 0;
7805 inst.operands[2].postind = 1;
7806 }
7807 }
7808
7809 encode_arm_cp_address (2, TRUE, TRUE, 0);
7810}
7811
7812
7813/* iWMMXt instructions: strictly in alphabetical order. */
7814
7815static void
7816do_iwmmxt_tandorc (void)
7817{
7818 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
7819}
7820
7821static void
7822do_iwmmxt_textrc (void)
7823{
7824 inst.instruction |= inst.operands[0].reg << 12;
7825 inst.instruction |= inst.operands[1].imm;
7826}
7827
7828static void
7829do_iwmmxt_textrm (void)
7830{
7831 inst.instruction |= inst.operands[0].reg << 12;
7832 inst.instruction |= inst.operands[1].reg << 16;
7833 inst.instruction |= inst.operands[2].imm;
7834}
7835
7836static void
7837do_iwmmxt_tinsr (void)
7838{
7839 inst.instruction |= inst.operands[0].reg << 16;
7840 inst.instruction |= inst.operands[1].reg << 12;
7841 inst.instruction |= inst.operands[2].imm;
7842}
7843
7844static void
7845do_iwmmxt_tmia (void)
7846{
7847 inst.instruction |= inst.operands[0].reg << 5;
7848 inst.instruction |= inst.operands[1].reg;
7849 inst.instruction |= inst.operands[2].reg << 12;
7850}
7851
7852static void
7853do_iwmmxt_waligni (void)
7854{
7855 inst.instruction |= inst.operands[0].reg << 12;
7856 inst.instruction |= inst.operands[1].reg << 16;
7857 inst.instruction |= inst.operands[2].reg;
7858 inst.instruction |= inst.operands[3].imm << 20;
7859}
7860
7861static void
7862do_iwmmxt_wmerge (void)
7863{
7864 inst.instruction |= inst.operands[0].reg << 12;
7865 inst.instruction |= inst.operands[1].reg << 16;
7866 inst.instruction |= inst.operands[2].reg;
7867 inst.instruction |= inst.operands[3].imm << 21;
7868}
7869
7870static void
7871do_iwmmxt_wmov (void)
7872{
7873 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7874 inst.instruction |= inst.operands[0].reg << 12;
7875 inst.instruction |= inst.operands[1].reg << 16;
7876 inst.instruction |= inst.operands[1].reg;
7877}
7878
7879static void
7880do_iwmmxt_wldstbh (void)
7881{
7882 int reloc;
7883 inst.instruction |= inst.operands[0].reg << 12;
7884 if (thumb_mode)
7885 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
7886 else
7887 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
7888 encode_arm_cp_address (1, TRUE, FALSE, reloc);
7889}
7890
7891static void
7892do_iwmmxt_wldstw (void)
7893{
7894 /* RIWR_RIWC clears .isreg for a control register. */
7895 if (!inst.operands[0].isreg)
7896 {
7897 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7898 inst.instruction |= 0xf0000000;
7899 }
7900
7901 inst.instruction |= inst.operands[0].reg << 12;
7902 encode_arm_cp_address (1, TRUE, TRUE, 0);
7903}
7904
7905static void
7906do_iwmmxt_wldstd (void)
7907{
7908 inst.instruction |= inst.operands[0].reg << 12;
7909 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
7910 && inst.operands[1].immisreg)
7911 {
7912 inst.instruction &= ~0x1a000ff;
7913 inst.instruction |= (0xf << 28);
7914 if (inst.operands[1].preind)
7915 inst.instruction |= PRE_INDEX;
7916 if (!inst.operands[1].negative)
7917 inst.instruction |= INDEX_UP;
7918 if (inst.operands[1].writeback)
7919 inst.instruction |= WRITE_BACK;
7920 inst.instruction |= inst.operands[1].reg << 16;
7921 inst.instruction |= inst.reloc.exp.X_add_number << 4;
7922 inst.instruction |= inst.operands[1].imm;
7923 }
7924 else
7925 encode_arm_cp_address (1, TRUE, FALSE, 0);
7926}
7927
7928static void
7929do_iwmmxt_wshufh (void)
7930{
7931 inst.instruction |= inst.operands[0].reg << 12;
7932 inst.instruction |= inst.operands[1].reg << 16;
7933 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
7934 inst.instruction |= (inst.operands[2].imm & 0x0f);
7935}
7936
7937static void
7938do_iwmmxt_wzero (void)
7939{
7940 /* WZERO reg is an alias for WANDN reg, reg, reg. */
7941 inst.instruction |= inst.operands[0].reg;
7942 inst.instruction |= inst.operands[0].reg << 12;
7943 inst.instruction |= inst.operands[0].reg << 16;
7944}
7945
7946static void
7947do_iwmmxt_wrwrwr_or_imm5 (void)
7948{
7949 if (inst.operands[2].isreg)
7950 do_rd_rn_rm ();
7951 else {
7952 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
7953 _("immediate operand requires iWMMXt2"));
7954 do_rd_rn ();
7955 if (inst.operands[2].imm == 0)
7956 {
7957 switch ((inst.instruction >> 20) & 0xf)
7958 {
7959 case 4:
7960 case 5:
7961 case 6:
7962 case 7:
7963 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
7964 inst.operands[2].imm = 16;
7965 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
7966 break;
7967 case 8:
7968 case 9:
7969 case 10:
7970 case 11:
7971 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
7972 inst.operands[2].imm = 32;
7973 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
7974 break;
7975 case 12:
7976 case 13:
7977 case 14:
7978 case 15:
7979 {
7980 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
7981 unsigned long wrn;
7982 wrn = (inst.instruction >> 16) & 0xf;
7983 inst.instruction &= 0xff0fff0f;
7984 inst.instruction |= wrn;
7985 /* Bail out here; the instruction is now assembled. */
7986 return;
7987 }
7988 }
7989 }
7990 /* Map 32 -> 0, etc. */
7991 inst.operands[2].imm &= 0x1f;
7992 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
7993 }
7994}
7995
7996/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
7997 operations first, then control, shift, and load/store. */
7998
7999/* Insns like "foo X,Y,Z". */
8000
8001static void
8002do_mav_triple (void)
8003{
8004 inst.instruction |= inst.operands[0].reg << 16;
8005 inst.instruction |= inst.operands[1].reg;
8006 inst.instruction |= inst.operands[2].reg << 12;
8007}
8008
8009/* Insns like "foo W,X,Y,Z".
8010 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8011
8012static void
8013do_mav_quad (void)
8014{
8015 inst.instruction |= inst.operands[0].reg << 5;
8016 inst.instruction |= inst.operands[1].reg << 12;
8017 inst.instruction |= inst.operands[2].reg << 16;
8018 inst.instruction |= inst.operands[3].reg;
8019}
8020
8021/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8022static void
8023do_mav_dspsc (void)
8024{
8025 inst.instruction |= inst.operands[1].reg << 12;
8026}
8027
8028/* Maverick shift immediate instructions.
8029 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8030 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8031
8032static void
8033do_mav_shift (void)
8034{
8035 int imm = inst.operands[2].imm;
8036
8037 inst.instruction |= inst.operands[0].reg << 12;
8038 inst.instruction |= inst.operands[1].reg << 16;
8039
8040 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8041 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8042 Bit 4 should be 0. */
8043 imm = (imm & 0xf) | ((imm & 0x70) << 1);
8044
8045 inst.instruction |= imm;
8046}
8047
8048/* XScale instructions. Also sorted arithmetic before move. */
8049
8050/* Xscale multiply-accumulate (argument parse)
8051 MIAcc acc0,Rm,Rs
8052 MIAPHcc acc0,Rm,Rs
8053 MIAxycc acc0,Rm,Rs. */
8054
8055static void
8056do_xsc_mia (void)
8057{
8058 inst.instruction |= inst.operands[1].reg;
8059 inst.instruction |= inst.operands[2].reg << 12;
8060}
8061
8062/* Xscale move-accumulator-register (argument parse)
8063
8064 MARcc acc0,RdLo,RdHi. */
8065
8066static void
8067do_xsc_mar (void)
8068{
8069 inst.instruction |= inst.operands[1].reg << 12;
8070 inst.instruction |= inst.operands[2].reg << 16;
8071}
8072
8073/* Xscale move-register-accumulator (argument parse)
8074
8075 MRAcc RdLo,RdHi,acc0. */
8076
8077static void
8078do_xsc_mra (void)
8079{
8080 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
8081 inst.instruction |= inst.operands[0].reg << 12;
8082 inst.instruction |= inst.operands[1].reg << 16;
8083}
8084
8085/* Encoding functions relevant only to Thumb. */
8086
8087/* inst.operands[i] is a shifted-register operand; encode
8088 it into inst.instruction in the format used by Thumb32. */
8089
8090static void
8091encode_thumb32_shifted_operand (int i)
8092{
8093 unsigned int value = inst.reloc.exp.X_add_number;
8094 unsigned int shift = inst.operands[i].shift_kind;
8095
8096 constraint (inst.operands[i].immisreg,
8097 _("shift by register not allowed in thumb mode"));
8098 inst.instruction |= inst.operands[i].reg;
8099 if (shift == SHIFT_RRX)
8100 inst.instruction |= SHIFT_ROR << 4;
8101 else
8102 {
8103 constraint (inst.reloc.exp.X_op != O_constant,
8104 _("expression too complex"));
8105
8106 constraint (value > 32
8107 || (value == 32 && (shift == SHIFT_LSL
8108 || shift == SHIFT_ROR)),
8109 _("shift expression is too large"));
8110
8111 if (value == 0)
8112 shift = SHIFT_LSL;
8113 else if (value == 32)
8114 value = 0;
8115
8116 inst.instruction |= shift << 4;
8117 inst.instruction |= (value & 0x1c) << 10;
8118 inst.instruction |= (value & 0x03) << 6;
8119 }
8120}
8121
8122
8123/* inst.operands[i] was set up by parse_address. Encode it into a
8124 Thumb32 format load or store instruction. Reject forms that cannot
8125 be used with such instructions. If is_t is true, reject forms that
8126 cannot be used with a T instruction; if is_d is true, reject forms
8127 that cannot be used with a D instruction. */
8128
8129static void
8130encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
8131{
8132 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
8133
8134 constraint (!inst.operands[i].isreg,
8135 _("Instruction does not support =N addresses"));
8136
8137 inst.instruction |= inst.operands[i].reg << 16;
8138 if (inst.operands[i].immisreg)
8139 {
8140 constraint (is_pc, _("cannot use register index with PC-relative addressing"));
8141 constraint (is_t || is_d, _("cannot use register index with this instruction"));
8142 constraint (inst.operands[i].negative,
8143 _("Thumb does not support negative register indexing"));
8144 constraint (inst.operands[i].postind,
8145 _("Thumb does not support register post-indexing"));
8146 constraint (inst.operands[i].writeback,
8147 _("Thumb does not support register indexing with writeback"));
8148 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
8149 _("Thumb supports only LSL in shifted register indexing"));
8150
8151 inst.instruction |= inst.operands[i].imm;
8152 if (inst.operands[i].shifted)
8153 {
8154 constraint (inst.reloc.exp.X_op != O_constant,
8155 _("expression too complex"));
8156 constraint (inst.reloc.exp.X_add_number < 0
8157 || inst.reloc.exp.X_add_number > 3,
8158 _("shift out of range"));
8159 inst.instruction |= inst.reloc.exp.X_add_number << 4;
8160 }
8161 inst.reloc.type = BFD_RELOC_UNUSED;
8162 }
8163 else if (inst.operands[i].preind)
8164 {
8165 constraint (is_pc && inst.operands[i].writeback,
8166 _("cannot use writeback with PC-relative addressing"));
8167 constraint (is_t && inst.operands[i].writeback,
8168 _("cannot use writeback with this instruction"));
8169
8170 if (is_d)
8171 {
8172 inst.instruction |= 0x01000000;
8173 if (inst.operands[i].writeback)
8174 inst.instruction |= 0x00200000;
8175 }
8176 else
8177 {
8178 inst.instruction |= 0x00000c00;
8179 if (inst.operands[i].writeback)
8180 inst.instruction |= 0x00000100;
8181 }
8182 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
8183 }
8184 else if (inst.operands[i].postind)
8185 {
8186 assert (inst.operands[i].writeback);
8187 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
8188 constraint (is_t, _("cannot use post-indexing with this instruction"));
8189
8190 if (is_d)
8191 inst.instruction |= 0x00200000;
8192 else
8193 inst.instruction |= 0x00000900;
8194 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
8195 }
8196 else /* unindexed - only for coprocessor */
8197 inst.error = _("instruction does not accept unindexed addressing");
8198}
8199
8200/* Table of Thumb instructions which exist in both 16- and 32-bit
8201 encodings (the latter only in post-V6T2 cores). The index is the
8202 value used in the insns table below. When there is more than one
8203 possible 16-bit encoding for the instruction, this table always
8204 holds variant (1).
8205 Also contains several pseudo-instructions used during relaxation. */
8206#define T16_32_TAB \
8207 X(adc, 4140, eb400000), \
8208 X(adcs, 4140, eb500000), \
8209 X(add, 1c00, eb000000), \
8210 X(adds, 1c00, eb100000), \
8211 X(addi, 0000, f1000000), \
8212 X(addis, 0000, f1100000), \
8213 X(add_pc,000f, f20f0000), \
8214 X(add_sp,000d, f10d0000), \
8215 X(adr, 000f, f20f0000), \
8216 X(and, 4000, ea000000), \
8217 X(ands, 4000, ea100000), \
8218 X(asr, 1000, fa40f000), \
8219 X(asrs, 1000, fa50f000), \
8220 X(b, e000, f000b000), \
8221 X(bcond, d000, f0008000), \
8222 X(bic, 4380, ea200000), \
8223 X(bics, 4380, ea300000), \
8224 X(cmn, 42c0, eb100f00), \
8225 X(cmp, 2800, ebb00f00), \
8226 X(cpsie, b660, f3af8400), \
8227 X(cpsid, b670, f3af8600), \
8228 X(cpy, 4600, ea4f0000), \
8229 X(dec_sp,80dd, f1ad0d00), \
8230 X(eor, 4040, ea800000), \
8231 X(eors, 4040, ea900000), \
8232 X(inc_sp,00dd, f10d0d00), \
8233 X(ldmia, c800, e8900000), \
8234 X(ldr, 6800, f8500000), \
8235 X(ldrb, 7800, f8100000), \
8236 X(ldrh, 8800, f8300000), \
8237 X(ldrsb, 5600, f9100000), \
8238 X(ldrsh, 5e00, f9300000), \
8239 X(ldr_pc,4800, f85f0000), \
8240 X(ldr_pc2,4800, f85f0000), \
8241 X(ldr_sp,9800, f85d0000), \
8242 X(lsl, 0000, fa00f000), \
8243 X(lsls, 0000, fa10f000), \
8244 X(lsr, 0800, fa20f000), \
8245 X(lsrs, 0800, fa30f000), \
8246 X(mov, 2000, ea4f0000), \
8247 X(movs, 2000, ea5f0000), \
8248 X(mul, 4340, fb00f000), \
8249 X(muls, 4340, ffffffff), /* no 32b muls */ \
8250 X(mvn, 43c0, ea6f0000), \
8251 X(mvns, 43c0, ea7f0000), \
8252 X(neg, 4240, f1c00000), /* rsb #0 */ \
8253 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8254 X(orr, 4300, ea400000), \
8255 X(orrs, 4300, ea500000), \
8256 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8257 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8258 X(rev, ba00, fa90f080), \
8259 X(rev16, ba40, fa90f090), \
8260 X(revsh, bac0, fa90f0b0), \
8261 X(ror, 41c0, fa60f000), \
8262 X(rors, 41c0, fa70f000), \
8263 X(sbc, 4180, eb600000), \
8264 X(sbcs, 4180, eb700000), \
8265 X(stmia, c000, e8800000), \
8266 X(str, 6000, f8400000), \
8267 X(strb, 7000, f8000000), \
8268 X(strh, 8000, f8200000), \
8269 X(str_sp,9000, f84d0000), \
8270 X(sub, 1e00, eba00000), \
8271 X(subs, 1e00, ebb00000), \
8272 X(subi, 8000, f1a00000), \
8273 X(subis, 8000, f1b00000), \
8274 X(sxtb, b240, fa4ff080), \
8275 X(sxth, b200, fa0ff080), \
8276 X(tst, 4200, ea100f00), \
8277 X(uxtb, b2c0, fa5ff080), \
8278 X(uxth, b280, fa1ff080), \
8279 X(nop, bf00, f3af8000), \
8280 X(yield, bf10, f3af8001), \
8281 X(wfe, bf20, f3af8002), \
8282 X(wfi, bf30, f3af8003), \
8283 X(sev, bf40, f3af9004), /* typo, 8004? */
8284
8285/* To catch errors in encoding functions, the codes are all offset by
8286 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8287 as 16-bit instructions. */
8288#define X(a,b,c) T_MNEM_##a
8289enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
8290#undef X
8291
8292#define X(a,b,c) 0x##b
8293static const unsigned short thumb_op16[] = { T16_32_TAB };
8294#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8295#undef X
8296
8297#define X(a,b,c) 0x##c
8298static const unsigned int thumb_op32[] = { T16_32_TAB };
8299#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8300#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8301#undef X
8302#undef T16_32_TAB
8303
8304/* Thumb instruction encoders, in alphabetical order. */
8305
8306/* ADDW or SUBW. */
8307static void
8308do_t_add_sub_w (void)
8309{
8310 int Rd, Rn;
8311
8312 Rd = inst.operands[0].reg;
8313 Rn = inst.operands[1].reg;
8314
8315 constraint (Rd == 15, _("PC not allowed as destination"));
8316 inst.instruction |= (Rn << 16) | (Rd << 8);
8317 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
8318}
8319
8320/* Parse an add or subtract instruction. We get here with inst.instruction
8321 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8322
8323static void
8324do_t_add_sub (void)
8325{
8326 int Rd, Rs, Rn;
8327
8328 Rd = inst.operands[0].reg;
8329 Rs = (inst.operands[1].present
8330 ? inst.operands[1].reg /* Rd, Rs, foo */
8331 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
8332
8333 if (unified_syntax)
8334 {
8335 bfd_boolean flags;
8336 bfd_boolean narrow;
8337 int opcode;
8338
8339 flags = (inst.instruction == T_MNEM_adds
8340 || inst.instruction == T_MNEM_subs);
8341 if (flags)
8342 narrow = (current_it_mask == 0);
8343 else
8344 narrow = (current_it_mask != 0);
8345 if (!inst.operands[2].isreg)
8346 {
8347 int add;
8348
8349 add = (inst.instruction == T_MNEM_add
8350 || inst.instruction == T_MNEM_adds);
8351 opcode = 0;
8352 if (inst.size_req != 4)
8353 {
8354 /* Attempt to use a narrow opcode, with relaxation if
8355 appropriate. */
8356 if (Rd == REG_SP && Rs == REG_SP && !flags)
8357 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
8358 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
8359 opcode = T_MNEM_add_sp;
8360 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
8361 opcode = T_MNEM_add_pc;
8362 else if (Rd <= 7 && Rs <= 7 && narrow)
8363 {
8364 if (flags)
8365 opcode = add ? T_MNEM_addis : T_MNEM_subis;
8366 else
8367 opcode = add ? T_MNEM_addi : T_MNEM_subi;
8368 }
8369 if (opcode)
8370 {
8371 inst.instruction = THUMB_OP16(opcode);
8372 inst.instruction |= (Rd << 4) | Rs;
8373 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
8374 if (inst.size_req != 2)
8375 inst.relax = opcode;
8376 }
8377 else
8378 constraint (inst.size_req == 2, BAD_HIREG);
8379 }
8380 if (inst.size_req == 4
8381 || (inst.size_req != 2 && !opcode))
8382 {
8383 if (Rd == REG_PC)
8384 {
8385 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
8386 _("only SUBS PC, LR, #const allowed"));
8387 constraint (inst.reloc.exp.X_op != O_constant,
8388 _("expression too complex"));
8389 constraint (inst.reloc.exp.X_add_number < 0
8390 || inst.reloc.exp.X_add_number > 0xff,
8391 _("immediate value out of range"));
8392 inst.instruction = T2_SUBS_PC_LR
8393 | inst.reloc.exp.X_add_number;
8394 inst.reloc.type = BFD_RELOC_UNUSED;
8395 return;
8396 }
8397 else if (Rs == REG_PC)
8398 {
8399 /* Always use addw/subw. */
8400 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
8401 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
8402 }
8403 else
8404 {
8405 inst.instruction = THUMB_OP32 (inst.instruction);
8406 inst.instruction = (inst.instruction & 0xe1ffffff)
8407 | 0x10000000;
8408 if (flags)
8409 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
8410 else
8411 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
8412 }
8413 inst.instruction |= Rd << 8;
8414 inst.instruction |= Rs << 16;
8415 }
8416 }
8417 else
8418 {
8419 Rn = inst.operands[2].reg;
8420 /* See if we can do this with a 16-bit instruction. */
8421 if (!inst.operands[2].shifted && inst.size_req != 4)
8422 {
8423 if (Rd > 7 || Rs > 7 || Rn > 7)
8424 narrow = FALSE;
8425
8426 if (narrow)
8427 {
8428 inst.instruction = ((inst.instruction == T_MNEM_adds
8429 || inst.instruction == T_MNEM_add)
8430 ? T_OPCODE_ADD_R3
8431 : T_OPCODE_SUB_R3);
8432 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
8433 return;
8434 }
8435
8436 if (inst.instruction == T_MNEM_add)
8437 {
8438 if (Rd == Rs)
8439 {
8440 inst.instruction = T_OPCODE_ADD_HI;
8441 inst.instruction |= (Rd & 8) << 4;
8442 inst.instruction |= (Rd & 7);
8443 inst.instruction |= Rn << 3;
8444 return;
8445 }
8446 /* ... because addition is commutative! */
8447 else if (Rd == Rn)
8448 {
8449 inst.instruction = T_OPCODE_ADD_HI;
8450 inst.instruction |= (Rd & 8) << 4;
8451 inst.instruction |= (Rd & 7);
8452 inst.instruction |= Rs << 3;
8453 return;
8454 }
8455 }
8456 }
8457 /* If we get here, it can't be done in 16 bits. */
8458 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
8459 _("shift must be constant"));
8460 inst.instruction = THUMB_OP32 (inst.instruction);
8461 inst.instruction |= Rd << 8;
8462 inst.instruction |= Rs << 16;
8463 encode_thumb32_shifted_operand (2);
8464 }
8465 }
8466 else
8467 {
8468 constraint (inst.instruction == T_MNEM_adds
8469 || inst.instruction == T_MNEM_subs,
8470 BAD_THUMB32);
8471
8472 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
8473 {
8474 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
8475 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
8476 BAD_HIREG);
8477
8478 inst.instruction = (inst.instruction == T_MNEM_add
8479 ? 0x0000 : 0x8000);
8480 inst.instruction |= (Rd << 4) | Rs;
8481 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
8482 return;
8483 }
8484
8485 Rn = inst.operands[2].reg;
8486 constraint (inst.operands[2].shifted, _("unshifted register required"));
8487
8488 /* We now have Rd, Rs, and Rn set to registers. */
8489 if (Rd > 7 || Rs > 7 || Rn > 7)
8490 {
8491 /* Can't do this for SUB. */
8492 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
8493 inst.instruction = T_OPCODE_ADD_HI;
8494 inst.instruction |= (Rd & 8) << 4;
8495 inst.instruction |= (Rd & 7);
8496 if (Rs == Rd)
8497 inst.instruction |= Rn << 3;
8498 else if (Rn == Rd)
8499 inst.instruction |= Rs << 3;
8500 else
8501 constraint (1, _("dest must overlap one source register"));
8502 }
8503 else
8504 {
8505 inst.instruction = (inst.instruction == T_MNEM_add
8506 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
8507 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
8508 }
8509 }
8510}
8511
8512static void
8513do_t_adr (void)
8514{
8515 if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7)
8516 {
8517 /* Defer to section relaxation. */
8518 inst.relax = inst.instruction;
8519 inst.instruction = THUMB_OP16 (inst.instruction);
8520 inst.instruction |= inst.operands[0].reg << 4;
8521 }
8522 else if (unified_syntax && inst.size_req != 2)
8523 {
8524 /* Generate a 32-bit opcode. */
8525 inst.instruction = THUMB_OP32 (inst.instruction);
8526 inst.instruction |= inst.operands[0].reg << 8;
8527 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
8528 inst.reloc.pc_rel = 1;
8529 }
8530 else
8531 {
8532 /* Generate a 16-bit opcode. */
8533 inst.instruction = THUMB_OP16 (inst.instruction);
8534 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
8535 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
8536 inst.reloc.pc_rel = 1;
8537
8538 inst.instruction |= inst.operands[0].reg << 4;
8539 }
8540}
8541
8542/* Arithmetic instructions for which there is just one 16-bit
8543 instruction encoding, and it allows only two low registers.
8544 For maximal compatibility with ARM syntax, we allow three register
8545 operands even when Thumb-32 instructions are not available, as long
8546 as the first two are identical. For instance, both "sbc r0,r1" and
8547 "sbc r0,r0,r1" are allowed. */
8548static void
8549do_t_arit3 (void)
8550{
8551 int Rd, Rs, Rn;
8552
8553 Rd = inst.operands[0].reg;
8554 Rs = (inst.operands[1].present
8555 ? inst.operands[1].reg /* Rd, Rs, foo */
8556 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
8557 Rn = inst.operands[2].reg;
8558
8559 if (unified_syntax)
8560 {
8561 if (!inst.operands[2].isreg)
8562 {
8563 /* For an immediate, we always generate a 32-bit opcode;
8564 section relaxation will shrink it later if possible. */
8565 inst.instruction = THUMB_OP32 (inst.instruction);
8566 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
8567 inst.instruction |= Rd << 8;
8568 inst.instruction |= Rs << 16;
8569 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
8570 }
8571 else
8572 {
8573 bfd_boolean narrow;
8574
8575 /* See if we can do this with a 16-bit instruction. */
8576 if (THUMB_SETS_FLAGS (inst.instruction))
8577 narrow = current_it_mask == 0;
8578 else
8579 narrow = current_it_mask != 0;
8580
8581 if (Rd > 7 || Rn > 7 || Rs > 7)
8582 narrow = FALSE;
8583 if (inst.operands[2].shifted)
8584 narrow = FALSE;
8585 if (inst.size_req == 4)
8586 narrow = FALSE;
8587
8588 if (narrow
8589 && Rd == Rs)
8590 {
8591 inst.instruction = THUMB_OP16 (inst.instruction);
8592 inst.instruction |= Rd;
8593 inst.instruction |= Rn << 3;
8594 return;
8595 }
8596
8597 /* If we get here, it can't be done in 16 bits. */
8598 constraint (inst.operands[2].shifted
8599 && inst.operands[2].immisreg,
8600 _("shift must be constant"));
8601 inst.instruction = THUMB_OP32 (inst.instruction);
8602 inst.instruction |= Rd << 8;
8603 inst.instruction |= Rs << 16;
8604 encode_thumb32_shifted_operand (2);
8605 }
8606 }
8607 else
8608 {
8609 /* On its face this is a lie - the instruction does set the
8610 flags. However, the only supported mnemonic in this mode
8611 says it doesn't. */
8612 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
8613
8614 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
8615 _("unshifted register required"));
8616 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
8617 constraint (Rd != Rs,
8618 _("dest and source1 must be the same register"));
8619
8620 inst.instruction = THUMB_OP16 (inst.instruction);
8621 inst.instruction |= Rd;
8622 inst.instruction |= Rn << 3;
8623 }
8624}
8625
8626/* Similarly, but for instructions where the arithmetic operation is
8627 commutative, so we can allow either of them to be different from
8628 the destination operand in a 16-bit instruction. For instance, all
8629 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8630 accepted. */
8631static void
8632do_t_arit3c (void)
8633{
8634 int Rd, Rs, Rn;
8635
8636 Rd = inst.operands[0].reg;
8637 Rs = (inst.operands[1].present
8638 ? inst.operands[1].reg /* Rd, Rs, foo */
8639 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
8640 Rn = inst.operands[2].reg;
8641
8642 if (unified_syntax)
8643 {
8644 if (!inst.operands[2].isreg)
8645 {
8646 /* For an immediate, we always generate a 32-bit opcode;
8647 section relaxation will shrink it later if possible. */
8648 inst.instruction = THUMB_OP32 (inst.instruction);
8649 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
8650 inst.instruction |= Rd << 8;
8651 inst.instruction |= Rs << 16;
8652 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
8653 }
8654 else
8655 {
8656 bfd_boolean narrow;
8657
8658 /* See if we can do this with a 16-bit instruction. */
8659 if (THUMB_SETS_FLAGS (inst.instruction))
8660 narrow = current_it_mask == 0;
8661 else
8662 narrow = current_it_mask != 0;
8663
8664 if (Rd > 7 || Rn > 7 || Rs > 7)
8665 narrow = FALSE;
8666 if (inst.operands[2].shifted)
8667 narrow = FALSE;
8668 if (inst.size_req == 4)
8669 narrow = FALSE;
8670
8671 if (narrow)
8672 {
8673 if (Rd == Rs)
8674 {
8675 inst.instruction = THUMB_OP16 (inst.instruction);
8676 inst.instruction |= Rd;
8677 inst.instruction |= Rn << 3;
8678 return;
8679 }
8680 if (Rd == Rn)
8681 {
8682 inst.instruction = THUMB_OP16 (inst.instruction);
8683 inst.instruction |= Rd;
8684 inst.instruction |= Rs << 3;
8685 return;
8686 }
8687 }
8688
8689 /* If we get here, it can't be done in 16 bits. */
8690 constraint (inst.operands[2].shifted
8691 && inst.operands[2].immisreg,
8692 _("shift must be constant"));
8693 inst.instruction = THUMB_OP32 (inst.instruction);
8694 inst.instruction |= Rd << 8;
8695 inst.instruction |= Rs << 16;
8696 encode_thumb32_shifted_operand (2);
8697 }
8698 }
8699 else
8700 {
8701 /* On its face this is a lie - the instruction does set the
8702 flags. However, the only supported mnemonic in this mode
8703 says it doesn't. */
8704 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
8705
8706 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
8707 _("unshifted register required"));
8708 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
8709
8710 inst.instruction = THUMB_OP16 (inst.instruction);
8711 inst.instruction |= Rd;
8712
8713 if (Rd == Rs)
8714 inst.instruction |= Rn << 3;
8715 else if (Rd == Rn)
8716 inst.instruction |= Rs << 3;
8717 else
8718 constraint (1, _("dest must overlap one source register"));
8719 }
8720}
8721
8722static void
8723do_t_barrier (void)
8724{
8725 if (inst.operands[0].present)
8726 {
8727 constraint ((inst.instruction & 0xf0) != 0x40
8728 && inst.operands[0].imm != 0xf,
8729 "bad barrier type");
8730 inst.instruction |= inst.operands[0].imm;
8731 }
8732 else
8733 inst.instruction |= 0xf;
8734}
8735
8736static void
8737do_t_bfc (void)
8738{
8739 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
8740 constraint (msb > 32, _("bit-field extends past end of register"));
8741 /* The instruction encoding stores the LSB and MSB,
8742 not the LSB and width. */
8743 inst.instruction |= inst.operands[0].reg << 8;
8744 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
8745 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
8746 inst.instruction |= msb - 1;
8747}
8748
8749static void
8750do_t_bfi (void)
8751{
8752 unsigned int msb;
8753
8754 /* #0 in second position is alternative syntax for bfc, which is
8755 the same instruction but with REG_PC in the Rm field. */
8756 if (!inst.operands[1].isreg)
8757 inst.operands[1].reg = REG_PC;
8758
8759 msb = inst.operands[2].imm + inst.operands[3].imm;
8760 constraint (msb > 32, _("bit-field extends past end of register"));
8761 /* The instruction encoding stores the LSB and MSB,
8762 not the LSB and width. */
8763 inst.instruction |= inst.operands[0].reg << 8;
8764 inst.instruction |= inst.operands[1].reg << 16;
8765 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
8766 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
8767 inst.instruction |= msb - 1;
8768}
8769
8770static void
8771do_t_bfx (void)
8772{
8773 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
8774 _("bit-field extends past end of register"));
8775 inst.instruction |= inst.operands[0].reg << 8;
8776 inst.instruction |= inst.operands[1].reg << 16;
8777 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
8778 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
8779 inst.instruction |= inst.operands[3].imm - 1;
8780}
8781
8782/* ARM V5 Thumb BLX (argument parse)
8783 BLX <target_addr> which is BLX(1)
8784 BLX <Rm> which is BLX(2)
8785 Unfortunately, there are two different opcodes for this mnemonic.
8786 So, the insns[].value is not used, and the code here zaps values
8787 into inst.instruction.
8788
8789 ??? How to take advantage of the additional two bits of displacement
8790 available in Thumb32 mode? Need new relocation? */
8791
8792static void
8793do_t_blx (void)
8794{
8795 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8796 if (inst.operands[0].isreg)
8797 /* We have a register, so this is BLX(2). */
8798 inst.instruction |= inst.operands[0].reg << 3;
8799 else
8800 {
8801 /* No register. This must be BLX(1). */
8802 inst.instruction = 0xf000e800;
8803#ifdef OBJ_ELF
8804 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
8805 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
8806 else
8807#endif
8808 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
8809 inst.reloc.pc_rel = 1;
8810 }
8811}
8812
8813static void
8814do_t_branch (void)
8815{
8816 int opcode;
8817 int cond;
8818
8819 if (current_it_mask)
8820 {
8821 /* Conditional branches inside IT blocks are encoded as unconditional
8822 branches. */
8823 cond = COND_ALWAYS;
8824 /* A branch must be the last instruction in an IT block. */
8825 constraint (current_it_mask != 0x10, BAD_BRANCH);
8826 }
8827 else
8828 cond = inst.cond;
8829
8830 if (cond != COND_ALWAYS)
8831 opcode = T_MNEM_bcond;
8832 else
8833 opcode = inst.instruction;
8834
8835 if (unified_syntax && inst.size_req == 4)
8836 {
8837 inst.instruction = THUMB_OP32(opcode);
8838 if (cond == COND_ALWAYS)
8839 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
8840 else
8841 {
8842 assert (cond != 0xF);
8843 inst.instruction |= cond << 22;
8844 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
8845 }
8846 }
8847 else
8848 {
8849 inst.instruction = THUMB_OP16(opcode);
8850 if (cond == COND_ALWAYS)
8851 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
8852 else
8853 {
8854 inst.instruction |= cond << 8;
8855 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
8856 }
8857 /* Allow section relaxation. */
8858 if (unified_syntax && inst.size_req != 2)
8859 inst.relax = opcode;
8860 }
8861
8862 inst.reloc.pc_rel = 1;
8863}
8864
8865static void
8866do_t_bkpt (void)
8867{
8868 constraint (inst.cond != COND_ALWAYS,
8869 _("instruction is always unconditional"));
8870 if (inst.operands[0].present)
8871 {
8872 constraint (inst.operands[0].imm > 255,
8873 _("immediate value out of range"));
8874 inst.instruction |= inst.operands[0].imm;
8875 }
8876}
8877
8878static void
8879do_t_branch23 (void)
8880{
8881 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8882 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
8883 inst.reloc.pc_rel = 1;
8884
8885 /* If the destination of the branch is a defined symbol which does not have
8886 the THUMB_FUNC attribute, then we must be calling a function which has
8887 the (interfacearm) attribute. We look for the Thumb entry point to that
8888 function and change the branch to refer to that function instead. */
8889 if ( inst.reloc.exp.X_op == O_symbol
8890 && inst.reloc.exp.X_add_symbol != NULL
8891 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
8892 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
8893 inst.reloc.exp.X_add_symbol =
8894 find_real_start (inst.reloc.exp.X_add_symbol);
8895}
8896
8897static void
8898do_t_bx (void)
8899{
8900 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8901 inst.instruction |= inst.operands[0].reg << 3;
8902 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8903 should cause the alignment to be checked once it is known. This is
8904 because BX PC only works if the instruction is word aligned. */
8905}
8906
8907static void
8908do_t_bxj (void)
8909{
8910 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8911 if (inst.operands[0].reg == REG_PC)
8912 as_tsktsk (_("use of r15 in bxj is not really useful"));
8913
8914 inst.instruction |= inst.operands[0].reg << 16;
8915}
8916
8917static void
8918do_t_clz (void)
8919{
8920 inst.instruction |= inst.operands[0].reg << 8;
8921 inst.instruction |= inst.operands[1].reg << 16;
8922 inst.instruction |= inst.operands[1].reg;
8923}
8924
8925static void
8926do_t_cps (void)
8927{
8928 constraint (current_it_mask, BAD_NOT_IT);
8929 inst.instruction |= inst.operands[0].imm;
8930}
8931
8932static void
8933do_t_cpsi (void)
8934{
8935 constraint (current_it_mask, BAD_NOT_IT);
8936 if (unified_syntax
8937 && (inst.operands[1].present || inst.size_req == 4)
8938 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
8939 {
8940 unsigned int imod = (inst.instruction & 0x0030) >> 4;
8941 inst.instruction = 0xf3af8000;
8942 inst.instruction |= imod << 9;
8943 inst.instruction |= inst.operands[0].imm << 5;
8944 if (inst.operands[1].present)
8945 inst.instruction |= 0x100 | inst.operands[1].imm;
8946 }
8947 else
8948 {
8949 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
8950 && (inst.operands[0].imm & 4),
8951 _("selected processor does not support 'A' form "
8952 "of this instruction"));
8953 constraint (inst.operands[1].present || inst.size_req == 4,
8954 _("Thumb does not support the 2-argument "
8955 "form of this instruction"));
8956 inst.instruction |= inst.operands[0].imm;
8957 }
8958}
8959
8960/* THUMB CPY instruction (argument parse). */
8961
8962static void
8963do_t_cpy (void)
8964{
8965 if (inst.size_req == 4)
8966 {
8967 inst.instruction = THUMB_OP32 (T_MNEM_mov);
8968 inst.instruction |= inst.operands[0].reg << 8;
8969 inst.instruction |= inst.operands[1].reg;
8970 }
8971 else
8972 {
8973 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
8974 inst.instruction |= (inst.operands[0].reg & 0x7);
8975 inst.instruction |= inst.operands[1].reg << 3;
8976 }
8977}
8978
8979static void
8980do_t_cbz (void)
8981{
8982 constraint (current_it_mask, BAD_NOT_IT);
8983 constraint (inst.operands[0].reg > 7, BAD_HIREG);
8984 inst.instruction |= inst.operands[0].reg;
8985 inst.reloc.pc_rel = 1;
8986 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
8987}
8988
8989static void
8990do_t_dbg (void)
8991{
8992 inst.instruction |= inst.operands[0].imm;
8993}
8994
8995static void
8996do_t_div (void)
8997{
8998 if (!inst.operands[1].present)
8999 inst.operands[1].reg = inst.operands[0].reg;
9000 inst.instruction |= inst.operands[0].reg << 8;
9001 inst.instruction |= inst.operands[1].reg << 16;
9002 inst.instruction |= inst.operands[2].reg;
9003}
9004
9005static void
9006do_t_hint (void)
9007{
9008 if (unified_syntax && inst.size_req == 4)
9009 inst.instruction = THUMB_OP32 (inst.instruction);
9010 else
9011 inst.instruction = THUMB_OP16 (inst.instruction);
9012}
9013
9014static void
9015do_t_it (void)
9016{
9017 unsigned int cond = inst.operands[0].imm;
9018
9019 constraint (current_it_mask, BAD_NOT_IT);
9020 current_it_mask = (inst.instruction & 0xf) | 0x10;
9021 current_cc = cond;
9022
9023 /* If the condition is a negative condition, invert the mask. */
9024 if ((cond & 0x1) == 0x0)
9025 {
9026 unsigned int mask = inst.instruction & 0x000f;
9027
9028 if ((mask & 0x7) == 0)
9029 /* no conversion needed */;
9030 else if ((mask & 0x3) == 0)
9031 mask ^= 0x8;
9032 else if ((mask & 0x1) == 0)
9033 mask ^= 0xC;
9034 else
9035 mask ^= 0xE;
9036
9037 inst.instruction &= 0xfff0;
9038 inst.instruction |= mask;
9039 }
9040
9041 inst.instruction |= cond << 4;
9042}
9043
9044/* Helper function used for both push/pop and ldm/stm. */
9045static void
9046encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
9047{
9048 bfd_boolean load;
9049
9050 load = (inst.instruction & (1 << 20)) != 0;
9051
9052 if (mask & (1 << 13))
9053 inst.error = _("SP not allowed in register list");
9054 if (load)
9055 {
9056 if (mask & (1 << 14)
9057 && mask & (1 << 15))
9058 inst.error = _("LR and PC should not both be in register list");
9059
9060 if ((mask & (1 << base)) != 0
9061 && writeback)
9062 as_warn (_("base register should not be in register list "
9063 "when written back"));
9064 }
9065 else
9066 {
9067 if (mask & (1 << 15))
9068 inst.error = _("PC not allowed in register list");
9069
9070 if (mask & (1 << base))
9071 as_warn (_("value stored for r%d is UNPREDICTABLE"), base);
9072 }
9073
9074 if ((mask & (mask - 1)) == 0)
9075 {
9076 /* Single register transfers implemented as str/ldr. */
9077 if (writeback)
9078 {
9079 if (inst.instruction & (1 << 23))
9080 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
9081 else
9082 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
9083 }
9084 else
9085 {
9086 if (inst.instruction & (1 << 23))
9087 inst.instruction = 0x00800000; /* ia -> [base] */
9088 else
9089 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
9090 }
9091
9092 inst.instruction |= 0xf8400000;
9093 if (load)
9094 inst.instruction |= 0x00100000;
9095
9096 mask = ffs(mask) - 1;
9097 mask <<= 12;
9098 }
9099 else if (writeback)
9100 inst.instruction |= WRITE_BACK;
9101
9102 inst.instruction |= mask;
9103 inst.instruction |= base << 16;
9104}
9105
9106static void
9107do_t_ldmstm (void)
9108{
9109 /* This really doesn't seem worth it. */
9110 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
9111 _("expression too complex"));
9112 constraint (inst.operands[1].writeback,
9113 _("Thumb load/store multiple does not support {reglist}^"));
9114
9115 if (unified_syntax)
9116 {
9117 bfd_boolean narrow;
9118 unsigned mask;
9119
9120 narrow = FALSE;
9121 /* See if we can use a 16-bit instruction. */
9122 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
9123 && inst.size_req != 4
9124 && !(inst.operands[1].imm & ~0xff))
9125 {
9126 mask = 1 << inst.operands[0].reg;
9127
9128 if (inst.operands[0].reg <= 7
9129 && (inst.instruction == T_MNEM_stmia
9130 ? inst.operands[0].writeback
9131 : (inst.operands[0].writeback
9132 == !(inst.operands[1].imm & mask))))
9133 {
9134 if (inst.instruction == T_MNEM_stmia
9135 && (inst.operands[1].imm & mask)
9136 && (inst.operands[1].imm & (mask - 1)))
9137 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9138 inst.operands[0].reg);
9139
9140 inst.instruction = THUMB_OP16 (inst.instruction);
9141 inst.instruction |= inst.operands[0].reg << 8;
9142 inst.instruction |= inst.operands[1].imm;
9143 narrow = TRUE;
9144 }
9145 else if (inst.operands[0] .reg == REG_SP
9146 && inst.operands[0].writeback)
9147 {
9148 inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia
9149 ? T_MNEM_push : T_MNEM_pop);
9150 inst.instruction |= inst.operands[1].imm;
9151 narrow = TRUE;
9152 }
9153 }
9154
9155 if (!narrow)
9156 {
9157 if (inst.instruction < 0xffff)
9158 inst.instruction = THUMB_OP32 (inst.instruction);
9159
9160 encode_thumb2_ldmstm(inst.operands[0].reg, inst.operands[1].imm,
9161 inst.operands[0].writeback);
9162 }
9163 }
9164 else
9165 {
9166 constraint (inst.operands[0].reg > 7
9167 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
9168 constraint (inst.instruction != T_MNEM_ldmia
9169 && inst.instruction != T_MNEM_stmia,
9170 _("Thumb-2 instruction only valid in unified syntax"));
9171 if (inst.instruction == T_MNEM_stmia)
9172 {
9173 if (!inst.operands[0].writeback)
9174 as_warn (_("this instruction will write back the base register"));
9175 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
9176 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
9177 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9178 inst.operands[0].reg);
9179 }
9180 else
9181 {
9182 if (!inst.operands[0].writeback
9183 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
9184 as_warn (_("this instruction will write back the base register"));
9185 else if (inst.operands[0].writeback
9186 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
9187 as_warn (_("this instruction will not write back the base register"));
9188 }
9189
9190 inst.instruction = THUMB_OP16 (inst.instruction);
9191 inst.instruction |= inst.operands[0].reg << 8;
9192 inst.instruction |= inst.operands[1].imm;
9193 }
9194}
9195
9196static void
9197do_t_ldrex (void)
9198{
9199 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
9200 || inst.operands[1].postind || inst.operands[1].writeback
9201 || inst.operands[1].immisreg || inst.operands[1].shifted
9202 || inst.operands[1].negative,
9203 BAD_ADDR_MODE);
9204
9205 inst.instruction |= inst.operands[0].reg << 12;
9206 inst.instruction |= inst.operands[1].reg << 16;
9207 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
9208}
9209
9210static void
9211do_t_ldrexd (void)
9212{
9213 if (!inst.operands[1].present)
9214 {
9215 constraint (inst.operands[0].reg == REG_LR,
9216 _("r14 not allowed as first register "
9217 "when second register is omitted"));
9218 inst.operands[1].reg = inst.operands[0].reg + 1;
9219 }
9220 constraint (inst.operands[0].reg == inst.operands[1].reg,
9221 BAD_OVERLAP);
9222
9223 inst.instruction |= inst.operands[0].reg << 12;
9224 inst.instruction |= inst.operands[1].reg << 8;
9225 inst.instruction |= inst.operands[2].reg << 16;
9226}
9227
9228static void
9229do_t_ldst (void)
9230{
9231 unsigned long opcode;
9232 int Rn;
9233
9234 opcode = inst.instruction;
9235 if (unified_syntax)
9236 {
9237 if (!inst.operands[1].isreg)
9238 {
9239 if (opcode <= 0xffff)
9240 inst.instruction = THUMB_OP32 (opcode);
9241 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
9242 return;
9243 }
9244 if (inst.operands[1].isreg
9245 && !inst.operands[1].writeback
9246 && !inst.operands[1].shifted && !inst.operands[1].postind
9247 && !inst.operands[1].negative && inst.operands[0].reg <= 7
9248 && opcode <= 0xffff
9249 && inst.size_req != 4)
9250 {
9251 /* Insn may have a 16-bit form. */
9252 Rn = inst.operands[1].reg;
9253 if (inst.operands[1].immisreg)
9254 {
9255 inst.instruction = THUMB_OP16 (opcode);
9256 /* [Rn, Ri] */
9257 if (Rn <= 7 && inst.operands[1].imm <= 7)
9258 goto op16;
9259 }
9260 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
9261 && opcode != T_MNEM_ldrsb)
9262 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
9263 || (Rn == REG_SP && opcode == T_MNEM_str))
9264 {
9265 /* [Rn, #const] */
9266 if (Rn > 7)
9267 {
9268 if (Rn == REG_PC)
9269 {
9270 if (inst.reloc.pc_rel)
9271 opcode = T_MNEM_ldr_pc2;
9272 else
9273 opcode = T_MNEM_ldr_pc;
9274 }
9275 else
9276 {
9277 if (opcode == T_MNEM_ldr)
9278 opcode = T_MNEM_ldr_sp;
9279 else
9280 opcode = T_MNEM_str_sp;
9281 }
9282 inst.instruction = inst.operands[0].reg << 8;
9283 }
9284 else
9285 {
9286 inst.instruction = inst.operands[0].reg;
9287 inst.instruction |= inst.operands[1].reg << 3;
9288 }
9289 inst.instruction |= THUMB_OP16 (opcode);
9290 if (inst.size_req == 2)
9291 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
9292 else
9293 inst.relax = opcode;
9294 return;
9295 }
9296 }
9297 /* Definitely a 32-bit variant. */
9298 inst.instruction = THUMB_OP32 (opcode);
9299 inst.instruction |= inst.operands[0].reg << 12;
9300 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
9301 return;
9302 }
9303
9304 constraint (inst.operands[0].reg > 7, BAD_HIREG);
9305
9306 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
9307 {
9308 /* Only [Rn,Rm] is acceptable. */
9309 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
9310 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
9311 || inst.operands[1].postind || inst.operands[1].shifted
9312 || inst.operands[1].negative,
9313 _("Thumb does not support this addressing mode"));
9314 inst.instruction = THUMB_OP16 (inst.instruction);
9315 goto op16;
9316 }
9317
9318 inst.instruction = THUMB_OP16 (inst.instruction);
9319 if (!inst.operands[1].isreg)
9320 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
9321 return;
9322
9323 constraint (!inst.operands[1].preind
9324 || inst.operands[1].shifted
9325 || inst.operands[1].writeback,
9326 _("Thumb does not support this addressing mode"));
9327 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
9328 {
9329 constraint (inst.instruction & 0x0600,
9330 _("byte or halfword not valid for base register"));
9331 constraint (inst.operands[1].reg == REG_PC
9332 && !(inst.instruction & THUMB_LOAD_BIT),
9333 _("r15 based store not allowed"));
9334 constraint (inst.operands[1].immisreg,
9335 _("invalid base register for register offset"));
9336
9337 if (inst.operands[1].reg == REG_PC)
9338 inst.instruction = T_OPCODE_LDR_PC;
9339 else if (inst.instruction & THUMB_LOAD_BIT)
9340 inst.instruction = T_OPCODE_LDR_SP;
9341 else
9342 inst.instruction = T_OPCODE_STR_SP;
9343
9344 inst.instruction |= inst.operands[0].reg << 8;
9345 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
9346 return;
9347 }
9348
9349 constraint (inst.operands[1].reg > 7, BAD_HIREG);
9350 if (!inst.operands[1].immisreg)
9351 {
9352 /* Immediate offset. */
9353 inst.instruction |= inst.operands[0].reg;
9354 inst.instruction |= inst.operands[1].reg << 3;
9355 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
9356 return;
9357 }
9358
9359 /* Register offset. */
9360 constraint (inst.operands[1].imm > 7, BAD_HIREG);
9361 constraint (inst.operands[1].negative,
9362 _("Thumb does not support this addressing mode"));
9363
9364 op16:
9365 switch (inst.instruction)
9366 {
9367 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
9368 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
9369 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
9370 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
9371 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
9372 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
9373 case 0x5600 /* ldrsb */:
9374 case 0x5e00 /* ldrsh */: break;
9375 default: abort ();
9376 }
9377
9378 inst.instruction |= inst.operands[0].reg;
9379 inst.instruction |= inst.operands[1].reg << 3;
9380 inst.instruction |= inst.operands[1].imm << 6;
9381}
9382
9383static void
9384do_t_ldstd (void)
9385{
9386 if (!inst.operands[1].present)
9387 {
9388 inst.operands[1].reg = inst.operands[0].reg + 1;
9389 constraint (inst.operands[0].reg == REG_LR,
9390 _("r14 not allowed here"));
9391 }
9392 inst.instruction |= inst.operands[0].reg << 12;
9393 inst.instruction |= inst.operands[1].reg << 8;
9394 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
9395
9396}
9397
9398static void
9399do_t_ldstt (void)
9400{
9401 inst.instruction |= inst.operands[0].reg << 12;
9402 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
9403}
9404
9405static void
9406do_t_mla (void)
9407{
9408 inst.instruction |= inst.operands[0].reg << 8;
9409 inst.instruction |= inst.operands[1].reg << 16;
9410 inst.instruction |= inst.operands[2].reg;
9411 inst.instruction |= inst.operands[3].reg << 12;
9412}
9413
9414static void
9415do_t_mlal (void)
9416{
9417 inst.instruction |= inst.operands[0].reg << 12;
9418 inst.instruction |= inst.operands[1].reg << 8;
9419 inst.instruction |= inst.operands[2].reg << 16;
9420 inst.instruction |= inst.operands[3].reg;
9421}
9422
9423static void
9424do_t_mov_cmp (void)
9425{
9426 if (unified_syntax)
9427 {
9428 int r0off = (inst.instruction == T_MNEM_mov
9429 || inst.instruction == T_MNEM_movs) ? 8 : 16;
9430 unsigned long opcode;
9431 bfd_boolean narrow;
9432 bfd_boolean low_regs;
9433
9434 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7);
9435 opcode = inst.instruction;
9436 if (current_it_mask)
9437 narrow = opcode != T_MNEM_movs;
9438 else
9439 narrow = opcode != T_MNEM_movs || low_regs;
9440 if (inst.size_req == 4
9441 || inst.operands[1].shifted)
9442 narrow = FALSE;
9443
9444 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
9445 if (opcode == T_MNEM_movs && inst.operands[1].isreg
9446 && !inst.operands[1].shifted
9447 && inst.operands[0].reg == REG_PC
9448 && inst.operands[1].reg == REG_LR)
9449 {
9450 inst.instruction = T2_SUBS_PC_LR;
9451 return;
9452 }
9453
9454 if (!inst.operands[1].isreg)
9455 {
9456 /* Immediate operand. */
9457 if (current_it_mask == 0 && opcode == T_MNEM_mov)
9458 narrow = 0;
9459 if (low_regs && narrow)
9460 {
9461 inst.instruction = THUMB_OP16 (opcode);
9462 inst.instruction |= inst.operands[0].reg << 8;
9463 if (inst.size_req == 2)
9464 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
9465 else
9466 inst.relax = opcode;
9467 }
9468 else
9469 {
9470 inst.instruction = THUMB_OP32 (inst.instruction);
9471 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9472 inst.instruction |= inst.operands[0].reg << r0off;
9473 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9474 }
9475 }
9476 else if (inst.operands[1].shifted && inst.operands[1].immisreg
9477 && (inst.instruction == T_MNEM_mov
9478 || inst.instruction == T_MNEM_movs))
9479 {
9480 /* Register shifts are encoded as separate shift instructions. */
9481 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
9482
9483 if (current_it_mask)
9484 narrow = !flags;
9485 else
9486 narrow = flags;
9487
9488 if (inst.size_req == 4)
9489 narrow = FALSE;
9490
9491 if (!low_regs || inst.operands[1].imm > 7)
9492 narrow = FALSE;
9493
9494 if (inst.operands[0].reg != inst.operands[1].reg)
9495 narrow = FALSE;
9496
9497 switch (inst.operands[1].shift_kind)
9498 {
9499 case SHIFT_LSL:
9500 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
9501 break;
9502 case SHIFT_ASR:
9503 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
9504 break;
9505 case SHIFT_LSR:
9506 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
9507 break;
9508 case SHIFT_ROR:
9509 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
9510 break;
9511 default:
9512 abort();
9513 }
9514
9515 inst.instruction = opcode;
9516 if (narrow)
9517 {
9518 inst.instruction |= inst.operands[0].reg;
9519 inst.instruction |= inst.operands[1].imm << 3;
9520 }
9521 else
9522 {
9523 if (flags)
9524 inst.instruction |= CONDS_BIT;
9525
9526 inst.instruction |= inst.operands[0].reg << 8;
9527 inst.instruction |= inst.operands[1].reg << 16;
9528 inst.instruction |= inst.operands[1].imm;
9529 }
9530 }
9531 else if (!narrow)
9532 {
9533 /* Some mov with immediate shift have narrow variants.
9534 Register shifts are handled above. */
9535 if (low_regs && inst.operands[1].shifted
9536 && (inst.instruction == T_MNEM_mov
9537 || inst.instruction == T_MNEM_movs))
9538 {
9539 if (current_it_mask)
9540 narrow = (inst.instruction == T_MNEM_mov);
9541 else
9542 narrow = (inst.instruction == T_MNEM_movs);
9543 }
9544
9545 if (narrow)
9546 {
9547 switch (inst.operands[1].shift_kind)
9548 {
9549 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
9550 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
9551 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
9552 default: narrow = FALSE; break;
9553 }
9554 }
9555
9556 if (narrow)
9557 {
9558 inst.instruction |= inst.operands[0].reg;
9559 inst.instruction |= inst.operands[1].reg << 3;
9560 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
9561 }
9562 else
9563 {
9564 inst.instruction = THUMB_OP32 (inst.instruction);
9565 inst.instruction |= inst.operands[0].reg << r0off;
9566 encode_thumb32_shifted_operand (1);
9567 }
9568 }
9569 else
9570 switch (inst.instruction)
9571 {
9572 case T_MNEM_mov:
9573 inst.instruction = T_OPCODE_MOV_HR;
9574 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9575 inst.instruction |= (inst.operands[0].reg & 0x7);
9576 inst.instruction |= inst.operands[1].reg << 3;
9577 break;
9578
9579 case T_MNEM_movs:
9580 /* We know we have low registers at this point.
9581 Generate ADD Rd, Rs, #0. */
9582 inst.instruction = T_OPCODE_ADD_I3;
9583 inst.instruction |= inst.operands[0].reg;
9584 inst.instruction |= inst.operands[1].reg << 3;
9585 break;
9586
9587 case T_MNEM_cmp:
9588 if (low_regs)
9589 {
9590 inst.instruction = T_OPCODE_CMP_LR;
9591 inst.instruction |= inst.operands[0].reg;
9592 inst.instruction |= inst.operands[1].reg << 3;
9593 }
9594 else
9595 {
9596 inst.instruction = T_OPCODE_CMP_HR;
9597 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9598 inst.instruction |= (inst.operands[0].reg & 0x7);
9599 inst.instruction |= inst.operands[1].reg << 3;
9600 }
9601 break;
9602 }
9603 return;
9604 }
9605
9606 inst.instruction = THUMB_OP16 (inst.instruction);
9607 if (inst.operands[1].isreg)
9608 {
9609 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
9610 {
9611 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9612 since a MOV instruction produces unpredictable results. */
9613 if (inst.instruction == T_OPCODE_MOV_I8)
9614 inst.instruction = T_OPCODE_ADD_I3;
9615 else
9616 inst.instruction = T_OPCODE_CMP_LR;
9617
9618 inst.instruction |= inst.operands[0].reg;
9619 inst.instruction |= inst.operands[1].reg << 3;
9620 }
9621 else
9622 {
9623 if (inst.instruction == T_OPCODE_MOV_I8)
9624 inst.instruction = T_OPCODE_MOV_HR;
9625 else
9626 inst.instruction = T_OPCODE_CMP_HR;
9627 do_t_cpy ();
9628 }
9629 }
9630 else
9631 {
9632 constraint (inst.operands[0].reg > 7,
9633 _("only lo regs allowed with immediate"));
9634 inst.instruction |= inst.operands[0].reg << 8;
9635 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
9636 }
9637}
9638
9639static void
9640do_t_mov16 (void)
9641{
9642 bfd_vma imm;
9643 bfd_boolean top;
9644
9645 top = (inst.instruction & 0x00800000) != 0;
9646 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
9647 {
9648 constraint (top, _(":lower16: not allowed this instruction"));
9649 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
9650 }
9651 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
9652 {
9653 constraint (!top, _(":upper16: not allowed this instruction"));
9654 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
9655 }
9656
9657 inst.instruction |= inst.operands[0].reg << 8;
9658 if (inst.reloc.type == BFD_RELOC_UNUSED)
9659 {
9660 imm = inst.reloc.exp.X_add_number;
9661 inst.instruction |= (imm & 0xf000) << 4;
9662 inst.instruction |= (imm & 0x0800) << 15;
9663 inst.instruction |= (imm & 0x0700) << 4;
9664 inst.instruction |= (imm & 0x00ff);
9665 }
9666}
9667
9668static void
9669do_t_mvn_tst (void)
9670{
9671 if (unified_syntax)
9672 {
9673 int r0off = (inst.instruction == T_MNEM_mvn
9674 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
9675 bfd_boolean narrow;
9676
9677 if (inst.size_req == 4
9678 || inst.instruction > 0xffff
9679 || inst.operands[1].shifted
9680 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
9681 narrow = FALSE;
9682 else if (inst.instruction == T_MNEM_cmn)
9683 narrow = TRUE;
9684 else if (THUMB_SETS_FLAGS (inst.instruction))
9685 narrow = (current_it_mask == 0);
9686 else
9687 narrow = (current_it_mask != 0);
9688
9689 if (!inst.operands[1].isreg)
9690 {
9691 /* For an immediate, we always generate a 32-bit opcode;
9692 section relaxation will shrink it later if possible. */
9693 if (inst.instruction < 0xffff)
9694 inst.instruction = THUMB_OP32 (inst.instruction);
9695 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9696 inst.instruction |= inst.operands[0].reg << r0off;
9697 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9698 }
9699 else
9700 {
9701 /* See if we can do this with a 16-bit instruction. */
9702 if (narrow)
9703 {
9704 inst.instruction = THUMB_OP16 (inst.instruction);
9705 inst.instruction |= inst.operands[0].reg;
9706 inst.instruction |= inst.operands[1].reg << 3;
9707 }
9708 else
9709 {
9710 constraint (inst.operands[1].shifted
9711 && inst.operands[1].immisreg,
9712 _("shift must be constant"));
9713 if (inst.instruction < 0xffff)
9714 inst.instruction = THUMB_OP32 (inst.instruction);
9715 inst.instruction |= inst.operands[0].reg << r0off;
9716 encode_thumb32_shifted_operand (1);
9717 }
9718 }
9719 }
9720 else
9721 {
9722 constraint (inst.instruction > 0xffff
9723 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
9724 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
9725 _("unshifted register required"));
9726 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9727 BAD_HIREG);
9728
9729 inst.instruction = THUMB_OP16 (inst.instruction);
9730 inst.instruction |= inst.operands[0].reg;
9731 inst.instruction |= inst.operands[1].reg << 3;
9732 }
9733}
9734
9735static void
9736do_t_mrs (void)
9737{
9738 int flags;
9739
9740 if (do_vfp_nsyn_mrs () == SUCCESS)
9741 return;
9742
9743 flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
9744 if (flags == 0)
9745 {
9746 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m),
9747 _("selected processor does not support "
9748 "requested special purpose register"));
9749 }
9750 else
9751 {
9752 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
9753 _("selected processor does not support "
9754 "requested special purpose register %x"));
9755 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9756 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
9757 _("'CPSR' or 'SPSR' expected"));
9758 }
9759
9760 inst.instruction |= inst.operands[0].reg << 8;
9761 inst.instruction |= (flags & SPSR_BIT) >> 2;
9762 inst.instruction |= inst.operands[1].imm & 0xff;
9763}
9764
9765static void
9766do_t_msr (void)
9767{
9768 int flags;
9769
9770 if (do_vfp_nsyn_msr () == SUCCESS)
9771 return;
9772
9773 constraint (!inst.operands[1].isreg,
9774 _("Thumb encoding does not support an immediate here"));
9775 flags = inst.operands[0].imm;
9776 if (flags & ~0xff)
9777 {
9778 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
9779 _("selected processor does not support "
9780 "requested special purpose register"));
9781 }
9782 else
9783 {
9784 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m),
9785 _("selected processor does not support "
9786 "requested special purpose register"));
9787 flags |= PSR_f;
9788 }
9789 inst.instruction |= (flags & SPSR_BIT) >> 2;
9790 inst.instruction |= (flags & ~SPSR_BIT) >> 8;
9791 inst.instruction |= (flags & 0xff);
9792 inst.instruction |= inst.operands[1].reg << 16;
9793}
9794
9795static void
9796do_t_mul (void)
9797{
9798 if (!inst.operands[2].present)
9799 inst.operands[2].reg = inst.operands[0].reg;
9800
9801 /* There is no 32-bit MULS and no 16-bit MUL. */
9802 if (unified_syntax && inst.instruction == T_MNEM_mul)
9803 {
9804 inst.instruction = THUMB_OP32 (inst.instruction);
9805 inst.instruction |= inst.operands[0].reg << 8;
9806 inst.instruction |= inst.operands[1].reg << 16;
9807 inst.instruction |= inst.operands[2].reg << 0;
9808 }
9809 else
9810 {
9811 constraint (!unified_syntax
9812 && inst.instruction == T_MNEM_muls, BAD_THUMB32);
9813 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9814 BAD_HIREG);
9815
9816 inst.instruction = THUMB_OP16 (inst.instruction);
9817 inst.instruction |= inst.operands[0].reg;
9818
9819 if (inst.operands[0].reg == inst.operands[1].reg)
9820 inst.instruction |= inst.operands[2].reg << 3;
9821 else if (inst.operands[0].reg == inst.operands[2].reg)
9822 inst.instruction |= inst.operands[1].reg << 3;
9823 else
9824 constraint (1, _("dest must overlap one source register"));
9825 }
9826}
9827
9828static void
9829do_t_mull (void)
9830{
9831 inst.instruction |= inst.operands[0].reg << 12;
9832 inst.instruction |= inst.operands[1].reg << 8;
9833 inst.instruction |= inst.operands[2].reg << 16;
9834 inst.instruction |= inst.operands[3].reg;
9835
9836 if (inst.operands[0].reg == inst.operands[1].reg)
9837 as_tsktsk (_("rdhi and rdlo must be different"));
9838}
9839
9840static void
9841do_t_nop (void)
9842{
9843 if (unified_syntax)
9844 {
9845 if (inst.size_req == 4 || inst.operands[0].imm > 15)
9846 {
9847 inst.instruction = THUMB_OP32 (inst.instruction);
9848 inst.instruction |= inst.operands[0].imm;
9849 }
9850 else
9851 {
9852 inst.instruction = THUMB_OP16 (inst.instruction);
9853 inst.instruction |= inst.operands[0].imm << 4;
9854 }
9855 }
9856 else
9857 {
9858 constraint (inst.operands[0].present,
9859 _("Thumb does not support NOP with hints"));
9860 inst.instruction = 0x46c0;
9861 }
9862}
9863
9864static void
9865do_t_neg (void)
9866{
9867 if (unified_syntax)
9868 {
9869 bfd_boolean narrow;
9870
9871 if (THUMB_SETS_FLAGS (inst.instruction))
9872 narrow = (current_it_mask == 0);
9873 else
9874 narrow = (current_it_mask != 0);
9875 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
9876 narrow = FALSE;
9877 if (inst.size_req == 4)
9878 narrow = FALSE;
9879
9880 if (!narrow)
9881 {
9882 inst.instruction = THUMB_OP32 (inst.instruction);
9883 inst.instruction |= inst.operands[0].reg << 8;
9884 inst.instruction |= inst.operands[1].reg << 16;
9885 }
9886 else
9887 {
9888 inst.instruction = THUMB_OP16 (inst.instruction);
9889 inst.instruction |= inst.operands[0].reg;
9890 inst.instruction |= inst.operands[1].reg << 3;
9891 }
9892 }
9893 else
9894 {
9895 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9896 BAD_HIREG);
9897 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9898
9899 inst.instruction = THUMB_OP16 (inst.instruction);
9900 inst.instruction |= inst.operands[0].reg;
9901 inst.instruction |= inst.operands[1].reg << 3;
9902 }
9903}
9904
9905static void
9906do_t_pkhbt (void)
9907{
9908 inst.instruction |= inst.operands[0].reg << 8;
9909 inst.instruction |= inst.operands[1].reg << 16;
9910 inst.instruction |= inst.operands[2].reg;
9911 if (inst.operands[3].present)
9912 {
9913 unsigned int val = inst.reloc.exp.X_add_number;
9914 constraint (inst.reloc.exp.X_op != O_constant,
9915 _("expression too complex"));
9916 inst.instruction |= (val & 0x1c) << 10;
9917 inst.instruction |= (val & 0x03) << 6;
9918 }
9919}
9920
9921static void
9922do_t_pkhtb (void)
9923{
9924 if (!inst.operands[3].present)
9925 inst.instruction &= ~0x00000020;
9926 do_t_pkhbt ();
9927}
9928
9929static void
9930do_t_pld (void)
9931{
9932 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
9933}
9934
9935static void
9936do_t_push_pop (void)
9937{
9938 unsigned mask;
9939
9940 constraint (inst.operands[0].writeback,
9941 _("push/pop do not support {reglist}^"));
9942 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
9943 _("expression too complex"));
9944
9945 mask = inst.operands[0].imm;
9946 if ((mask & ~0xff) == 0)
9947 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
9948 else if ((inst.instruction == T_MNEM_push
9949 && (mask & ~0xff) == 1 << REG_LR)
9950 || (inst.instruction == T_MNEM_pop
9951 && (mask & ~0xff) == 1 << REG_PC))
9952 {
9953 inst.instruction = THUMB_OP16 (inst.instruction);
9954 inst.instruction |= THUMB_PP_PC_LR;
9955 inst.instruction |= mask & 0xff;
9956 }
9957 else if (unified_syntax)
9958 {
9959 inst.instruction = THUMB_OP32 (inst.instruction);
9960 encode_thumb2_ldmstm(13, mask, TRUE);
9961 }
9962 else
9963 {
9964 inst.error = _("invalid register list to push/pop instruction");
9965 return;
9966 }
9967}
9968
9969static void
9970do_t_rbit (void)
9971{
9972 inst.instruction |= inst.operands[0].reg << 8;
9973 inst.instruction |= inst.operands[1].reg << 16;
9974}
9975
9976static void
9977do_t_rd_rm (void)
9978{
9979 inst.instruction |= inst.operands[0].reg << 8;
9980 inst.instruction |= inst.operands[1].reg;
9981}
9982
9983static void
9984do_t_rev (void)
9985{
9986 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
9987 && inst.size_req != 4)
9988 {
9989 inst.instruction = THUMB_OP16 (inst.instruction);
9990 inst.instruction |= inst.operands[0].reg;
9991 inst.instruction |= inst.operands[1].reg << 3;
9992 }
9993 else if (unified_syntax)
9994 {
9995 inst.instruction = THUMB_OP32 (inst.instruction);
9996 inst.instruction |= inst.operands[0].reg << 8;
9997 inst.instruction |= inst.operands[1].reg << 16;
9998 inst.instruction |= inst.operands[1].reg;
9999 }
10000 else
10001 inst.error = BAD_HIREG;
10002}
10003
10004static void
10005do_t_rsb (void)
10006{
10007 int Rd, Rs;
10008
10009 Rd = inst.operands[0].reg;
10010 Rs = (inst.operands[1].present
10011 ? inst.operands[1].reg /* Rd, Rs, foo */
10012 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10013
10014 inst.instruction |= Rd << 8;
10015 inst.instruction |= Rs << 16;
10016 if (!inst.operands[2].isreg)
10017 {
10018 bfd_boolean narrow;
10019
10020 if ((inst.instruction & 0x00100000) != 0)
10021 narrow = (current_it_mask == 0);
10022 else
10023 narrow = (current_it_mask != 0);
10024
10025 if (Rd > 7 || Rs > 7)
10026 narrow = FALSE;
10027
10028 if (inst.size_req == 4 || !unified_syntax)
10029 narrow = FALSE;
10030
10031 if (inst.reloc.exp.X_op != O_constant
10032 || inst.reloc.exp.X_add_number != 0)
10033 narrow = FALSE;
10034
10035 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10036 relaxation, but it doesn't seem worth the hassle. */
10037 if (narrow)
10038 {
10039 inst.reloc.type = BFD_RELOC_UNUSED;
10040 inst.instruction = THUMB_OP16 (T_MNEM_negs);
10041 inst.instruction |= Rs << 3;
10042 inst.instruction |= Rd;
10043 }
10044 else
10045 {
10046 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10047 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10048 }
10049 }
10050 else
10051 encode_thumb32_shifted_operand (2);
10052}
10053
10054static void
10055do_t_setend (void)
10056{
10057 constraint (current_it_mask, BAD_NOT_IT);
10058 if (inst.operands[0].imm)
10059 inst.instruction |= 0x8;
10060}
10061
10062static void
10063do_t_shift (void)
10064{
10065 if (!inst.operands[1].present)
10066 inst.operands[1].reg = inst.operands[0].reg;
10067
10068 if (unified_syntax)
10069 {
10070 bfd_boolean narrow;
10071 int shift_kind;
10072
10073 switch (inst.instruction)
10074 {
10075 case T_MNEM_asr:
10076 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
10077 case T_MNEM_lsl:
10078 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
10079 case T_MNEM_lsr:
10080 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
10081 case T_MNEM_ror:
10082 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
10083 default: abort ();
10084 }
10085
10086 if (THUMB_SETS_FLAGS (inst.instruction))
10087 narrow = (current_it_mask == 0);
10088 else
10089 narrow = (current_it_mask != 0);
10090 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
10091 narrow = FALSE;
10092 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
10093 narrow = FALSE;
10094 if (inst.operands[2].isreg
10095 && (inst.operands[1].reg != inst.operands[0].reg
10096 || inst.operands[2].reg > 7))
10097 narrow = FALSE;
10098 if (inst.size_req == 4)
10099 narrow = FALSE;
10100
10101 if (!narrow)
10102 {
10103 if (inst.operands[2].isreg)
10104 {
10105 inst.instruction = THUMB_OP32 (inst.instruction);
10106 inst.instruction |= inst.operands[0].reg << 8;
10107 inst.instruction |= inst.operands[1].reg << 16;
10108 inst.instruction |= inst.operands[2].reg;
10109 }
10110 else
10111 {
10112 inst.operands[1].shifted = 1;
10113 inst.operands[1].shift_kind = shift_kind;
10114 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
10115 ? T_MNEM_movs : T_MNEM_mov);
10116 inst.instruction |= inst.operands[0].reg << 8;
10117 encode_thumb32_shifted_operand (1);
10118 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10119 inst.reloc.type = BFD_RELOC_UNUSED;
10120 }
10121 }
10122 else
10123 {
10124 if (inst.operands[2].isreg)
10125 {
10126 switch (shift_kind)
10127 {
10128 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
10129 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
10130 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
10131 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
10132 default: abort ();
10133 }
10134
10135 inst.instruction |= inst.operands[0].reg;
10136 inst.instruction |= inst.operands[2].reg << 3;
10137 }
10138 else
10139 {
10140 switch (shift_kind)
10141 {
10142 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
10143 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
10144 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
10145 default: abort ();
10146 }
10147 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10148 inst.instruction |= inst.operands[0].reg;
10149 inst.instruction |= inst.operands[1].reg << 3;
10150 }
10151 }
10152 }
10153 else
10154 {
10155 constraint (inst.operands[0].reg > 7
10156 || inst.operands[1].reg > 7, BAD_HIREG);
10157 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10158
10159 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
10160 {
10161 constraint (inst.operands[2].reg > 7, BAD_HIREG);
10162 constraint (inst.operands[0].reg != inst.operands[1].reg,
10163 _("source1 and dest must be same register"));
10164
10165 switch (inst.instruction)
10166 {
10167 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
10168 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
10169 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
10170 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
10171 default: abort ();
10172 }
10173
10174 inst.instruction |= inst.operands[0].reg;
10175 inst.instruction |= inst.operands[2].reg << 3;
10176 }
10177 else
10178 {
10179 switch (inst.instruction)
10180 {
10181 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
10182 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
10183 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
10184 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
10185 default: abort ();
10186 }
10187 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10188 inst.instruction |= inst.operands[0].reg;
10189 inst.instruction |= inst.operands[1].reg << 3;
10190 }
10191 }
10192}
10193
10194static void
10195do_t_simd (void)
10196{
10197 inst.instruction |= inst.operands[0].reg << 8;
10198 inst.instruction |= inst.operands[1].reg << 16;
10199 inst.instruction |= inst.operands[2].reg;
10200}
10201
10202static void
10203do_t_smc (void)
10204{
10205 unsigned int value = inst.reloc.exp.X_add_number;
10206 constraint (inst.reloc.exp.X_op != O_constant,
10207 _("expression too complex"));
10208 inst.reloc.type = BFD_RELOC_UNUSED;
10209 inst.instruction |= (value & 0xf000) >> 12;
10210 inst.instruction |= (value & 0x0ff0);
10211 inst.instruction |= (value & 0x000f) << 16;
10212}
10213
10214static void
10215do_t_ssat (void)
10216{
10217 inst.instruction |= inst.operands[0].reg << 8;
10218 inst.instruction |= inst.operands[1].imm - 1;
10219 inst.instruction |= inst.operands[2].reg << 16;
10220
10221 if (inst.operands[3].present)
10222 {
10223 constraint (inst.reloc.exp.X_op != O_constant,
10224 _("expression too complex"));
10225
10226 if (inst.reloc.exp.X_add_number != 0)
10227 {
10228 if (inst.operands[3].shift_kind == SHIFT_ASR)
10229 inst.instruction |= 0x00200000; /* sh bit */
10230 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
10231 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
10232 }
10233 inst.reloc.type = BFD_RELOC_UNUSED;
10234 }
10235}
10236
10237static void
10238do_t_ssat16 (void)
10239{
10240 inst.instruction |= inst.operands[0].reg << 8;
10241 inst.instruction |= inst.operands[1].imm - 1;
10242 inst.instruction |= inst.operands[2].reg << 16;
10243}
10244
10245static void
10246do_t_strex (void)
10247{
10248 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10249 || inst.operands[2].postind || inst.operands[2].writeback
10250 || inst.operands[2].immisreg || inst.operands[2].shifted
10251 || inst.operands[2].negative,
10252 BAD_ADDR_MODE);
10253
10254 inst.instruction |= inst.operands[0].reg << 8;
10255 inst.instruction |= inst.operands[1].reg << 12;
10256 inst.instruction |= inst.operands[2].reg << 16;
10257 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10258}
10259
10260static void
10261do_t_strexd (void)
10262{
10263 if (!inst.operands[2].present)
10264 inst.operands[2].reg = inst.operands[1].reg + 1;
10265
10266 constraint (inst.operands[0].reg == inst.operands[1].reg
10267 || inst.operands[0].reg == inst.operands[2].reg
10268 || inst.operands[0].reg == inst.operands[3].reg
10269 || inst.operands[1].reg == inst.operands[2].reg,
10270 BAD_OVERLAP);
10271
10272 inst.instruction |= inst.operands[0].reg;
10273 inst.instruction |= inst.operands[1].reg << 12;
10274 inst.instruction |= inst.operands[2].reg << 8;
10275 inst.instruction |= inst.operands[3].reg << 16;
10276}
10277
10278static void
10279do_t_sxtah (void)
10280{
10281 inst.instruction |= inst.operands[0].reg << 8;
10282 inst.instruction |= inst.operands[1].reg << 16;
10283 inst.instruction |= inst.operands[2].reg;
10284 inst.instruction |= inst.operands[3].imm << 4;
10285}
10286
10287static void
10288do_t_sxth (void)
10289{
10290 if (inst.instruction <= 0xffff && inst.size_req != 4
10291 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
10292 && (!inst.operands[2].present || inst.operands[2].imm == 0))
10293 {
10294 inst.instruction = THUMB_OP16 (inst.instruction);
10295 inst.instruction |= inst.operands[0].reg;
10296 inst.instruction |= inst.operands[1].reg << 3;
10297 }
10298 else if (unified_syntax)
10299 {
10300 if (inst.instruction <= 0xffff)
10301 inst.instruction = THUMB_OP32 (inst.instruction);
10302 inst.instruction |= inst.operands[0].reg << 8;
10303 inst.instruction |= inst.operands[1].reg;
10304 inst.instruction |= inst.operands[2].imm << 4;
10305 }
10306 else
10307 {
10308 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
10309 _("Thumb encoding does not support rotation"));
10310 constraint (1, BAD_HIREG);
10311 }
10312}
10313
10314static void
10315do_t_swi (void)
10316{
10317 inst.reloc.type = BFD_RELOC_ARM_SWI;
10318}
10319
10320static void
10321do_t_tb (void)
10322{
10323 int half;
10324
10325 half = (inst.instruction & 0x10) != 0;
10326 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
10327 constraint (inst.operands[0].immisreg,
10328 _("instruction requires register index"));
10329 constraint (inst.operands[0].imm == 15,
10330 _("PC is not a valid index register"));
10331 constraint (!half && inst.operands[0].shifted,
10332 _("instruction does not allow shifted index"));
10333 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm;
10334}
10335
10336static void
10337do_t_usat (void)
10338{
10339 inst.instruction |= inst.operands[0].reg << 8;
10340 inst.instruction |= inst.operands[1].imm;
10341 inst.instruction |= inst.operands[2].reg << 16;
10342
10343 if (inst.operands[3].present)
10344 {
10345 constraint (inst.reloc.exp.X_op != O_constant,
10346 _("expression too complex"));
10347 if (inst.reloc.exp.X_add_number != 0)
10348 {
10349 if (inst.operands[3].shift_kind == SHIFT_ASR)
10350 inst.instruction |= 0x00200000; /* sh bit */
10351
10352 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
10353 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
10354 }
10355 inst.reloc.type = BFD_RELOC_UNUSED;
10356 }
10357}
10358
10359static void
10360do_t_usat16 (void)
10361{
10362 inst.instruction |= inst.operands[0].reg << 8;
10363 inst.instruction |= inst.operands[1].imm;
10364 inst.instruction |= inst.operands[2].reg << 16;
10365}
10366
10367/* Neon instruction encoder helpers. */
10368
10369/* Encodings for the different types for various Neon opcodes. */
10370
10371/* An "invalid" code for the following tables. */
10372#define N_INV -1u
10373
10374struct neon_tab_entry
10375{
10376 unsigned integer;
10377 unsigned float_or_poly;
10378 unsigned scalar_or_imm;
10379};
10380
10381/* Map overloaded Neon opcodes to their respective encodings. */
10382#define NEON_ENC_TAB \
10383 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10384 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10385 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10386 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10387 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10388 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10389 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10390 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10391 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10392 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10393 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10394 /* Register variants of the following two instructions are encoded as
10395 vcge / vcgt with the operands reversed. */ \
10396 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10397 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
10398 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10399 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10400 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10401 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10402 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10403 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10404 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10405 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10406 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10407 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10408 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10409 X(vshl, 0x0000400, N_INV, 0x0800510), \
10410 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10411 X(vand, 0x0000110, N_INV, 0x0800030), \
10412 X(vbic, 0x0100110, N_INV, 0x0800030), \
10413 X(veor, 0x1000110, N_INV, N_INV), \
10414 X(vorn, 0x0300110, N_INV, 0x0800010), \
10415 X(vorr, 0x0200110, N_INV, 0x0800010), \
10416 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10417 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10418 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10419 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10420 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10421 X(vst1, 0x0000000, 0x0800000, N_INV), \
10422 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10423 X(vst2, 0x0000100, 0x0800100, N_INV), \
10424 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10425 X(vst3, 0x0000200, 0x0800200, N_INV), \
10426 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10427 X(vst4, 0x0000300, 0x0800300, N_INV), \
10428 X(vmovn, 0x1b20200, N_INV, N_INV), \
10429 X(vtrn, 0x1b20080, N_INV, N_INV), \
10430 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10431 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10432 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10433 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10434 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10435 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10436 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10437 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10438 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10439
10440enum neon_opc
10441{
10442#define X(OPC,I,F,S) N_MNEM_##OPC
10443NEON_ENC_TAB
10444#undef X
10445};
10446
10447static const struct neon_tab_entry neon_enc_tab[] =
10448{
10449#define X(OPC,I,F,S) { (I), (F), (S) }
10450NEON_ENC_TAB
10451#undef X
10452};
10453
10454#define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10455#define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10456#define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10457#define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10458#define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10459#define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10460#define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10461#define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10462#define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10463#define NEON_ENC_SINGLE(X) \
10464 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10465#define NEON_ENC_DOUBLE(X) \
10466 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10467
10468/* Define shapes for instruction operands. The following mnemonic characters
10469 are used in this table:
10470
10471 F - VFP S<n> register
10472 D - Neon D<n> register
10473 Q - Neon Q<n> register
10474 I - Immediate
10475 S - Scalar
10476 R - ARM register
10477 L - D<n> register list
10478
10479 This table is used to generate various data:
10480 - enumerations of the form NS_DDR to be used as arguments to
10481 neon_select_shape.
10482 - a table classifying shapes into single, double, quad, mixed.
10483 - a table used to drive neon_select_shape.
10484*/
10485
10486#define NEON_SHAPE_DEF \
10487 X(3, (D, D, D), DOUBLE), \
10488 X(3, (Q, Q, Q), QUAD), \
10489 X(3, (D, D, I), DOUBLE), \
10490 X(3, (Q, Q, I), QUAD), \
10491 X(3, (D, D, S), DOUBLE), \
10492 X(3, (Q, Q, S), QUAD), \
10493 X(2, (D, D), DOUBLE), \
10494 X(2, (Q, Q), QUAD), \
10495 X(2, (D, S), DOUBLE), \
10496 X(2, (Q, S), QUAD), \
10497 X(2, (D, R), DOUBLE), \
10498 X(2, (Q, R), QUAD), \
10499 X(2, (D, I), DOUBLE), \
10500 X(2, (Q, I), QUAD), \
10501 X(3, (D, L, D), DOUBLE), \
10502 X(2, (D, Q), MIXED), \
10503 X(2, (Q, D), MIXED), \
10504 X(3, (D, Q, I), MIXED), \
10505 X(3, (Q, D, I), MIXED), \
10506 X(3, (Q, D, D), MIXED), \
10507 X(3, (D, Q, Q), MIXED), \
10508 X(3, (Q, Q, D), MIXED), \
10509 X(3, (Q, D, S), MIXED), \
10510 X(3, (D, Q, S), MIXED), \
10511 X(4, (D, D, D, I), DOUBLE), \
10512 X(4, (Q, Q, Q, I), QUAD), \
10513 X(2, (F, F), SINGLE), \
10514 X(3, (F, F, F), SINGLE), \
10515 X(2, (F, I), SINGLE), \
10516 X(2, (F, D), MIXED), \
10517 X(2, (D, F), MIXED), \
10518 X(3, (F, F, I), MIXED), \
10519 X(4, (R, R, F, F), SINGLE), \
10520 X(4, (F, F, R, R), SINGLE), \
10521 X(3, (D, R, R), DOUBLE), \
10522 X(3, (R, R, D), DOUBLE), \
10523 X(2, (S, R), SINGLE), \
10524 X(2, (R, S), SINGLE), \
10525 X(2, (F, R), SINGLE), \
10526 X(2, (R, F), SINGLE)
10527
10528#define S2(A,B) NS_##A##B
10529#define S3(A,B,C) NS_##A##B##C
10530#define S4(A,B,C,D) NS_##A##B##C##D
10531
10532#define X(N, L, C) S##N L
10533
10534enum neon_shape
10535{
10536 NEON_SHAPE_DEF,
10537 NS_NULL
10538};
10539
10540#undef X
10541#undef S2
10542#undef S3
10543#undef S4
10544
10545enum neon_shape_class
10546{
10547 SC_SINGLE,
10548 SC_DOUBLE,
10549 SC_QUAD,
10550 SC_MIXED
10551};
10552
10553#define X(N, L, C) SC_##C
10554
10555static enum neon_shape_class neon_shape_class[] =
10556{
10557 NEON_SHAPE_DEF
10558};
10559
10560#undef X
10561
10562enum neon_shape_el
10563{
10564 SE_F,
10565 SE_D,
10566 SE_Q,
10567 SE_I,
10568 SE_S,
10569 SE_R,
10570 SE_L
10571};
10572
10573/* Register widths of above. */
10574static unsigned neon_shape_el_size[] =
10575{
10576 32,
10577 64,
10578 128,
10579 0,
10580 32,
10581 32,
10582 0
10583};
10584
10585struct neon_shape_info
10586{
10587 unsigned els;
10588 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
10589};
10590
10591#define S2(A,B) { SE_##A, SE_##B }
10592#define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10593#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10594
10595#define X(N, L, C) { N, S##N L }
10596
10597static struct neon_shape_info neon_shape_tab[] =
10598{
10599 NEON_SHAPE_DEF
10600};
10601
10602#undef X
10603#undef S2
10604#undef S3
10605#undef S4
10606
10607/* Bit masks used in type checking given instructions.
10608 'N_EQK' means the type must be the same as (or based on in some way) the key
10609 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10610 set, various other bits can be set as well in order to modify the meaning of
10611 the type constraint. */
10612
10613enum neon_type_mask
10614{
10615 N_S8 = 0x000001,
10616 N_S16 = 0x000002,
10617 N_S32 = 0x000004,
10618 N_S64 = 0x000008,
10619 N_U8 = 0x000010,
10620 N_U16 = 0x000020,
10621 N_U32 = 0x000040,
10622 N_U64 = 0x000080,
10623 N_I8 = 0x000100,
10624 N_I16 = 0x000200,
10625 N_I32 = 0x000400,
10626 N_I64 = 0x000800,
10627 N_8 = 0x001000,
10628 N_16 = 0x002000,
10629 N_32 = 0x004000,
10630 N_64 = 0x008000,
10631 N_P8 = 0x010000,
10632 N_P16 = 0x020000,
10633 N_F32 = 0x040000,
10634 N_F64 = 0x080000,
10635 N_KEY = 0x100000, /* key element (main type specifier). */
10636 N_EQK = 0x200000, /* given operand has the same type & size as the key. */
10637 N_VFP = 0x400000, /* VFP mode: operand size must match register width. */
10638 N_DBL = 0x000001, /* if N_EQK, this operand is twice the size. */
10639 N_HLF = 0x000002, /* if N_EQK, this operand is half the size. */
10640 N_SGN = 0x000004, /* if N_EQK, this operand is forced to be signed. */
10641 N_UNS = 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10642 N_INT = 0x000010, /* if N_EQK, this operand is forced to be integer. */
10643 N_FLT = 0x000020, /* if N_EQK, this operand is forced to be float. */
10644 N_SIZ = 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10645 N_UTYP = 0,
10646 N_MAX_NONSPECIAL = N_F64
10647};
10648
10649#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10650
10651#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10652#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10653#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10654#define N_SUF_32 (N_SU_32 | N_F32)
10655#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10656#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10657
10658/* Pass this as the first type argument to neon_check_type to ignore types
10659 altogether. */
10660#define N_IGNORE_TYPE (N_KEY | N_EQK)
10661
10662/* Select a "shape" for the current instruction (describing register types or
10663 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10664 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10665 function of operand parsing, so this function doesn't need to be called.
10666 Shapes should be listed in order of decreasing length. */
10667
10668static enum neon_shape
10669neon_select_shape (enum neon_shape shape, ...)
10670{
10671 va_list ap;
10672 enum neon_shape first_shape = shape;
10673
10674 /* Fix missing optional operands. FIXME: we don't know at this point how
10675 many arguments we should have, so this makes the assumption that we have
10676 > 1. This is true of all current Neon opcodes, I think, but may not be
10677 true in the future. */
10678 if (!inst.operands[1].present)
10679 inst.operands[1] = inst.operands[0];
10680
10681 va_start (ap, shape);
10682
10683 for (; shape != NS_NULL; shape = va_arg (ap, int))
10684 {
10685 unsigned j;
10686 int matches = 1;
10687
10688 for (j = 0; j < neon_shape_tab[shape].els; j++)
10689 {
10690 if (!inst.operands[j].present)
10691 {
10692 matches = 0;
10693 break;
10694 }
10695
10696 switch (neon_shape_tab[shape].el[j])
10697 {
10698 case SE_F:
10699 if (!(inst.operands[j].isreg
10700 && inst.operands[j].isvec
10701 && inst.operands[j].issingle
10702 && !inst.operands[j].isquad))
10703 matches = 0;
10704 break;
10705
10706 case SE_D:
10707 if (!(inst.operands[j].isreg
10708 && inst.operands[j].isvec
10709 && !inst.operands[j].isquad
10710 && !inst.operands[j].issingle))
10711 matches = 0;
10712 break;
10713
10714 case SE_R:
10715 if (!(inst.operands[j].isreg
10716 && !inst.operands[j].isvec))
10717 matches = 0;
10718 break;
10719
10720 case SE_Q:
10721 if (!(inst.operands[j].isreg
10722 && inst.operands[j].isvec
10723 && inst.operands[j].isquad
10724 && !inst.operands[j].issingle))
10725 matches = 0;
10726 break;
10727
10728 case SE_I:
10729 if (!(!inst.operands[j].isreg
10730 && !inst.operands[j].isscalar))
10731 matches = 0;
10732 break;
10733
10734 case SE_S:
10735 if (!(!inst.operands[j].isreg
10736 && inst.operands[j].isscalar))
10737 matches = 0;
10738 break;
10739
10740 case SE_L:
10741 break;
10742 }
10743 }
10744 if (matches)
10745 break;
10746 }
10747
10748 va_end (ap);
10749
10750 if (shape == NS_NULL && first_shape != NS_NULL)
10751 first_error (_("invalid instruction shape"));
10752
10753 return shape;
10754}
10755
10756/* True if SHAPE is predominantly a quadword operation (most of the time, this
10757 means the Q bit should be set). */
10758
10759static int
10760neon_quad (enum neon_shape shape)
10761{
10762 return neon_shape_class[shape] == SC_QUAD;
10763}
10764
10765static void
10766neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
10767 unsigned *g_size)
10768{
10769 /* Allow modification to be made to types which are constrained to be
10770 based on the key element, based on bits set alongside N_EQK. */
10771 if ((typebits & N_EQK) != 0)
10772 {
10773 if ((typebits & N_HLF) != 0)
10774 *g_size /= 2;
10775 else if ((typebits & N_DBL) != 0)
10776 *g_size *= 2;
10777 if ((typebits & N_SGN) != 0)
10778 *g_type = NT_signed;
10779 else if ((typebits & N_UNS) != 0)
10780 *g_type = NT_unsigned;
10781 else if ((typebits & N_INT) != 0)
10782 *g_type = NT_integer;
10783 else if ((typebits & N_FLT) != 0)
10784 *g_type = NT_float;
10785 else if ((typebits & N_SIZ) != 0)
10786 *g_type = NT_untyped;
10787 }
10788}
10789
10790/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10791 operand type, i.e. the single type specified in a Neon instruction when it
10792 is the only one given. */
10793
10794static struct neon_type_el
10795neon_type_promote (struct neon_type_el *key, unsigned thisarg)
10796{
10797 struct neon_type_el dest = *key;
10798
10799 assert ((thisarg & N_EQK) != 0);
10800
10801 neon_modify_type_size (thisarg, &dest.type, &dest.size);
10802
10803 return dest;
10804}
10805
10806/* Convert Neon type and size into compact bitmask representation. */
10807
10808static enum neon_type_mask
10809type_chk_of_el_type (enum neon_el_type type, unsigned size)
10810{
10811 switch (type)
10812 {
10813 case NT_untyped:
10814 switch (size)
10815 {
10816 case 8: return N_8;
10817 case 16: return N_16;
10818 case 32: return N_32;
10819 case 64: return N_64;
10820 default: ;
10821 }
10822 break;
10823
10824 case NT_integer:
10825 switch (size)
10826 {
10827 case 8: return N_I8;
10828 case 16: return N_I16;
10829 case 32: return N_I32;
10830 case 64: return N_I64;
10831 default: ;
10832 }
10833 break;
10834
10835 case NT_float:
10836 switch (size)
10837 {
10838 case 32: return N_F32;
10839 case 64: return N_F64;
10840 default: ;
10841 }
10842 break;
10843
10844 case NT_poly:
10845 switch (size)
10846 {
10847 case 8: return N_P8;
10848 case 16: return N_P16;
10849 default: ;
10850 }
10851 break;
10852
10853 case NT_signed:
10854 switch (size)
10855 {
10856 case 8: return N_S8;
10857 case 16: return N_S16;
10858 case 32: return N_S32;
10859 case 64: return N_S64;
10860 default: ;
10861 }
10862 break;
10863
10864 case NT_unsigned:
10865 switch (size)
10866 {
10867 case 8: return N_U8;
10868 case 16: return N_U16;
10869 case 32: return N_U32;
10870 case 64: return N_U64;
10871 default: ;
10872 }
10873 break;
10874
10875 default: ;
10876 }
10877
10878 return N_UTYP;
10879}
10880
10881/* Convert compact Neon bitmask type representation to a type and size. Only
10882 handles the case where a single bit is set in the mask. */
10883
10884static int
10885el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
10886 enum neon_type_mask mask)
10887{
10888 if ((mask & N_EQK) != 0)
10889 return FAIL;
10890
10891 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
10892 *size = 8;
10893 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
10894 *size = 16;
10895 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
10896 *size = 32;
10897 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
10898 *size = 64;
10899 else
10900 return FAIL;
10901
10902 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
10903 *type = NT_signed;
10904 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
10905 *type = NT_unsigned;
10906 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
10907 *type = NT_integer;
10908 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
10909 *type = NT_untyped;
10910 else if ((mask & (N_P8 | N_P16)) != 0)
10911 *type = NT_poly;
10912 else if ((mask & (N_F32 | N_F64)) != 0)
10913 *type = NT_float;
10914 else
10915 return FAIL;
10916
10917 return SUCCESS;
10918}
10919
10920/* Modify a bitmask of allowed types. This is only needed for type
10921 relaxation. */
10922
10923static unsigned
10924modify_types_allowed (unsigned allowed, unsigned mods)
10925{
10926 unsigned size;
10927 enum neon_el_type type;
10928 unsigned destmask;
10929 int i;
10930
10931 destmask = 0;
10932
10933 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
10934 {
10935 if (el_type_of_type_chk (&type, &size, allowed & i) == SUCCESS)
10936 {
10937 neon_modify_type_size (mods, &type, &size);
10938 destmask |= type_chk_of_el_type (type, size);
10939 }
10940 }
10941
10942 return destmask;
10943}
10944
10945/* Check type and return type classification.
10946 The manual states (paraphrase): If one datatype is given, it indicates the
10947 type given in:
10948 - the second operand, if there is one
10949 - the operand, if there is no second operand
10950 - the result, if there are no operands.
10951 This isn't quite good enough though, so we use a concept of a "key" datatype
10952 which is set on a per-instruction basis, which is the one which matters when
10953 only one data type is written.
10954 Note: this function has side-effects (e.g. filling in missing operands). All
10955 Neon instructions should call it before performing bit encoding. */
10956
10957static struct neon_type_el
10958neon_check_type (unsigned els, enum neon_shape ns, ...)
10959{
10960 va_list ap;
10961 unsigned i, pass, key_el = 0;
10962 unsigned types[NEON_MAX_TYPE_ELS];
10963 enum neon_el_type k_type = NT_invtype;
10964 unsigned k_size = -1u;
10965 struct neon_type_el badtype = {NT_invtype, -1};
10966 unsigned key_allowed = 0;
10967
10968 /* Optional registers in Neon instructions are always (not) in operand 1.
10969 Fill in the missing operand here, if it was omitted. */
10970 if (els > 1 && !inst.operands[1].present)
10971 inst.operands[1] = inst.operands[0];
10972
10973 /* Suck up all the varargs. */
10974 va_start (ap, ns);
10975 for (i = 0; i < els; i++)
10976 {
10977 unsigned thisarg = va_arg (ap, unsigned);
10978 if (thisarg == N_IGNORE_TYPE)
10979 {
10980 va_end (ap);
10981 return badtype;
10982 }
10983 types[i] = thisarg;
10984 if ((thisarg & N_KEY) != 0)
10985 key_el = i;
10986 }
10987 va_end (ap);
10988
10989 if (inst.vectype.elems > 0)
10990 for (i = 0; i < els; i++)
10991 if (inst.operands[i].vectype.type != NT_invtype)
10992 {
10993 first_error (_("types specified in both the mnemonic and operands"));
10994 return badtype;
10995 }
10996
10997 /* Duplicate inst.vectype elements here as necessary.
10998 FIXME: No idea if this is exactly the same as the ARM assembler,
10999 particularly when an insn takes one register and one non-register
11000 operand. */
11001 if (inst.vectype.elems == 1 && els > 1)
11002 {
11003 unsigned j;
11004 inst.vectype.elems = els;
11005 inst.vectype.el[key_el] = inst.vectype.el[0];
11006 for (j = 0; j < els; j++)
11007 if (j != key_el)
11008 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
11009 types[j]);
11010 }
11011 else if (inst.vectype.elems == 0 && els > 0)
11012 {
11013 unsigned j;
11014 /* No types were given after the mnemonic, so look for types specified
11015 after each operand. We allow some flexibility here; as long as the
11016 "key" operand has a type, we can infer the others. */
11017 for (j = 0; j < els; j++)
11018 if (inst.operands[j].vectype.type != NT_invtype)
11019 inst.vectype.el[j] = inst.operands[j].vectype;
11020
11021 if (inst.operands[key_el].vectype.type != NT_invtype)
11022 {
11023 for (j = 0; j < els; j++)
11024 if (inst.operands[j].vectype.type == NT_invtype)
11025 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
11026 types[j]);
11027 }
11028 else
11029 {
11030 first_error (_("operand types can't be inferred"));
11031 return badtype;
11032 }
11033 }
11034 else if (inst.vectype.elems != els)
11035 {
11036 first_error (_("type specifier has the wrong number of parts"));
11037 return badtype;
11038 }
11039
11040 for (pass = 0; pass < 2; pass++)
11041 {
11042 for (i = 0; i < els; i++)
11043 {
11044 unsigned thisarg = types[i];
11045 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
11046 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
11047 enum neon_el_type g_type = inst.vectype.el[i].type;
11048 unsigned g_size = inst.vectype.el[i].size;
11049
11050 /* Decay more-specific signed & unsigned types to sign-insensitive
11051 integer types if sign-specific variants are unavailable. */
11052 if ((g_type == NT_signed || g_type == NT_unsigned)
11053 && (types_allowed & N_SU_ALL) == 0)
11054 g_type = NT_integer;
11055
11056 /* If only untyped args are allowed, decay any more specific types to
11057 them. Some instructions only care about signs for some element
11058 sizes, so handle that properly. */
11059 if ((g_size == 8 && (types_allowed & N_8) != 0)
11060 || (g_size == 16 && (types_allowed & N_16) != 0)
11061 || (g_size == 32 && (types_allowed & N_32) != 0)
11062 || (g_size == 64 && (types_allowed & N_64) != 0))
11063 g_type = NT_untyped;
11064
11065 if (pass == 0)
11066 {
11067 if ((thisarg & N_KEY) != 0)
11068 {
11069 k_type = g_type;
11070 k_size = g_size;
11071 key_allowed = thisarg & ~N_KEY;
11072 }
11073 }
11074 else
11075 {
11076 if ((thisarg & N_VFP) != 0)
11077 {
11078 enum neon_shape_el regshape = neon_shape_tab[ns].el[i];
11079 unsigned regwidth = neon_shape_el_size[regshape], match;
11080
11081 /* In VFP mode, operands must match register widths. If we
11082 have a key operand, use its width, else use the width of
11083 the current operand. */
11084 if (k_size != -1u)
11085 match = k_size;
11086 else
11087 match = g_size;
11088
11089 if (regwidth != match)
11090 {
11091 first_error (_("operand size must match register width"));
11092 return badtype;
11093 }
11094 }
11095
11096 if ((thisarg & N_EQK) == 0)
11097 {
11098 unsigned given_type = type_chk_of_el_type (g_type, g_size);
11099
11100 if ((given_type & types_allowed) == 0)
11101 {
11102 first_error (_("bad type in Neon instruction"));
11103 return badtype;
11104 }
11105 }
11106 else
11107 {
11108 enum neon_el_type mod_k_type = k_type;
11109 unsigned mod_k_size = k_size;
11110 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
11111 if (g_type != mod_k_type || g_size != mod_k_size)
11112 {
11113 first_error (_("inconsistent types in Neon instruction"));
11114 return badtype;
11115 }
11116 }
11117 }
11118 }
11119 }
11120
11121 return inst.vectype.el[key_el];
11122}
11123
11124/* Neon-style VFP instruction forwarding. */
11125
11126/* Thumb VFP instructions have 0xE in the condition field. */
11127
11128static void
11129do_vfp_cond_or_thumb (void)
11130{
11131 if (thumb_mode)
11132 inst.instruction |= 0xe0000000;
11133 else
11134 inst.instruction |= inst.cond << 28;
11135}
11136
11137/* Look up and encode a simple mnemonic, for use as a helper function for the
11138 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11139 etc. It is assumed that operand parsing has already been done, and that the
11140 operands are in the form expected by the given opcode (this isn't necessarily
11141 the same as the form in which they were parsed, hence some massaging must
11142 take place before this function is called).
11143 Checks current arch version against that in the looked-up opcode. */
11144
11145static void
11146do_vfp_nsyn_opcode (const char *opname)
11147{
11148 const struct asm_opcode *opcode;
11149
11150 opcode = hash_find (arm_ops_hsh, opname);
11151
11152 if (!opcode)
11153 abort ();
11154
11155 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
11156 thumb_mode ? *opcode->tvariant : *opcode->avariant),
11157 _(BAD_FPU));
11158
11159 if (thumb_mode)
11160 {
11161 inst.instruction = opcode->tvalue;
11162 opcode->tencode ();
11163 }
11164 else
11165 {
11166 inst.instruction = (inst.cond << 28) | opcode->avalue;
11167 opcode->aencode ();
11168 }
11169}
11170
11171static void
11172do_vfp_nsyn_add_sub (enum neon_shape rs)
11173{
11174 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
11175
11176 if (rs == NS_FFF)
11177 {
11178 if (is_add)
11179 do_vfp_nsyn_opcode ("fadds");
11180 else
11181 do_vfp_nsyn_opcode ("fsubs");
11182 }
11183 else
11184 {
11185 if (is_add)
11186 do_vfp_nsyn_opcode ("faddd");
11187 else
11188 do_vfp_nsyn_opcode ("fsubd");
11189 }
11190}
11191
11192/* Check operand types to see if this is a VFP instruction, and if so call
11193 PFN (). */
11194
11195static int
11196try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
11197{
11198 enum neon_shape rs;
11199 struct neon_type_el et;
11200
11201 switch (args)
11202 {
11203 case 2:
11204 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
11205 et = neon_check_type (2, rs,
11206 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11207 break;
11208
11209 case 3:
11210 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
11211 et = neon_check_type (3, rs,
11212 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11213 break;
11214
11215 default:
11216 abort ();
11217 }
11218
11219 if (et.type != NT_invtype)
11220 {
11221 pfn (rs);
11222 return SUCCESS;
11223 }
11224 else
11225 inst.error = NULL;
11226
11227 return FAIL;
11228}
11229
11230static void
11231do_vfp_nsyn_mla_mls (enum neon_shape rs)
11232{
11233 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
11234
11235 if (rs == NS_FFF)
11236 {
11237 if (is_mla)
11238 do_vfp_nsyn_opcode ("fmacs");
11239 else
11240 do_vfp_nsyn_opcode ("fmscs");
11241 }
11242 else
11243 {
11244 if (is_mla)
11245 do_vfp_nsyn_opcode ("fmacd");
11246 else
11247 do_vfp_nsyn_opcode ("fmscd");
11248 }
11249}
11250
11251static void
11252do_vfp_nsyn_mul (enum neon_shape rs)
11253{
11254 if (rs == NS_FFF)
11255 do_vfp_nsyn_opcode ("fmuls");
11256 else
11257 do_vfp_nsyn_opcode ("fmuld");
11258}
11259
11260static void
11261do_vfp_nsyn_abs_neg (enum neon_shape rs)
11262{
11263 int is_neg = (inst.instruction & 0x80) != 0;
11264 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
11265
11266 if (rs == NS_FF)
11267 {
11268 if (is_neg)
11269 do_vfp_nsyn_opcode ("fnegs");
11270 else
11271 do_vfp_nsyn_opcode ("fabss");
11272 }
11273 else
11274 {
11275 if (is_neg)
11276 do_vfp_nsyn_opcode ("fnegd");
11277 else
11278 do_vfp_nsyn_opcode ("fabsd");
11279 }
11280}
11281
11282/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11283 insns belong to Neon, and are handled elsewhere. */
11284
11285static void
11286do_vfp_nsyn_ldm_stm (int is_dbmode)
11287{
11288 int is_ldm = (inst.instruction & (1 << 20)) != 0;
11289 if (is_ldm)
11290 {
11291 if (is_dbmode)
11292 do_vfp_nsyn_opcode ("fldmdbs");
11293 else
11294 do_vfp_nsyn_opcode ("fldmias");
11295 }
11296 else
11297 {
11298 if (is_dbmode)
11299 do_vfp_nsyn_opcode ("fstmdbs");
11300 else
11301 do_vfp_nsyn_opcode ("fstmias");
11302 }
11303}
11304
11305static void
11306do_vfp_nsyn_sqrt (void)
11307{
11308 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
11309 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11310
11311 if (rs == NS_FF)
11312 do_vfp_nsyn_opcode ("fsqrts");
11313 else
11314 do_vfp_nsyn_opcode ("fsqrtd");
11315}
11316
11317static void
11318do_vfp_nsyn_div (void)
11319{
11320 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
11321 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
11322 N_F32 | N_F64 | N_KEY | N_VFP);
11323
11324 if (rs == NS_FFF)
11325 do_vfp_nsyn_opcode ("fdivs");
11326 else
11327 do_vfp_nsyn_opcode ("fdivd");
11328}
11329
11330static void
11331do_vfp_nsyn_nmul (void)
11332{
11333 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
11334 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
11335 N_F32 | N_F64 | N_KEY | N_VFP);
11336
11337 if (rs == NS_FFF)
11338 {
11339 inst.instruction = NEON_ENC_SINGLE (inst.instruction);
11340 do_vfp_sp_dyadic ();
11341 }
11342 else
11343 {
11344 inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
11345 do_vfp_dp_rd_rn_rm ();
11346 }
11347 do_vfp_cond_or_thumb ();
11348}
11349
11350static void
11351do_vfp_nsyn_cmp (void)
11352{
11353 if (inst.operands[1].isreg)
11354 {
11355 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
11356 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11357
11358 if (rs == NS_FF)
11359 {
11360 inst.instruction = NEON_ENC_SINGLE (inst.instruction);
11361 do_vfp_sp_monadic ();
11362 }
11363 else
11364 {
11365 inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
11366 do_vfp_dp_rd_rm ();
11367 }
11368 }
11369 else
11370 {
11371 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
11372 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
11373
11374 switch (inst.instruction & 0x0fffffff)
11375 {
11376 case N_MNEM_vcmp:
11377 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
11378 break;
11379 case N_MNEM_vcmpe:
11380 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
11381 break;
11382 default:
11383 abort ();
11384 }
11385
11386 if (rs == NS_FI)
11387 {
11388 inst.instruction = NEON_ENC_SINGLE (inst.instruction);
11389 do_vfp_sp_compare_z ();
11390 }
11391 else
11392 {
11393 inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
11394 do_vfp_dp_rd ();
11395 }
11396 }
11397 do_vfp_cond_or_thumb ();
11398}
11399
11400static void
11401nsyn_insert_sp (void)
11402{
11403 inst.operands[1] = inst.operands[0];
11404 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
11405 inst.operands[0].reg = 13;
11406 inst.operands[0].isreg = 1;
11407 inst.operands[0].writeback = 1;
11408 inst.operands[0].present = 1;
11409}
11410
11411static void
11412do_vfp_nsyn_push (void)
11413{
11414 nsyn_insert_sp ();
11415 if (inst.operands[1].issingle)
11416 do_vfp_nsyn_opcode ("fstmdbs");
11417 else
11418 do_vfp_nsyn_opcode ("fstmdbd");
11419}
11420
11421static void
11422do_vfp_nsyn_pop (void)
11423{
11424 nsyn_insert_sp ();
11425 if (inst.operands[1].issingle)
11426 do_vfp_nsyn_opcode ("fldmias");
11427 else
11428 do_vfp_nsyn_opcode ("fldmiad");
11429}
11430
11431/* Fix up Neon data-processing instructions, ORing in the correct bits for
11432 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11433
11434static unsigned
11435neon_dp_fixup (unsigned i)
11436{
11437 if (thumb_mode)
11438 {
11439 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11440 if (i & (1 << 24))
11441 i |= 1 << 28;
11442
11443 i &= ~(1 << 24);
11444
11445 i |= 0xef000000;
11446 }
11447 else
11448 i |= 0xf2000000;
11449
11450 return i;
11451}
11452
11453/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11454 (0, 1, 2, 3). */
11455
11456static unsigned
11457neon_logbits (unsigned x)
11458{
11459 return ffs (x) - 4;
11460}
11461
11462#define LOW4(R) ((R) & 0xf)
11463#define HI1(R) (((R) >> 4) & 1)
11464
11465/* Encode insns with bit pattern:
11466
11467 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11468 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11469
11470 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11471 different meaning for some instruction. */
11472
11473static void
11474neon_three_same (int isquad, int ubit, int size)
11475{
11476 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11477 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11478 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
11479 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
11480 inst.instruction |= LOW4 (inst.operands[2].reg);
11481 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
11482 inst.instruction |= (isquad != 0) << 6;
11483 inst.instruction |= (ubit != 0) << 24;
11484 if (size != -1)
11485 inst.instruction |= neon_logbits (size) << 20;
11486
11487 inst.instruction = neon_dp_fixup (inst.instruction);
11488}
11489
11490/* Encode instructions of the form:
11491
11492 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11493 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11494
11495 Don't write size if SIZE == -1. */
11496
11497static void
11498neon_two_same (int qbit, int ubit, int size)
11499{
11500 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11501 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11502 inst.instruction |= LOW4 (inst.operands[1].reg);
11503 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
11504 inst.instruction |= (qbit != 0) << 6;
11505 inst.instruction |= (ubit != 0) << 24;
11506
11507 if (size != -1)
11508 inst.instruction |= neon_logbits (size) << 18;
11509
11510 inst.instruction = neon_dp_fixup (inst.instruction);
11511}
11512
11513/* Neon instruction encoders, in approximate order of appearance. */
11514
11515static void
11516do_neon_dyadic_i_su (void)
11517{
11518 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11519 struct neon_type_el et = neon_check_type (3, rs,
11520 N_EQK, N_EQK, N_SU_32 | N_KEY);
11521 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11522}
11523
11524static void
11525do_neon_dyadic_i64_su (void)
11526{
11527 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11528 struct neon_type_el et = neon_check_type (3, rs,
11529 N_EQK, N_EQK, N_SU_ALL | N_KEY);
11530 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11531}
11532
11533static void
11534neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
11535 unsigned immbits)
11536{
11537 unsigned size = et.size >> 3;
11538 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11539 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11540 inst.instruction |= LOW4 (inst.operands[1].reg);
11541 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
11542 inst.instruction |= (isquad != 0) << 6;
11543 inst.instruction |= immbits << 16;
11544 inst.instruction |= (size >> 3) << 7;
11545 inst.instruction |= (size & 0x7) << 19;
11546 if (write_ubit)
11547 inst.instruction |= (uval != 0) << 24;
11548
11549 inst.instruction = neon_dp_fixup (inst.instruction);
11550}
11551
11552static void
11553do_neon_shl_imm (void)
11554{
11555 if (!inst.operands[2].isreg)
11556 {
11557 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
11558 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
11559 inst.instruction = NEON_ENC_IMMED (inst.instruction);
11560 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
11561 }
11562 else
11563 {
11564 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11565 struct neon_type_el et = neon_check_type (3, rs,
11566 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
11567 unsigned int tmp;
11568
11569 /* VSHL/VQSHL 3-register variants have syntax such as:
11570 vshl.xx Dd, Dm, Dn
11571 whereas other 3-register operations encoded by neon_three_same have
11572 syntax like:
11573 vadd.xx Dd, Dn, Dm
11574 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
11575 here. */
11576 tmp = inst.operands[2].reg;
11577 inst.operands[2].reg = inst.operands[1].reg;
11578 inst.operands[1].reg = tmp;
11579 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
11580 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11581 }
11582}
11583
11584static void
11585do_neon_qshl_imm (void)
11586{
11587 if (!inst.operands[2].isreg)
11588 {
11589 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
11590 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
11591
11592 inst.instruction = NEON_ENC_IMMED (inst.instruction);
11593 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
11594 inst.operands[2].imm);
11595 }
11596 else
11597 {
11598 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11599 struct neon_type_el et = neon_check_type (3, rs,
11600 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
11601 unsigned int tmp;
11602
11603 /* See note in do_neon_shl_imm. */
11604 tmp = inst.operands[2].reg;
11605 inst.operands[2].reg = inst.operands[1].reg;
11606 inst.operands[1].reg = tmp;
11607 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
11608 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11609 }
11610}
11611
11612static void
11613do_neon_rshl (void)
11614{
11615 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11616 struct neon_type_el et = neon_check_type (3, rs,
11617 N_EQK, N_EQK, N_SU_ALL | N_KEY);
11618 unsigned int tmp;
11619
11620 tmp = inst.operands[2].reg;
11621 inst.operands[2].reg = inst.operands[1].reg;
11622 inst.operands[1].reg = tmp;
11623 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11624}
11625
11626static int
11627neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
11628{
11629 /* Handle .I8 pseudo-instructions. */
11630 if (size == 8)
11631 {
11632 /* Unfortunately, this will make everything apart from zero out-of-range.
11633 FIXME is this the intended semantics? There doesn't seem much point in
11634 accepting .I8 if so. */
11635 immediate |= immediate << 8;
11636 size = 16;
11637 }
11638
11639 if (size >= 32)
11640 {
11641 if (immediate == (immediate & 0x000000ff))
11642 {
11643 *immbits = immediate;
11644 return 0x1;
11645 }
11646 else if (immediate == (immediate & 0x0000ff00))
11647 {
11648 *immbits = immediate >> 8;
11649 return 0x3;
11650 }
11651 else if (immediate == (immediate & 0x00ff0000))
11652 {
11653 *immbits = immediate >> 16;
11654 return 0x5;
11655 }
11656 else if (immediate == (immediate & 0xff000000))
11657 {
11658 *immbits = immediate >> 24;
11659 return 0x7;
11660 }
11661 if ((immediate & 0xffff) != (immediate >> 16))
11662 goto bad_immediate;
11663 immediate &= 0xffff;
11664 }
11665
11666 if (immediate == (immediate & 0x000000ff))
11667 {
11668 *immbits = immediate;
11669 return 0x9;
11670 }
11671 else if (immediate == (immediate & 0x0000ff00))
11672 {
11673 *immbits = immediate >> 8;
11674 return 0xb;
11675 }
11676
11677 bad_immediate:
11678 first_error (_("immediate value out of range"));
11679 return FAIL;
11680}
11681
11682/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11683 A, B, C, D. */
11684
11685static int
11686neon_bits_same_in_bytes (unsigned imm)
11687{
11688 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
11689 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
11690 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
11691 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
11692}
11693
11694/* For immediate of above form, return 0bABCD. */
11695
11696static unsigned
11697neon_squash_bits (unsigned imm)
11698{
11699 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
11700 | ((imm & 0x01000000) >> 21);
11701}
11702
11703/* Compress quarter-float representation to 0b...000 abcdefgh. */
11704
11705static unsigned
11706neon_qfloat_bits (unsigned imm)
11707{
11708 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
11709}
11710
11711/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11712 the instruction. *OP is passed as the initial value of the op field, and
11713 may be set to a different value depending on the constant (i.e.
11714 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11715 MVN). If the immediate looks like a repeated parttern then also
11716 try smaller element sizes. */
11717
11718static int
11719neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
11720 unsigned *immbits, int *op, int size,
11721 enum neon_el_type type)
11722{
11723 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
11724 float. */
11725 if (type == NT_float && !float_p)
11726 return FAIL;
11727
11728 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
11729 {
11730 if (size != 32 || *op == 1)
11731 return FAIL;
11732 *immbits = neon_qfloat_bits (immlo);
11733 return 0xf;
11734 }
11735
11736 if (size == 64)
11737 {
11738 if (neon_bits_same_in_bytes (immhi)
11739 && neon_bits_same_in_bytes (immlo))
11740 {
11741 if (*op == 1)
11742 return FAIL;
11743 *immbits = (neon_squash_bits (immhi) << 4)
11744 | neon_squash_bits (immlo);
11745 *op = 1;
11746 return 0xe;
11747 }
11748
11749 if (immhi != immlo)
11750 return FAIL;
11751 }
11752
11753 if (size >= 32)
11754 {
11755 if (immlo == (immlo & 0x000000ff))
11756 {
11757 *immbits = immlo;
11758 return 0x0;
11759 }
11760 else if (immlo == (immlo & 0x0000ff00))
11761 {
11762 *immbits = immlo >> 8;
11763 return 0x2;
11764 }
11765 else if (immlo == (immlo & 0x00ff0000))
11766 {
11767 *immbits = immlo >> 16;
11768 return 0x4;
11769 }
11770 else if (immlo == (immlo & 0xff000000))
11771 {
11772 *immbits = immlo >> 24;
11773 return 0x6;
11774 }
11775 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
11776 {
11777 *immbits = (immlo >> 8) & 0xff;
11778 return 0xc;
11779 }
11780 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
11781 {
11782 *immbits = (immlo >> 16) & 0xff;
11783 return 0xd;
11784 }
11785
11786 if ((immlo & 0xffff) != (immlo >> 16))
11787 return FAIL;
11788 immlo &= 0xffff;
11789 }
11790
11791 if (size >= 16)
11792 {
11793 if (immlo == (immlo & 0x000000ff))
11794 {
11795 *immbits = immlo;
11796 return 0x8;
11797 }
11798 else if (immlo == (immlo & 0x0000ff00))
11799 {
11800 *immbits = immlo >> 8;
11801 return 0xa;
11802 }
11803
11804 if ((immlo & 0xff) != (immlo >> 8))
11805 return FAIL;
11806 immlo &= 0xff;
11807 }
11808
11809 if (immlo == (immlo & 0x000000ff))
11810 {
11811 /* Don't allow MVN with 8-bit immediate. */
11812 if (*op == 1)
11813 return FAIL;
11814 *immbits = immlo;
11815 return 0xe;
11816 }
11817
11818 return FAIL;
11819}
11820
11821/* Write immediate bits [7:0] to the following locations:
11822
11823 |28/24|23 19|18 16|15 4|3 0|
11824 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11825
11826 This function is used by VMOV/VMVN/VORR/VBIC. */
11827
11828static void
11829neon_write_immbits (unsigned immbits)
11830{
11831 inst.instruction |= immbits & 0xf;
11832 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
11833 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
11834}
11835
11836/* Invert low-order SIZE bits of XHI:XLO. */
11837
11838static void
11839neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
11840{
11841 unsigned immlo = xlo ? *xlo : 0;
11842 unsigned immhi = xhi ? *xhi : 0;
11843
11844 switch (size)
11845 {
11846 case 8:
11847 immlo = (~immlo) & 0xff;
11848 break;
11849
11850 case 16:
11851 immlo = (~immlo) & 0xffff;
11852 break;
11853
11854 case 64:
11855 immhi = (~immhi) & 0xffffffff;
11856 /* fall through. */
11857
11858 case 32:
11859 immlo = (~immlo) & 0xffffffff;
11860 break;
11861
11862 default:
11863 abort ();
11864 }
11865
11866 if (xlo)
11867 *xlo = immlo;
11868
11869 if (xhi)
11870 *xhi = immhi;
11871}
11872
11873static void
11874do_neon_logic (void)
11875{
11876 if (inst.operands[2].present && inst.operands[2].isreg)
11877 {
11878 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11879 neon_check_type (3, rs, N_IGNORE_TYPE);
11880 /* U bit and size field were set as part of the bitmask. */
11881 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
11882 neon_three_same (neon_quad (rs), 0, -1);
11883 }
11884 else
11885 {
11886 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
11887 struct neon_type_el et = neon_check_type (2, rs,
11888 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
11889 enum neon_opc opcode = inst.instruction & 0x0fffffff;
11890 unsigned immbits;
11891 int cmode;
11892
11893 if (et.type == NT_invtype)
11894 return;
11895
11896 inst.instruction = NEON_ENC_IMMED (inst.instruction);
11897
11898 immbits = inst.operands[1].imm;
11899 if (et.size == 64)
11900 {
11901 /* .i64 is a pseudo-op, so the immediate must be a repeating
11902 pattern. */
11903 if (immbits != (inst.operands[1].regisimm ?
11904 inst.operands[1].reg : 0))
11905 {
11906 /* Set immbits to an invalid constant. */
11907 immbits = 0xdeadbeef;
11908 }
11909 }
11910
11911 switch (opcode)
11912 {
11913 case N_MNEM_vbic:
11914 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
11915 break;
11916
11917 case N_MNEM_vorr:
11918 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
11919 break;
11920
11921 case N_MNEM_vand:
11922 /* Pseudo-instruction for VBIC. */
11923 neon_invert_size (&immbits, 0, et.size);
11924 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
11925 break;
11926
11927 case N_MNEM_vorn:
11928 /* Pseudo-instruction for VORR. */
11929 neon_invert_size (&immbits, 0, et.size);
11930 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
11931 break;
11932
11933 default:
11934 abort ();
11935 }
11936
11937 if (cmode == FAIL)
11938 return;
11939
11940 inst.instruction |= neon_quad (rs) << 6;
11941 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11942 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11943 inst.instruction |= cmode << 8;
11944 neon_write_immbits (immbits);
11945
11946 inst.instruction = neon_dp_fixup (inst.instruction);
11947 }
11948}
11949
11950static void
11951do_neon_bitfield (void)
11952{
11953 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11954 neon_check_type (3, rs, N_IGNORE_TYPE);
11955 neon_three_same (neon_quad (rs), 0, -1);
11956}
11957
11958static void
11959neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
11960 unsigned destbits)
11961{
11962 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11963 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
11964 types | N_KEY);
11965 if (et.type == NT_float)
11966 {
11967 inst.instruction = NEON_ENC_FLOAT (inst.instruction);
11968 neon_three_same (neon_quad (rs), 0, -1);
11969 }
11970 else
11971 {
11972 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
11973 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
11974 }
11975}
11976
11977static void
11978do_neon_dyadic_if_su (void)
11979{
11980 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
11981}
11982
11983static void
11984do_neon_dyadic_if_su_d (void)
11985{
11986 /* This version only allow D registers, but that constraint is enforced during
11987 operand parsing so we don't need to do anything extra here. */
11988 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
11989}
11990
11991static void
11992do_neon_dyadic_if_i_d (void)
11993{
11994 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11995 affected if we specify unsigned args. */
11996 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
11997}
11998
11999enum vfp_or_neon_is_neon_bits
12000{
12001 NEON_CHECK_CC = 1,
12002 NEON_CHECK_ARCH = 2
12003};
12004
12005/* Call this function if an instruction which may have belonged to the VFP or
12006 Neon instruction sets, but turned out to be a Neon instruction (due to the
12007 operand types involved, etc.). We have to check and/or fix-up a couple of
12008 things:
12009
12010 - Make sure the user hasn't attempted to make a Neon instruction
12011 conditional.
12012 - Alter the value in the condition code field if necessary.
12013 - Make sure that the arch supports Neon instructions.
12014
12015 Which of these operations take place depends on bits from enum
12016 vfp_or_neon_is_neon_bits.
12017
12018 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12019 current instruction's condition is COND_ALWAYS, the condition field is
12020 changed to inst.uncond_value. This is necessary because instructions shared
12021 between VFP and Neon may be conditional for the VFP variants only, and the
12022 unconditional Neon version must have, e.g., 0xF in the condition field. */
12023
12024static int
12025vfp_or_neon_is_neon (unsigned check)
12026{
12027 /* Conditions are always legal in Thumb mode (IT blocks). */
12028 if (!thumb_mode && (check & NEON_CHECK_CC))
12029 {
12030 if (inst.cond != COND_ALWAYS)
12031 {
12032 first_error (_(BAD_COND));
12033 return FAIL;
12034 }
12035 if (inst.uncond_value != -1)
12036 inst.instruction |= inst.uncond_value << 28;
12037 }
12038
12039 if ((check & NEON_CHECK_ARCH)
12040 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
12041 {
12042 first_error (_(BAD_FPU));
12043 return FAIL;
12044 }
12045
12046 return SUCCESS;
12047}
12048
12049static void
12050do_neon_addsub_if_i (void)
12051{
12052 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
12053 return;
12054
12055 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12056 return;
12057
12058 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12059 affected if we specify unsigned args. */
12060 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
12061}
12062
12063/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12064 result to be:
12065 V<op> A,B (A is operand 0, B is operand 2)
12066 to mean:
12067 V<op> A,B,A
12068 not:
12069 V<op> A,B,B
12070 so handle that case specially. */
12071
12072static void
12073neon_exchange_operands (void)
12074{
12075 void *scratch = alloca (sizeof (inst.operands[0]));
12076 if (inst.operands[1].present)
12077 {
12078 /* Swap operands[1] and operands[2]. */
12079 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
12080 inst.operands[1] = inst.operands[2];
12081 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
12082 }
12083 else
12084 {
12085 inst.operands[1] = inst.operands[2];
12086 inst.operands[2] = inst.operands[0];
12087 }
12088}
12089
12090static void
12091neon_compare (unsigned regtypes, unsigned immtypes, int invert)
12092{
12093 if (inst.operands[2].isreg)
12094 {
12095 if (invert)
12096 neon_exchange_operands ();
12097 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
12098 }
12099 else
12100 {
12101 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12102 struct neon_type_el et = neon_check_type (2, rs,
12103 N_EQK | N_SIZ, immtypes | N_KEY);
12104
12105 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12106 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12107 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12108 inst.instruction |= LOW4 (inst.operands[1].reg);
12109 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12110 inst.instruction |= neon_quad (rs) << 6;
12111 inst.instruction |= (et.type == NT_float) << 10;
12112 inst.instruction |= neon_logbits (et.size) << 18;
12113
12114 inst.instruction = neon_dp_fixup (inst.instruction);
12115 }
12116}
12117
12118static void
12119do_neon_cmp (void)
12120{
12121 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
12122}
12123
12124static void
12125do_neon_cmp_inv (void)
12126{
12127 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
12128}
12129
12130static void
12131do_neon_ceq (void)
12132{
12133 neon_compare (N_IF_32, N_IF_32, FALSE);
12134}
12135
12136/* For multiply instructions, we have the possibility of 16-bit or 32-bit
12137 scalars, which are encoded in 5 bits, M : Rm.
12138 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12139 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12140 index in M. */
12141
12142static unsigned
12143neon_scalar_for_mul (unsigned scalar, unsigned elsize)
12144{
12145 unsigned regno = NEON_SCALAR_REG (scalar);
12146 unsigned elno = NEON_SCALAR_INDEX (scalar);
12147
12148 switch (elsize)
12149 {
12150 case 16:
12151 if (regno > 7 || elno > 3)
12152 goto bad_scalar;
12153 return regno | (elno << 3);
12154
12155 case 32:
12156 if (regno > 15 || elno > 1)
12157 goto bad_scalar;
12158 return regno | (elno << 4);
12159
12160 default:
12161 bad_scalar:
12162 first_error (_("scalar out of range for multiply instruction"));
12163 }
12164
12165 return 0;
12166}
12167
12168/* Encode multiply / multiply-accumulate scalar instructions. */
12169
12170static void
12171neon_mul_mac (struct neon_type_el et, int ubit)
12172{
12173 unsigned scalar;
12174
12175 /* Give a more helpful error message if we have an invalid type. */
12176 if (et.type == NT_invtype)
12177 return;
12178
12179 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
12180 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12181 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12182 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12183 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12184 inst.instruction |= LOW4 (scalar);
12185 inst.instruction |= HI1 (scalar) << 5;
12186 inst.instruction |= (et.type == NT_float) << 8;
12187 inst.instruction |= neon_logbits (et.size) << 20;
12188 inst.instruction |= (ubit != 0) << 24;
12189
12190 inst.instruction = neon_dp_fixup (inst.instruction);
12191}
12192
12193static void
12194do_neon_mac_maybe_scalar (void)
12195{
12196 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
12197 return;
12198
12199 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12200 return;
12201
12202 if (inst.operands[2].isscalar)
12203 {
12204 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
12205 struct neon_type_el et = neon_check_type (3, rs,
12206 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
12207 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
12208 neon_mul_mac (et, neon_quad (rs));
12209 }
12210 else
12211 {
12212 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12213 affected if we specify unsigned args. */
12214 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
12215 }
12216}
12217
12218static void
12219do_neon_tst (void)
12220{
12221 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12222 struct neon_type_el et = neon_check_type (3, rs,
12223 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
12224 neon_three_same (neon_quad (rs), 0, et.size);
12225}
12226
12227/* VMUL with 3 registers allows the P8 type. The scalar version supports the
12228 same types as the MAC equivalents. The polynomial type for this instruction
12229 is encoded the same as the integer type. */
12230
12231static void
12232do_neon_mul (void)
12233{
12234 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
12235 return;
12236
12237 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12238 return;
12239
12240 if (inst.operands[2].isscalar)
12241 do_neon_mac_maybe_scalar ();
12242 else
12243 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
12244}
12245
12246static void
12247do_neon_qdmulh (void)
12248{
12249 if (inst.operands[2].isscalar)
12250 {
12251 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
12252 struct neon_type_el et = neon_check_type (3, rs,
12253 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
12254 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
12255 neon_mul_mac (et, neon_quad (rs));
12256 }
12257 else
12258 {
12259 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12260 struct neon_type_el et = neon_check_type (3, rs,
12261 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
12262 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12263 /* The U bit (rounding) comes from bit mask. */
12264 neon_three_same (neon_quad (rs), 0, et.size);
12265 }
12266}
12267
12268static void
12269do_neon_fcmp_absolute (void)
12270{
12271 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12272 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
12273 /* Size field comes from bit mask. */
12274 neon_three_same (neon_quad (rs), 1, -1);
12275}
12276
12277static void
12278do_neon_fcmp_absolute_inv (void)
12279{
12280 neon_exchange_operands ();
12281 do_neon_fcmp_absolute ();
12282}
12283
12284static void
12285do_neon_step (void)
12286{
12287 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12288 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
12289 neon_three_same (neon_quad (rs), 0, -1);
12290}
12291
12292static void
12293do_neon_abs_neg (void)
12294{
12295 enum neon_shape rs;
12296 struct neon_type_el et;
12297
12298 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
12299 return;
12300
12301 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12302 return;
12303
12304 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
12305 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
12306
12307 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12308 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12309 inst.instruction |= LOW4 (inst.operands[1].reg);
12310 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12311 inst.instruction |= neon_quad (rs) << 6;
12312 inst.instruction |= (et.type == NT_float) << 10;
12313 inst.instruction |= neon_logbits (et.size) << 18;
12314
12315 inst.instruction = neon_dp_fixup (inst.instruction);
12316}
12317
12318static void
12319do_neon_sli (void)
12320{
12321 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12322 struct neon_type_el et = neon_check_type (2, rs,
12323 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
12324 int imm = inst.operands[2].imm;
12325 constraint (imm < 0 || (unsigned)imm >= et.size,
12326 _("immediate out of range for insert"));
12327 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
12328}
12329
12330static void
12331do_neon_sri (void)
12332{
12333 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12334 struct neon_type_el et = neon_check_type (2, rs,
12335 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
12336 int imm = inst.operands[2].imm;
12337 constraint (imm < 1 || (unsigned)imm > et.size,
12338 _("immediate out of range for insert"));
12339 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
12340}
12341
12342static void
12343do_neon_qshlu_imm (void)
12344{
12345 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12346 struct neon_type_el et = neon_check_type (2, rs,
12347 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
12348 int imm = inst.operands[2].imm;
12349 constraint (imm < 0 || (unsigned)imm >= et.size,
12350 _("immediate out of range for shift"));
12351 /* Only encodes the 'U present' variant of the instruction.
12352 In this case, signed types have OP (bit 8) set to 0.
12353 Unsigned types have OP set to 1. */
12354 inst.instruction |= (et.type == NT_unsigned) << 8;
12355 /* The rest of the bits are the same as other immediate shifts. */
12356 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
12357}
12358
12359static void
12360do_neon_qmovn (void)
12361{
12362 struct neon_type_el et = neon_check_type (2, NS_DQ,
12363 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
12364 /* Saturating move where operands can be signed or unsigned, and the
12365 destination has the same signedness. */
12366 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12367 if (et.type == NT_unsigned)
12368 inst.instruction |= 0xc0;
12369 else
12370 inst.instruction |= 0x80;
12371 neon_two_same (0, 1, et.size / 2);
12372}
12373
12374static void
12375do_neon_qmovun (void)
12376{
12377 struct neon_type_el et = neon_check_type (2, NS_DQ,
12378 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
12379 /* Saturating move with unsigned results. Operands must be signed. */
12380 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12381 neon_two_same (0, 1, et.size / 2);
12382}
12383
12384static void
12385do_neon_rshift_sat_narrow (void)
12386{
12387 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12388 or unsigned. If operands are unsigned, results must also be unsigned. */
12389 struct neon_type_el et = neon_check_type (2, NS_DQI,
12390 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
12391 int imm = inst.operands[2].imm;
12392 /* This gets the bounds check, size encoding and immediate bits calculation
12393 right. */
12394 et.size /= 2;
12395
12396 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12397 VQMOVN.I<size> <Dd>, <Qm>. */
12398 if (imm == 0)
12399 {
12400 inst.operands[2].present = 0;
12401 inst.instruction = N_MNEM_vqmovn;
12402 do_neon_qmovn ();
12403 return;
12404 }
12405
12406 constraint (imm < 1 || (unsigned)imm > et.size,
12407 _("immediate out of range"));
12408 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
12409}
12410
12411static void
12412do_neon_rshift_sat_narrow_u (void)
12413{
12414 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12415 or unsigned. If operands are unsigned, results must also be unsigned. */
12416 struct neon_type_el et = neon_check_type (2, NS_DQI,
12417 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
12418 int imm = inst.operands[2].imm;
12419 /* This gets the bounds check, size encoding and immediate bits calculation
12420 right. */
12421 et.size /= 2;
12422
12423 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12424 VQMOVUN.I<size> <Dd>, <Qm>. */
12425 if (imm == 0)
12426 {
12427 inst.operands[2].present = 0;
12428 inst.instruction = N_MNEM_vqmovun;
12429 do_neon_qmovun ();
12430 return;
12431 }
12432
12433 constraint (imm < 1 || (unsigned)imm > et.size,
12434 _("immediate out of range"));
12435 /* FIXME: The manual is kind of unclear about what value U should have in
12436 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12437 must be 1. */
12438 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
12439}
12440
12441static void
12442do_neon_movn (void)
12443{
12444 struct neon_type_el et = neon_check_type (2, NS_DQ,
12445 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
12446 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12447 neon_two_same (0, 1, et.size / 2);
12448}
12449
12450static void
12451do_neon_rshift_narrow (void)
12452{
12453 struct neon_type_el et = neon_check_type (2, NS_DQI,
12454 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
12455 int imm = inst.operands[2].imm;
12456 /* This gets the bounds check, size encoding and immediate bits calculation
12457 right. */
12458 et.size /= 2;
12459
12460 /* If immediate is zero then we are a pseudo-instruction for
12461 VMOVN.I<size> <Dd>, <Qm> */
12462 if (imm == 0)
12463 {
12464 inst.operands[2].present = 0;
12465 inst.instruction = N_MNEM_vmovn;
12466 do_neon_movn ();
12467 return;
12468 }
12469
12470 constraint (imm < 1 || (unsigned)imm > et.size,
12471 _("immediate out of range for narrowing operation"));
12472 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
12473}
12474
12475static void
12476do_neon_shll (void)
12477{
12478 /* FIXME: Type checking when lengthening. */
12479 struct neon_type_el et = neon_check_type (2, NS_QDI,
12480 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
12481 unsigned imm = inst.operands[2].imm;
12482
12483 if (imm == et.size)
12484 {
12485 /* Maximum shift variant. */
12486 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12487 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12488 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12489 inst.instruction |= LOW4 (inst.operands[1].reg);
12490 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12491 inst.instruction |= neon_logbits (et.size) << 18;
12492
12493 inst.instruction = neon_dp_fixup (inst.instruction);
12494 }
12495 else
12496 {
12497 /* A more-specific type check for non-max versions. */
12498 et = neon_check_type (2, NS_QDI,
12499 N_EQK | N_DBL, N_SU_32 | N_KEY);
12500 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12501 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
12502 }
12503}
12504
12505/* Check the various types for the VCVT instruction, and return which version
12506 the current instruction is. */
12507
12508static int
12509neon_cvt_flavour (enum neon_shape rs)
12510{
12511#define CVT_VAR(C,X,Y) \
12512 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12513 if (et.type != NT_invtype) \
12514 { \
12515 inst.error = NULL; \
12516 return (C); \
12517 }
12518 struct neon_type_el et;
12519 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
12520 || rs == NS_FF) ? N_VFP : 0;
12521 /* The instruction versions which take an immediate take one register
12522 argument, which is extended to the width of the full register. Thus the
12523 "source" and "destination" registers must have the same width. Hack that
12524 here by making the size equal to the key (wider, in this case) operand. */
12525 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
12526
12527 CVT_VAR (0, N_S32, N_F32);
12528 CVT_VAR (1, N_U32, N_F32);
12529 CVT_VAR (2, N_F32, N_S32);
12530 CVT_VAR (3, N_F32, N_U32);
12531
12532 whole_reg = N_VFP;
12533
12534 /* VFP instructions. */
12535 CVT_VAR (4, N_F32, N_F64);
12536 CVT_VAR (5, N_F64, N_F32);
12537 CVT_VAR (6, N_S32, N_F64 | key);
12538 CVT_VAR (7, N_U32, N_F64 | key);
12539 CVT_VAR (8, N_F64 | key, N_S32);
12540 CVT_VAR (9, N_F64 | key, N_U32);
12541 /* VFP instructions with bitshift. */
12542 CVT_VAR (10, N_F32 | key, N_S16);
12543 CVT_VAR (11, N_F32 | key, N_U16);
12544 CVT_VAR (12, N_F64 | key, N_S16);
12545 CVT_VAR (13, N_F64 | key, N_U16);
12546 CVT_VAR (14, N_S16, N_F32 | key);
12547 CVT_VAR (15, N_U16, N_F32 | key);
12548 CVT_VAR (16, N_S16, N_F64 | key);
12549 CVT_VAR (17, N_U16, N_F64 | key);
12550
12551 return -1;
12552#undef CVT_VAR
12553}
12554
12555/* Neon-syntax VFP conversions. */
12556
12557static void
12558do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
12559{
12560 const char *opname = 0;
12561
12562 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
12563 {
12564 /* Conversions with immediate bitshift. */
12565 const char *enc[] =
12566 {
12567 "ftosls",
12568 "ftouls",
12569 "fsltos",
12570 "fultos",
12571 NULL,
12572 NULL,
12573 "ftosld",
12574 "ftould",
12575 "fsltod",
12576 "fultod",
12577 "fshtos",
12578 "fuhtos",
12579 "fshtod",
12580 "fuhtod",
12581 "ftoshs",
12582 "ftouhs",
12583 "ftoshd",
12584 "ftouhd"
12585 };
12586
12587 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
12588 {
12589 opname = enc[flavour];
12590 constraint (inst.operands[0].reg != inst.operands[1].reg,
12591 _("operands 0 and 1 must be the same register"));
12592 inst.operands[1] = inst.operands[2];
12593 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
12594 }
12595 }
12596 else
12597 {
12598 /* Conversions without bitshift. */
12599 const char *enc[] =
12600 {
12601 "ftosis",
12602 "ftouis",
12603 "fsitos",
12604 "fuitos",
12605 "fcvtsd",
12606 "fcvtds",
12607 "ftosid",
12608 "ftouid",
12609 "fsitod",
12610 "fuitod"
12611 };
12612
12613 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
12614 opname = enc[flavour];
12615 }
12616
12617 if (opname)
12618 do_vfp_nsyn_opcode (opname);
12619}
12620
12621static void
12622do_vfp_nsyn_cvtz (void)
12623{
12624 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
12625 int flavour = neon_cvt_flavour (rs);
12626 const char *enc[] =
12627 {
12628 "ftosizs",
12629 "ftouizs",
12630 NULL,
12631 NULL,
12632 NULL,
12633 NULL,
12634 "ftosizd",
12635 "ftouizd"
12636 };
12637
12638 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
12639 do_vfp_nsyn_opcode (enc[flavour]);
12640}
12641
12642static void
12643do_neon_cvt (void)
12644{
12645 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
12646 NS_FD, NS_DF, NS_FF, NS_NULL);
12647 int flavour = neon_cvt_flavour (rs);
12648
12649 /* VFP rather than Neon conversions. */
12650 if (flavour >= 4)
12651 {
12652 do_vfp_nsyn_cvt (rs, flavour);
12653 return;
12654 }
12655
12656 switch (rs)
12657 {
12658 case NS_DDI:
12659 case NS_QQI:
12660 {
12661 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12662 return;
12663
12664 /* Fixed-point conversion with #0 immediate is encoded as an
12665 integer conversion. */
12666 if (inst.operands[2].present && inst.operands[2].imm == 0)
12667 goto int_encode;
12668 unsigned immbits = 32 - inst.operands[2].imm;
12669 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12670 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12671 if (flavour != -1)
12672 inst.instruction |= enctab[flavour];
12673 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12674 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12675 inst.instruction |= LOW4 (inst.operands[1].reg);
12676 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12677 inst.instruction |= neon_quad (rs) << 6;
12678 inst.instruction |= 1 << 21;
12679 inst.instruction |= immbits << 16;
12680
12681 inst.instruction = neon_dp_fixup (inst.instruction);
12682 }
12683 break;
12684
12685 case NS_DD:
12686 case NS_QQ:
12687 int_encode:
12688 {
12689 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
12690
12691 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12692
12693 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12694 return;
12695
12696 if (flavour != -1)
12697 inst.instruction |= enctab[flavour];
12698
12699 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12700 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12701 inst.instruction |= LOW4 (inst.operands[1].reg);
12702 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12703 inst.instruction |= neon_quad (rs) << 6;
12704 inst.instruction |= 2 << 18;
12705
12706 inst.instruction = neon_dp_fixup (inst.instruction);
12707 }
12708 break;
12709
12710 default:
12711 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12712 do_vfp_nsyn_cvt (rs, flavour);
12713 }
12714}
12715
12716static void
12717neon_move_immediate (void)
12718{
12719 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
12720 struct neon_type_el et = neon_check_type (2, rs,
12721 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
12722 unsigned immlo, immhi = 0, immbits;
12723 int op, cmode, float_p;
12724
12725 constraint (et.type == NT_invtype,
12726 _("operand size must be specified for immediate VMOV"));
12727
12728 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12729 op = (inst.instruction & (1 << 5)) != 0;
12730
12731 immlo = inst.operands[1].imm;
12732 if (inst.operands[1].regisimm)
12733 immhi = inst.operands[1].reg;
12734
12735 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
12736 _("immediate has bits set outside the operand size"));
12737
12738 float_p = inst.operands[1].immisfloat;
12739
12740 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
12741 et.size, et.type)) == FAIL)
12742 {
12743 /* Invert relevant bits only. */
12744 neon_invert_size (&immlo, &immhi, et.size);
12745 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12746 with one or the other; those cases are caught by
12747 neon_cmode_for_move_imm. */
12748 op = !op;
12749 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
12750 &op, et.size, et.type)) == FAIL)
12751 {
12752 first_error (_("immediate out of range"));
12753 return;
12754 }
12755 }
12756
12757 inst.instruction &= ~(1 << 5);
12758 inst.instruction |= op << 5;
12759
12760 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12761 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12762 inst.instruction |= neon_quad (rs) << 6;
12763 inst.instruction |= cmode << 8;
12764
12765 neon_write_immbits (immbits);
12766}
12767
12768static void
12769do_neon_mvn (void)
12770{
12771 if (inst.operands[1].isreg)
12772 {
12773 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
12774
12775 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12776 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12777 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12778 inst.instruction |= LOW4 (inst.operands[1].reg);
12779 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12780 inst.instruction |= neon_quad (rs) << 6;
12781 }
12782 else
12783 {
12784 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12785 neon_move_immediate ();
12786 }
12787
12788 inst.instruction = neon_dp_fixup (inst.instruction);
12789}
12790
12791/* Encode instructions of form:
12792
12793 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12794 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm |
12795
12796*/
12797
12798static void
12799neon_mixed_length (struct neon_type_el et, unsigned size)
12800{
12801 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12802 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12803 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12804 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12805 inst.instruction |= LOW4 (inst.operands[2].reg);
12806 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
12807 inst.instruction |= (et.type == NT_unsigned) << 24;
12808 inst.instruction |= neon_logbits (size) << 20;
12809
12810 inst.instruction = neon_dp_fixup (inst.instruction);
12811}
12812
12813static void
12814do_neon_dyadic_long (void)
12815{
12816 /* FIXME: Type checking for lengthening op. */
12817 struct neon_type_el et = neon_check_type (3, NS_QDD,
12818 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
12819 neon_mixed_length (et, et.size);
12820}
12821
12822static void
12823do_neon_abal (void)
12824{
12825 struct neon_type_el et = neon_check_type (3, NS_QDD,
12826 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
12827 neon_mixed_length (et, et.size);
12828}
12829
12830static void
12831neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
12832{
12833 if (inst.operands[2].isscalar)
12834 {
12835 struct neon_type_el et = neon_check_type (3, NS_QDS,
12836 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
12837 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
12838 neon_mul_mac (et, et.type == NT_unsigned);
12839 }
12840 else
12841 {
12842 struct neon_type_el et = neon_check_type (3, NS_QDD,
12843 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
12844 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12845 neon_mixed_length (et, et.size);
12846 }
12847}
12848
12849static void
12850do_neon_mac_maybe_scalar_long (void)
12851{
12852 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
12853}
12854
12855static void
12856do_neon_dyadic_wide (void)
12857{
12858 struct neon_type_el et = neon_check_type (3, NS_QQD,
12859 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
12860 neon_mixed_length (et, et.size);
12861}
12862
12863static void
12864do_neon_dyadic_narrow (void)
12865{
12866 struct neon_type_el et = neon_check_type (3, NS_QDD,
12867 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
12868 /* Operand sign is unimportant, and the U bit is part of the opcode,
12869 so force the operand type to integer. */
12870 et.type = NT_integer;
12871 neon_mixed_length (et, et.size / 2);
12872}
12873
12874static void
12875do_neon_mul_sat_scalar_long (void)
12876{
12877 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
12878}
12879
12880static void
12881do_neon_vmull (void)
12882{
12883 if (inst.operands[2].isscalar)
12884 do_neon_mac_maybe_scalar_long ();
12885 else
12886 {
12887 struct neon_type_el et = neon_check_type (3, NS_QDD,
12888 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
12889 if (et.type == NT_poly)
12890 inst.instruction = NEON_ENC_POLY (inst.instruction);
12891 else
12892 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12893 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12894 zero. Should be OK as-is. */
12895 neon_mixed_length (et, et.size);
12896 }
12897}
12898
12899static void
12900do_neon_ext (void)
12901{
12902 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
12903 struct neon_type_el et = neon_check_type (3, rs,
12904 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
12905 unsigned imm = (inst.operands[3].imm * et.size) / 8;
12906 constraint (imm >= (neon_quad (rs) ? 16 : 8), _("shift out of range"));
12907 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12908 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12909 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12910 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12911 inst.instruction |= LOW4 (inst.operands[2].reg);
12912 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
12913 inst.instruction |= neon_quad (rs) << 6;
12914 inst.instruction |= imm << 8;
12915
12916 inst.instruction = neon_dp_fixup (inst.instruction);
12917}
12918
12919static void
12920do_neon_rev (void)
12921{
12922 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
12923 struct neon_type_el et = neon_check_type (2, rs,
12924 N_EQK, N_8 | N_16 | N_32 | N_KEY);
12925 unsigned op = (inst.instruction >> 7) & 3;
12926 /* N (width of reversed regions) is encoded as part of the bitmask. We
12927 extract it here to check the elements to be reversed are smaller.
12928 Otherwise we'd get a reserved instruction. */
12929 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
12930 assert (elsize != 0);
12931 constraint (et.size >= elsize,
12932 _("elements must be smaller than reversal region"));
12933 neon_two_same (neon_quad (rs), 1, et.size);
12934}
12935
12936static void
12937do_neon_dup (void)
12938{
12939 if (inst.operands[1].isscalar)
12940 {
12941 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
12942 struct neon_type_el et = neon_check_type (2, rs,
12943 N_EQK, N_8 | N_16 | N_32 | N_KEY);
12944 unsigned sizebits = et.size >> 3;
12945 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
12946 int logsize = neon_logbits (et.size);
12947 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
12948
12949 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
12950 return;
12951
12952 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
12953 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12954 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12955 inst.instruction |= LOW4 (dm);
12956 inst.instruction |= HI1 (dm) << 5;
12957 inst.instruction |= neon_quad (rs) << 6;
12958 inst.instruction |= x << 17;
12959 inst.instruction |= sizebits << 16;
12960
12961 inst.instruction = neon_dp_fixup (inst.instruction);
12962 }
12963 else
12964 {
12965 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
12966 struct neon_type_el et = neon_check_type (2, rs,
12967 N_8 | N_16 | N_32 | N_KEY, N_EQK);
12968 /* Duplicate ARM register to lanes of vector. */
12969 inst.instruction = NEON_ENC_ARMREG (inst.instruction);
12970 switch (et.size)
12971 {
12972 case 8: inst.instruction |= 0x400000; break;
12973 case 16: inst.instruction |= 0x000020; break;
12974 case 32: inst.instruction |= 0x000000; break;
12975 default: break;
12976 }
12977 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
12978 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
12979 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
12980 inst.instruction |= neon_quad (rs) << 21;
12981 /* The encoding for this instruction is identical for the ARM and Thumb
12982 variants, except for the condition field. */
12983 do_vfp_cond_or_thumb ();
12984 }
12985}
12986
12987/* VMOV has particularly many variations. It can be one of:
12988 0. VMOV<c><q> <Qd>, <Qm>
12989 1. VMOV<c><q> <Dd>, <Dm>
12990 (Register operations, which are VORR with Rm = Rn.)
12991 2. VMOV<c><q>.<dt> <Qd>, #<imm>
12992 3. VMOV<c><q>.<dt> <Dd>, #<imm>
12993 (Immediate loads.)
12994 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
12995 (ARM register to scalar.)
12996 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
12997 (Two ARM registers to vector.)
12998 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
12999 (Scalar to ARM register.)
13000 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13001 (Vector to two ARM registers.)
13002 8. VMOV.F32 <Sd>, <Sm>
13003 9. VMOV.F64 <Dd>, <Dm>
13004 (VFP register moves.)
13005 10. VMOV.F32 <Sd>, #imm
13006 11. VMOV.F64 <Dd>, #imm
13007 (VFP float immediate load.)
13008 12. VMOV <Rd>, <Sm>
13009 (VFP single to ARM reg.)
13010 13. VMOV <Sd>, <Rm>
13011 (ARM reg to VFP single.)
13012 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13013 (Two ARM regs to two VFP singles.)
13014 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13015 (Two VFP singles to two ARM regs.)
13016
13017 These cases can be disambiguated using neon_select_shape, except cases 1/9
13018 and 3/11 which depend on the operand type too.
13019
13020 All the encoded bits are hardcoded by this function.
13021
13022 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13023 Cases 5, 7 may be used with VFPv2 and above.
13024
13025 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13026 can specify a type where it doesn't make sense to, and is ignored).
13027*/
13028
13029static void
13030do_neon_mov (void)
13031{
13032 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
13033 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
13034 NS_NULL);
13035 struct neon_type_el et;
13036 const char *ldconst = 0;
13037
13038 switch (rs)
13039 {
13040 case NS_DD: /* case 1/9. */
13041 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
13042 /* It is not an error here if no type is given. */
13043 inst.error = NULL;
13044 if (et.type == NT_float && et.size == 64)
13045 {
13046 do_vfp_nsyn_opcode ("fcpyd");
13047 break;
13048 }
13049 /* fall through. */
13050
13051 case NS_QQ: /* case 0/1. */
13052 {
13053 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13054 return;
13055 /* The architecture manual I have doesn't explicitly state which
13056 value the U bit should have for register->register moves, but
13057 the equivalent VORR instruction has U = 0, so do that. */
13058 inst.instruction = 0x0200110;
13059 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13060 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13061 inst.instruction |= LOW4 (inst.operands[1].reg);
13062 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13063 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13064 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13065 inst.instruction |= neon_quad (rs) << 6;
13066
13067 inst.instruction = neon_dp_fixup (inst.instruction);
13068 }
13069 break;
13070
13071 case NS_DI: /* case 3/11. */
13072 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
13073 inst.error = NULL;
13074 if (et.type == NT_float && et.size == 64)
13075 {
13076 /* case 11 (fconstd). */
13077 ldconst = "fconstd";
13078 goto encode_fconstd;
13079 }
13080 /* fall through. */
13081
13082 case NS_QI: /* case 2/3. */
13083 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13084 return;
13085 inst.instruction = 0x0800010;
13086 neon_move_immediate ();
13087 inst.instruction = neon_dp_fixup (inst.instruction);
13088 break;
13089
13090 case NS_SR: /* case 4. */
13091 {
13092 unsigned bcdebits = 0;
13093 struct neon_type_el et = neon_check_type (2, NS_NULL,
13094 N_8 | N_16 | N_32 | N_KEY, N_EQK);
13095 int logsize = neon_logbits (et.size);
13096 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
13097 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
13098
13099 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
13100 _(BAD_FPU));
13101 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
13102 && et.size != 32, _(BAD_FPU));
13103 constraint (et.type == NT_invtype, _("bad type for scalar"));
13104 constraint (x >= 64 / et.size, _("scalar index out of range"));
13105
13106 switch (et.size)
13107 {
13108 case 8: bcdebits = 0x8; break;
13109 case 16: bcdebits = 0x1; break;
13110 case 32: bcdebits = 0x0; break;
13111 default: ;
13112 }
13113
13114 bcdebits |= x << logsize;
13115
13116 inst.instruction = 0xe000b10;
13117 do_vfp_cond_or_thumb ();
13118 inst.instruction |= LOW4 (dn) << 16;
13119 inst.instruction |= HI1 (dn) << 7;
13120 inst.instruction |= inst.operands[1].reg << 12;
13121 inst.instruction |= (bcdebits & 3) << 5;
13122 inst.instruction |= (bcdebits >> 2) << 21;
13123 }
13124 break;
13125
13126 case NS_DRR: /* case 5 (fmdrr). */
13127 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
13128 _(BAD_FPU));
13129
13130 inst.instruction = 0xc400b10;
13131 do_vfp_cond_or_thumb ();
13132 inst.instruction |= LOW4 (inst.operands[0].reg);
13133 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
13134 inst.instruction |= inst.operands[1].reg << 12;
13135 inst.instruction |= inst.operands[2].reg << 16;
13136 break;
13137
13138 case NS_RS: /* case 6. */
13139 {
13140 struct neon_type_el et = neon_check_type (2, NS_NULL,
13141 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
13142 unsigned logsize = neon_logbits (et.size);
13143 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
13144 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
13145 unsigned abcdebits = 0;
13146
13147 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
13148 _(BAD_FPU));
13149 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
13150 && et.size != 32, _(BAD_FPU));
13151 constraint (et.type == NT_invtype, _("bad type for scalar"));
13152 constraint (x >= 64 / et.size, _("scalar index out of range"));
13153
13154 switch (et.size)
13155 {
13156 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
13157 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
13158 case 32: abcdebits = 0x00; break;
13159 default: ;
13160 }
13161
13162 abcdebits |= x << logsize;
13163 inst.instruction = 0xe100b10;
13164 do_vfp_cond_or_thumb ();
13165 inst.instruction |= LOW4 (dn) << 16;
13166 inst.instruction |= HI1 (dn) << 7;
13167 inst.instruction |= inst.operands[0].reg << 12;
13168 inst.instruction |= (abcdebits & 3) << 5;
13169 inst.instruction |= (abcdebits >> 2) << 21;
13170 }
13171 break;
13172
13173 case NS_RRD: /* case 7 (fmrrd). */
13174 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
13175 _(BAD_FPU));
13176
13177 inst.instruction = 0xc500b10;
13178 do_vfp_cond_or_thumb ();
13179 inst.instruction |= inst.operands[0].reg << 12;
13180 inst.instruction |= inst.operands[1].reg << 16;
13181 inst.instruction |= LOW4 (inst.operands[2].reg);
13182 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13183 break;
13184
13185 case NS_FF: /* case 8 (fcpys). */
13186 do_vfp_nsyn_opcode ("fcpys");
13187 break;
13188
13189 case NS_FI: /* case 10 (fconsts). */
13190 ldconst = "fconsts";
13191 encode_fconstd:
13192 if (is_quarter_float (inst.operands[1].imm))
13193 {
13194 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
13195 do_vfp_nsyn_opcode (ldconst);
13196 }
13197 else
13198 first_error (_("immediate out of range"));
13199 break;
13200
13201 case NS_RF: /* case 12 (fmrs). */
13202 do_vfp_nsyn_opcode ("fmrs");
13203 break;
13204
13205 case NS_FR: /* case 13 (fmsr). */
13206 do_vfp_nsyn_opcode ("fmsr");
13207 break;
13208
13209 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13210 (one of which is a list), but we have parsed four. Do some fiddling to
13211 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13212 expect. */
13213 case NS_RRFF: /* case 14 (fmrrs). */
13214 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
13215 _("VFP registers must be adjacent"));
13216 inst.operands[2].imm = 2;
13217 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
13218 do_vfp_nsyn_opcode ("fmrrs");
13219 break;
13220
13221 case NS_FFRR: /* case 15 (fmsrr). */
13222 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
13223 _("VFP registers must be adjacent"));
13224 inst.operands[1] = inst.operands[2];
13225 inst.operands[2] = inst.operands[3];
13226 inst.operands[0].imm = 2;
13227 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
13228 do_vfp_nsyn_opcode ("fmsrr");
13229 break;
13230
13231 default:
13232 abort ();
13233 }
13234}
13235
13236static void
13237do_neon_rshift_round_imm (void)
13238{
13239 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13240 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13241 int imm = inst.operands[2].imm;
13242
13243 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13244 if (imm == 0)
13245 {
13246 inst.operands[2].present = 0;
13247 do_neon_mov ();
13248 return;
13249 }
13250
13251 constraint (imm < 1 || (unsigned)imm > et.size,
13252 _("immediate out of range for shift"));
13253 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13254 et.size - imm);
13255}
13256
13257static void
13258do_neon_movl (void)
13259{
13260 struct neon_type_el et = neon_check_type (2, NS_QD,
13261 N_EQK | N_DBL, N_SU_32 | N_KEY);
13262 unsigned sizebits = et.size >> 3;
13263 inst.instruction |= sizebits << 19;
13264 neon_two_same (0, et.type == NT_unsigned, -1);
13265}
13266
13267static void
13268do_neon_trn (void)
13269{
13270 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13271 struct neon_type_el et = neon_check_type (2, rs,
13272 N_EQK, N_8 | N_16 | N_32 | N_KEY);
13273 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
13274 neon_two_same (neon_quad (rs), 1, et.size);
13275}
13276
13277static void
13278do_neon_zip_uzp (void)
13279{
13280 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13281 struct neon_type_el et = neon_check_type (2, rs,
13282 N_EQK, N_8 | N_16 | N_32 | N_KEY);
13283 if (rs == NS_DD && et.size == 32)
13284 {
13285 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13286 inst.instruction = N_MNEM_vtrn;
13287 do_neon_trn ();
13288 return;
13289 }
13290 neon_two_same (neon_quad (rs), 1, et.size);
13291}
13292
13293static void
13294do_neon_sat_abs_neg (void)
13295{
13296 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13297 struct neon_type_el et = neon_check_type (2, rs,
13298 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
13299 neon_two_same (neon_quad (rs), 1, et.size);
13300}
13301
13302static void
13303do_neon_pair_long (void)
13304{
13305 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13306 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
13307 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13308 inst.instruction |= (et.type == NT_unsigned) << 7;
13309 neon_two_same (neon_quad (rs), 1, et.size);
13310}
13311
13312static void
13313do_neon_recip_est (void)
13314{
13315 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13316 struct neon_type_el et = neon_check_type (2, rs,
13317 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
13318 inst.instruction |= (et.type == NT_float) << 8;
13319 neon_two_same (neon_quad (rs), 1, et.size);
13320}
13321
13322static void
13323do_neon_cls (void)
13324{
13325 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13326 struct neon_type_el et = neon_check_type (2, rs,
13327 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
13328 neon_two_same (neon_quad (rs), 1, et.size);
13329}
13330
13331static void
13332do_neon_clz (void)
13333{
13334 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13335 struct neon_type_el et = neon_check_type (2, rs,
13336 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
13337 neon_two_same (neon_quad (rs), 1, et.size);
13338}
13339
13340static void
13341do_neon_cnt (void)
13342{
13343 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13344 struct neon_type_el et = neon_check_type (2, rs,
13345 N_EQK | N_INT, N_8 | N_KEY);
13346 neon_two_same (neon_quad (rs), 1, et.size);
13347}
13348
13349static void
13350do_neon_swp (void)
13351{
13352 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13353 neon_two_same (neon_quad (rs), 1, -1);
13354}
13355
13356static void
13357do_neon_tbl_tbx (void)
13358{
13359 unsigned listlenbits;
13360 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
13361
13362 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
13363 {
13364 first_error (_("bad list length for table lookup"));
13365 return;
13366 }
13367
13368 listlenbits = inst.operands[1].imm - 1;
13369 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13370 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13371 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13372 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13373 inst.instruction |= LOW4 (inst.operands[2].reg);
13374 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13375 inst.instruction |= listlenbits << 8;
13376
13377 inst.instruction = neon_dp_fixup (inst.instruction);
13378}
13379
13380static void
13381do_neon_ldm_stm (void)
13382{
13383 /* P, U and L bits are part of bitmask. */
13384 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
13385 unsigned offsetbits = inst.operands[1].imm * 2;
13386
13387 if (inst.operands[1].issingle)
13388 {
13389 do_vfp_nsyn_ldm_stm (is_dbmode);
13390 return;
13391 }
13392
13393 constraint (is_dbmode && !inst.operands[0].writeback,
13394 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13395
13396 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
13397 _("register list must contain at least 1 and at most 16 "
13398 "registers"));
13399
13400 inst.instruction |= inst.operands[0].reg << 16;
13401 inst.instruction |= inst.operands[0].writeback << 21;
13402 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
13403 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
13404
13405 inst.instruction |= offsetbits;
13406
13407 do_vfp_cond_or_thumb ();
13408}
13409
13410static void
13411do_neon_ldr_str (void)
13412{
13413 int is_ldr = (inst.instruction & (1 << 20)) != 0;
13414
13415 if (inst.operands[0].issingle)
13416 {
13417 if (is_ldr)
13418 do_vfp_nsyn_opcode ("flds");
13419 else
13420 do_vfp_nsyn_opcode ("fsts");
13421 }
13422 else
13423 {
13424 if (is_ldr)
13425 do_vfp_nsyn_opcode ("fldd");
13426 else
13427 do_vfp_nsyn_opcode ("fstd");
13428 }
13429}
13430
13431/* "interleave" version also handles non-interleaving register VLD1/VST1
13432 instructions. */
13433
13434static void
13435do_neon_ld_st_interleave (void)
13436{
13437 struct neon_type_el et = neon_check_type (1, NS_NULL,
13438 N_8 | N_16 | N_32 | N_64);
13439 unsigned alignbits = 0;
13440 unsigned idx;
13441 /* The bits in this table go:
13442 0: register stride of one (0) or two (1)
13443 1,2: register list length, minus one (1, 2, 3, 4).
13444 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13445 We use -1 for invalid entries. */
13446 const int typetable[] =
13447 {
13448 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13449 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13450 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13451 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13452 };
13453 int typebits;
13454
13455 if (et.type == NT_invtype)
13456 return;
13457
13458 if (inst.operands[1].immisalign)
13459 switch (inst.operands[1].imm >> 8)
13460 {
13461 case 64: alignbits = 1; break;
13462 case 128:
13463 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3)
13464 goto bad_alignment;
13465 alignbits = 2;
13466 break;
13467 case 256:
13468 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3)
13469 goto bad_alignment;
13470 alignbits = 3;
13471 break;
13472 default:
13473 bad_alignment:
13474 first_error (_("bad alignment"));
13475 return;
13476 }
13477
13478 inst.instruction |= alignbits << 4;
13479 inst.instruction |= neon_logbits (et.size) << 6;
13480
13481 /* Bits [4:6] of the immediate in a list specifier encode register stride
13482 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13483 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13484 up the right value for "type" in a table based on this value and the given
13485 list style, then stick it back. */
13486 idx = ((inst.operands[0].imm >> 4) & 7)
13487 | (((inst.instruction >> 8) & 3) << 3);
13488
13489 typebits = typetable[idx];
13490
13491 constraint (typebits == -1, _("bad list type for instruction"));
13492
13493 inst.instruction &= ~0xf00;
13494 inst.instruction |= typebits << 8;
13495}
13496
13497/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13498 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13499 otherwise. The variable arguments are a list of pairs of legal (size, align)
13500 values, terminated with -1. */
13501
13502static int
13503neon_alignment_bit (int size, int align, int *do_align, ...)
13504{
13505 va_list ap;
13506 int result = FAIL, thissize, thisalign;
13507
13508 if (!inst.operands[1].immisalign)
13509 {
13510 *do_align = 0;
13511 return SUCCESS;
13512 }
13513
13514 va_start (ap, do_align);
13515
13516 do
13517 {
13518 thissize = va_arg (ap, int);
13519 if (thissize == -1)
13520 break;
13521 thisalign = va_arg (ap, int);
13522
13523 if (size == thissize && align == thisalign)
13524 result = SUCCESS;
13525 }
13526 while (result != SUCCESS);
13527
13528 va_end (ap);
13529
13530 if (result == SUCCESS)
13531 *do_align = 1;
13532 else
13533 first_error (_("unsupported alignment for instruction"));
13534
13535 return result;
13536}
13537
13538static void
13539do_neon_ld_st_lane (void)
13540{
13541 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
13542 int align_good, do_align = 0;
13543 int logsize = neon_logbits (et.size);
13544 int align = inst.operands[1].imm >> 8;
13545 int n = (inst.instruction >> 8) & 3;
13546 int max_el = 64 / et.size;
13547
13548 if (et.type == NT_invtype)
13549 return;
13550
13551 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
13552 _("bad list length"));
13553 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
13554 _("scalar index out of range"));
13555 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
13556 && et.size == 8,
13557 _("stride of 2 unavailable when element size is 8"));
13558
13559 switch (n)
13560 {
13561 case 0: /* VLD1 / VST1. */
13562 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
13563 32, 32, -1);
13564 if (align_good == FAIL)
13565 return;
13566 if (do_align)
13567 {
13568 unsigned alignbits = 0;
13569 switch (et.size)
13570 {
13571 case 16: alignbits = 0x1; break;
13572 case 32: alignbits = 0x3; break;
13573 default: ;
13574 }
13575 inst.instruction |= alignbits << 4;
13576 }
13577 break;
13578
13579 case 1: /* VLD2 / VST2. */
13580 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
13581 32, 64, -1);
13582 if (align_good == FAIL)
13583 return;
13584 if (do_align)
13585 inst.instruction |= 1 << 4;
13586 break;
13587
13588 case 2: /* VLD3 / VST3. */
13589 constraint (inst.operands[1].immisalign,
13590 _("can't use alignment with this instruction"));
13591 break;
13592
13593 case 3: /* VLD4 / VST4. */
13594 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
13595 16, 64, 32, 64, 32, 128, -1);
13596 if (align_good == FAIL)
13597 return;
13598 if (do_align)
13599 {
13600 unsigned alignbits = 0;
13601 switch (et.size)
13602 {
13603 case 8: alignbits = 0x1; break;
13604 case 16: alignbits = 0x1; break;
13605 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
13606 default: ;
13607 }
13608 inst.instruction |= alignbits << 4;
13609 }
13610 break;
13611
13612 default: ;
13613 }
13614
13615 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13616 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13617 inst.instruction |= 1 << (4 + logsize);
13618
13619 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
13620 inst.instruction |= logsize << 10;
13621}
13622
13623/* Encode single n-element structure to all lanes VLD<n> instructions. */
13624
13625static void
13626do_neon_ld_dup (void)
13627{
13628 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
13629 int align_good, do_align = 0;
13630
13631 if (et.type == NT_invtype)
13632 return;
13633
13634 switch ((inst.instruction >> 8) & 3)
13635 {
13636 case 0: /* VLD1. */
13637 assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
13638 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
13639 &do_align, 16, 16, 32, 32, -1);
13640 if (align_good == FAIL)
13641 return;
13642 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
13643 {
13644 case 1: break;
13645 case 2: inst.instruction |= 1 << 5; break;
13646 default: first_error (_("bad list length")); return;
13647 }
13648 inst.instruction |= neon_logbits (et.size) << 6;
13649 break;
13650
13651 case 1: /* VLD2. */
13652 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
13653 &do_align, 8, 16, 16, 32, 32, 64, -1);
13654 if (align_good == FAIL)
13655 return;
13656 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
13657 _("bad list length"));
13658 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13659 inst.instruction |= 1 << 5;
13660 inst.instruction |= neon_logbits (et.size) << 6;
13661 break;
13662
13663 case 2: /* VLD3. */
13664 constraint (inst.operands[1].immisalign,
13665 _("can't use alignment with this instruction"));
13666 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
13667 _("bad list length"));
13668 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13669 inst.instruction |= 1 << 5;
13670 inst.instruction |= neon_logbits (et.size) << 6;
13671 break;
13672
13673 case 3: /* VLD4. */
13674 {
13675 int align = inst.operands[1].imm >> 8;
13676 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
13677 16, 64, 32, 64, 32, 128, -1);
13678 if (align_good == FAIL)
13679 return;
13680 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
13681 _("bad list length"));
13682 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13683 inst.instruction |= 1 << 5;
13684 if (et.size == 32 && align == 128)
13685 inst.instruction |= 0x3 << 6;
13686 else
13687 inst.instruction |= neon_logbits (et.size) << 6;
13688 }
13689 break;
13690
13691 default: ;
13692 }
13693
13694 inst.instruction |= do_align << 4;
13695}
13696
13697/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13698 apart from bits [11:4]. */
13699
13700static void
13701do_neon_ldx_stx (void)
13702{
13703 switch (NEON_LANE (inst.operands[0].imm))
13704 {
13705 case NEON_INTERLEAVE_LANES:
13706 inst.instruction = NEON_ENC_INTERLV (inst.instruction);
13707 do_neon_ld_st_interleave ();
13708 break;
13709
13710 case NEON_ALL_LANES:
13711 inst.instruction = NEON_ENC_DUP (inst.instruction);
13712 do_neon_ld_dup ();
13713 break;
13714
13715 default:
13716 inst.instruction = NEON_ENC_LANE (inst.instruction);
13717 do_neon_ld_st_lane ();
13718 }
13719
13720 /* L bit comes from bit mask. */
13721 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13722 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13723 inst.instruction |= inst.operands[1].reg << 16;
13724
13725 if (inst.operands[1].postind)
13726 {
13727 int postreg = inst.operands[1].imm & 0xf;
13728 constraint (!inst.operands[1].immisreg,
13729 _("post-index must be a register"));
13730 constraint (postreg == 0xd || postreg == 0xf,
13731 _("bad register for post-index"));
13732 inst.instruction |= postreg;
13733 }
13734 else if (inst.operands[1].writeback)
13735 {
13736 inst.instruction |= 0xd;
13737 }
13738 else
13739 inst.instruction |= 0xf;
13740
13741 if (thumb_mode)
13742 inst.instruction |= 0xf9000000;
13743 else
13744 inst.instruction |= 0xf4000000;
13745}
13746
13747
13748/* Overall per-instruction processing. */
13749
13750/* We need to be able to fix up arbitrary expressions in some statements.
13751 This is so that we can handle symbols that are an arbitrary distance from
13752 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13753 which returns part of an address in a form which will be valid for
13754 a data instruction. We do this by pushing the expression into a symbol
13755 in the expr_section, and creating a fix for that. */
13756
13757static void
13758fix_new_arm (fragS * frag,
13759 int where,
13760 short int size,
13761 expressionS * exp,
13762 int pc_rel,
13763 int reloc)
13764{
13765 fixS * new_fix;
13766
13767 switch (exp->X_op)
13768 {
13769 case O_constant:
13770 case O_symbol:
13771 case O_add:
13772 case O_subtract:
13773 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
13774 break;
13775
13776 default:
13777 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
13778 pc_rel, reloc);
13779 break;
13780 }
13781
13782 /* Mark whether the fix is to a THUMB instruction, or an ARM
13783 instruction. */
13784 new_fix->tc_fix_data = thumb_mode;
13785}
13786
13787/* Create a frg for an instruction requiring relaxation. */
13788static void
13789output_relax_insn (void)
13790{
13791 char * to;
13792 symbolS *sym;
13793 int offset;
13794
13795 /* The size of the instruction is unknown, so tie the debug info to the
13796 start of the instruction. */
13797 dwarf2_emit_insn (0);
13798
13799 switch (inst.reloc.exp.X_op)
13800 {
13801 case O_symbol:
13802 sym = inst.reloc.exp.X_add_symbol;
13803 offset = inst.reloc.exp.X_add_number;
13804 break;
13805 case O_constant:
13806 sym = NULL;
13807 offset = inst.reloc.exp.X_add_number;
13808 break;
13809 default:
13810 sym = make_expr_symbol (&inst.reloc.exp);
13811 offset = 0;
13812 break;
13813 }
13814 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
13815 inst.relax, sym, offset, NULL/*offset, opcode*/);
13816 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
13817}
13818
13819/* Write a 32-bit thumb instruction to buf. */
13820static void
13821put_thumb32_insn (char * buf, unsigned long insn)
13822{
13823 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
13824 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
13825}
13826
13827static void
13828output_inst (const char * str)
13829{
13830 char * to = NULL;
13831
13832 if (inst.error)
13833 {
13834 as_bad ("%s -- `%s'", inst.error, str);
13835 return;
13836 }
13837 if (inst.relax) {
13838 output_relax_insn();
13839 return;
13840 }
13841 if (inst.size == 0)
13842 return;
13843
13844 to = frag_more (inst.size);
13845
13846 if (thumb_mode && (inst.size > THUMB_SIZE))
13847 {
13848 assert (inst.size == (2 * THUMB_SIZE));
13849 put_thumb32_insn (to, inst.instruction);
13850 }
13851 else if (inst.size > INSN_SIZE)
13852 {
13853 assert (inst.size == (2 * INSN_SIZE));
13854 md_number_to_chars (to, inst.instruction, INSN_SIZE);
13855 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
13856 }
13857 else
13858 md_number_to_chars (to, inst.instruction, inst.size);
13859
13860 if (inst.reloc.type != BFD_RELOC_UNUSED)
13861 fix_new_arm (frag_now, to - frag_now->fr_literal,
13862 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
13863 inst.reloc.type);
13864
13865 dwarf2_emit_insn (inst.size);
13866}
13867
13868/* Tag values used in struct asm_opcode's tag field. */
13869enum opcode_tag
13870{
13871 OT_unconditional, /* Instruction cannot be conditionalized.
13872 The ARM condition field is still 0xE. */
13873 OT_unconditionalF, /* Instruction cannot be conditionalized
13874 and carries 0xF in its ARM condition field. */
13875 OT_csuffix, /* Instruction takes a conditional suffix. */
13876 OT_csuffixF, /* Some forms of the instruction take a conditional
13877 suffix, others place 0xF where the condition field
13878 would be. */
13879 OT_cinfix3, /* Instruction takes a conditional infix,
13880 beginning at character index 3. (In
13881 unified mode, it becomes a suffix.) */
13882 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
13883 tsts, cmps, cmns, and teqs. */
13884 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
13885 character index 3, even in unified mode. Used for
13886 legacy instructions where suffix and infix forms
13887 may be ambiguous. */
13888 OT_csuf_or_in3, /* Instruction takes either a conditional
13889 suffix or an infix at character index 3. */
13890 OT_odd_infix_unc, /* This is the unconditional variant of an
13891 instruction that takes a conditional infix
13892 at an unusual position. In unified mode,
13893 this variant will accept a suffix. */
13894 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
13895 are the conditional variants of instructions that
13896 take conditional infixes in unusual positions.
13897 The infix appears at character index
13898 (tag - OT_odd_infix_0). These are not accepted
13899 in unified mode. */
13900};
13901
13902/* Subroutine of md_assemble, responsible for looking up the primary
13903 opcode from the mnemonic the user wrote. STR points to the
13904 beginning of the mnemonic.
13905
13906 This is not simply a hash table lookup, because of conditional
13907 variants. Most instructions have conditional variants, which are
13908 expressed with a _conditional affix_ to the mnemonic. If we were
13909 to encode each conditional variant as a literal string in the opcode
13910 table, it would have approximately 20,000 entries.
13911
13912 Most mnemonics take this affix as a suffix, and in unified syntax,
13913 'most' is upgraded to 'all'. However, in the divided syntax, some
13914 instructions take the affix as an infix, notably the s-variants of
13915 the arithmetic instructions. Of those instructions, all but six
13916 have the infix appear after the third character of the mnemonic.
13917
13918 Accordingly, the algorithm for looking up primary opcodes given
13919 an identifier is:
13920
13921 1. Look up the identifier in the opcode table.
13922 If we find a match, go to step U.
13923
13924 2. Look up the last two characters of the identifier in the
13925 conditions table. If we find a match, look up the first N-2
13926 characters of the identifier in the opcode table. If we
13927 find a match, go to step CE.
13928
13929 3. Look up the fourth and fifth characters of the identifier in
13930 the conditions table. If we find a match, extract those
13931 characters from the identifier, and look up the remaining
13932 characters in the opcode table. If we find a match, go
13933 to step CM.
13934
13935 4. Fail.
13936
13937 U. Examine the tag field of the opcode structure, in case this is
13938 one of the six instructions with its conditional infix in an
13939 unusual place. If it is, the tag tells us where to find the
13940 infix; look it up in the conditions table and set inst.cond
13941 accordingly. Otherwise, this is an unconditional instruction.
13942 Again set inst.cond accordingly. Return the opcode structure.
13943
13944 CE. Examine the tag field to make sure this is an instruction that
13945 should receive a conditional suffix. If it is not, fail.
13946 Otherwise, set inst.cond from the suffix we already looked up,
13947 and return the opcode structure.
13948
13949 CM. Examine the tag field to make sure this is an instruction that
13950 should receive a conditional infix after the third character.
13951 If it is not, fail. Otherwise, undo the edits to the current
13952 line of input and proceed as for case CE. */
13953
13954static const struct asm_opcode *
13955opcode_lookup (char **str)
13956{
13957 char *end, *base;
13958 char *affix;
13959 const struct asm_opcode *opcode;
13960 const struct asm_cond *cond;
13961 char save[2];
13962 bfd_boolean neon_supported;
13963
13964 neon_supported = ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1);
13965
13966 /* Scan up to the end of the mnemonic, which must end in white space,
13967 '.' (in unified mode, or for Neon instructions), or end of string. */
13968 for (base = end = *str; *end != '\0'; end++)
13969 if (*end == ' ' || ((unified_syntax || neon_supported) && *end == '.'))
13970 break;
13971
13972 if (end == base)
13973 return 0;
13974
13975 /* Handle a possible width suffix and/or Neon type suffix. */
13976 if (end[0] == '.')
13977 {
13978 int offset = 2;
13979
13980 /* The .w and .n suffixes are only valid if the unified syntax is in
13981 use. */
13982 if (unified_syntax && end[1] == 'w')
13983 inst.size_req = 4;
13984 else if (unified_syntax && end[1] == 'n')
13985 inst.size_req = 2;
13986 else
13987 offset = 0;
13988
13989 inst.vectype.elems = 0;
13990
13991 *str = end + offset;
13992
13993 if (end[offset] == '.')
13994 {
13995 /* See if we have a Neon type suffix (possible in either unified or
13996 non-unified ARM syntax mode). */
13997 if (parse_neon_type (&inst.vectype, str) == FAIL)
13998 return 0;
13999 }
14000 else if (end[offset] != '\0' && end[offset] != ' ')
14001 return 0;
14002 }
14003 else
14004 *str = end;
14005
14006 /* Look for unaffixed or special-case affixed mnemonic. */
14007 opcode = hash_find_n (arm_ops_hsh, base, end - base);
14008 if (opcode)
14009 {
14010 /* step U */
14011 if (opcode->tag < OT_odd_infix_0)
14012 {
14013 inst.cond = COND_ALWAYS;
14014 return opcode;
14015 }
14016
14017 if (unified_syntax)
14018 as_warn (_("conditional infixes are deprecated in unified syntax"));
14019 affix = base + (opcode->tag - OT_odd_infix_0);
14020 cond = hash_find_n (arm_cond_hsh, affix, 2);
14021 assert (cond);
14022
14023 inst.cond = cond->value;
14024 return opcode;
14025 }
14026
14027 /* Cannot have a conditional suffix on a mnemonic of less than two
14028 characters. */
14029 if (end - base < 3)
14030 return 0;
14031
14032 /* Look for suffixed mnemonic. */
14033 affix = end - 2;
14034 cond = hash_find_n (arm_cond_hsh, affix, 2);
14035 opcode = hash_find_n (arm_ops_hsh, base, affix - base);
14036 if (opcode && cond)
14037 {
14038 /* step CE */
14039 switch (opcode->tag)
14040 {
14041 case OT_cinfix3_legacy:
14042 /* Ignore conditional suffixes matched on infix only mnemonics. */
14043 break;
14044
14045 case OT_cinfix3:
14046 case OT_cinfix3_deprecated:
14047 case OT_odd_infix_unc:
14048 if (!unified_syntax)
14049 return 0;
14050 /* else fall through */
14051
14052 case OT_csuffix:
14053 case OT_csuffixF:
14054 case OT_csuf_or_in3:
14055 inst.cond = cond->value;
14056 return opcode;
14057
14058 case OT_unconditional:
14059 case OT_unconditionalF:
14060 if (thumb_mode)
14061 {
14062 inst.cond = cond->value;
14063 }
14064 else
14065 {
14066 /* delayed diagnostic */
14067 inst.error = BAD_COND;
14068 inst.cond = COND_ALWAYS;
14069 }
14070 return opcode;
14071
14072 default:
14073 return 0;
14074 }
14075 }
14076
14077 /* Cannot have a usual-position infix on a mnemonic of less than
14078 six characters (five would be a suffix). */
14079 if (end - base < 6)
14080 return 0;
14081
14082 /* Look for infixed mnemonic in the usual position. */
14083 affix = base + 3;
14084 cond = hash_find_n (arm_cond_hsh, affix, 2);
14085 if (!cond)
14086 return 0;
14087
14088 memcpy (save, affix, 2);
14089 memmove (affix, affix + 2, (end - affix) - 2);
14090 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2);
14091 memmove (affix + 2, affix, (end - affix) - 2);
14092 memcpy (affix, save, 2);
14093
14094 if (opcode
14095 && (opcode->tag == OT_cinfix3
14096 || opcode->tag == OT_cinfix3_deprecated
14097 || opcode->tag == OT_csuf_or_in3
14098 || opcode->tag == OT_cinfix3_legacy))
14099 {
14100 /* step CM */
14101 if (unified_syntax
14102 && (opcode->tag == OT_cinfix3
14103 || opcode->tag == OT_cinfix3_deprecated))
14104 as_warn (_("conditional infixes are deprecated in unified syntax"));
14105
14106 inst.cond = cond->value;
14107 return opcode;
14108 }
14109
14110 return 0;
14111}
14112
14113void
14114md_assemble (char *str)
14115{
14116 char *p = str;
14117 const struct asm_opcode * opcode;
14118
14119 /* Align the previous label if needed. */
14120 if (last_label_seen != NULL)
14121 {
14122 symbol_set_frag (last_label_seen, frag_now);
14123 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
14124 S_SET_SEGMENT (last_label_seen, now_seg);
14125 }
14126
14127 memset (&inst, '\0', sizeof (inst));
14128 inst.reloc.type = BFD_RELOC_UNUSED;
14129
14130 opcode = opcode_lookup (&p);
14131 if (!opcode)
14132 {
14133 /* It wasn't an instruction, but it might be a register alias of
14134 the form alias .req reg, or a Neon .dn/.qn directive. */
14135 if (!create_register_alias (str, p)
14136 && !create_neon_reg_alias (str, p))
14137 as_bad (_("bad instruction `%s'"), str);
14138
14139 return;
14140 }
14141
14142 if (opcode->tag == OT_cinfix3_deprecated)
14143 as_warn (_("s suffix on comparison instruction is deprecated"));
14144
14145 /* The value which unconditional instructions should have in place of the
14146 condition field. */
14147 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
14148
14149 if (thumb_mode)
14150 {
14151 arm_feature_set variant;
14152
14153 variant = cpu_variant;
14154 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
14155 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
14156 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
14157 /* Check that this instruction is supported for this CPU. */
14158 if (!opcode->tvariant
14159 || (thumb_mode == 1
14160 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
14161 {
14162 as_bad (_("selected processor does not support `%s'"), str);
14163 return;
14164 }
14165 if (inst.cond != COND_ALWAYS && !unified_syntax
14166 && opcode->tencode != do_t_branch)
14167 {
14168 as_bad (_("Thumb does not support conditional execution"));
14169 return;
14170 }
14171
14172 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req)
14173 {
14174 /* Implicit require narrow instructions on Thumb-1. This avoids
14175 relaxation accidentally introducing Thumb-2 instructions. */
14176 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23)
14177 inst.size_req = 2;
14178 }
14179
14180 /* Check conditional suffixes. */
14181 if (current_it_mask)
14182 {
14183 int cond;
14184 cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1;
14185 current_it_mask <<= 1;
14186 current_it_mask &= 0x1f;
14187 /* The BKPT instruction is unconditional even in an IT block. */
14188 if (!inst.error
14189 && cond != inst.cond && opcode->tencode != do_t_bkpt)
14190 {
14191 as_bad (_("incorrect condition in IT block"));
14192 return;
14193 }
14194 }
14195 else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch)
14196 {
14197 as_bad (_("thumb conditional instrunction not in IT block"));
14198 return;
14199 }
14200
14201 mapping_state (MAP_THUMB);
14202 inst.instruction = opcode->tvalue;
14203
14204 if (!parse_operands (p, opcode->operands))
14205 opcode->tencode ();
14206
14207 /* Clear current_it_mask at the end of an IT block. */
14208 if (current_it_mask == 0x10)
14209 current_it_mask = 0;
14210
14211 if (!(inst.error || inst.relax))
14212 {
14213 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
14214 inst.size = (inst.instruction > 0xffff ? 4 : 2);
14215 if (inst.size_req && inst.size_req != inst.size)
14216 {
14217 as_bad (_("cannot honor width suffix -- `%s'"), str);
14218 return;
14219 }
14220 }
14221
14222 /* Something has gone badly wrong if we try to relax a fixed size
14223 instruction. */
14224 assert (inst.size_req == 0 || !inst.relax);
14225
14226 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
14227 *opcode->tvariant);
14228 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14229 set those bits when Thumb-2 32-bit instructions are seen. ie.
14230 anything other than bl/blx.
14231 This is overly pessimistic for relaxable instructions. */
14232 if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
14233 || inst.relax)
14234 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
14235 arm_ext_v6t2);
14236 }
14237 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
14238 {
14239 /* Check that this instruction is supported for this CPU. */
14240 if (!opcode->avariant ||
14241 !ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))
14242 {
14243 as_bad (_("selected processor does not support `%s'"), str);
14244 return;
14245 }
14246 if (inst.size_req)
14247 {
14248 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
14249 return;
14250 }
14251
14252 mapping_state (MAP_ARM);
14253 inst.instruction = opcode->avalue;
14254 if (opcode->tag == OT_unconditionalF)
14255 inst.instruction |= 0xF << 28;
14256 else
14257 inst.instruction |= inst.cond << 28;
14258 inst.size = INSN_SIZE;
14259 if (!parse_operands (p, opcode->operands))
14260 opcode->aencode ();
14261 /* Arm mode bx is marked as both v4T and v5 because it's still required
14262 on a hypothetical non-thumb v5 core. */
14263 if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t)
14264 || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5))
14265 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
14266 else
14267 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
14268 *opcode->avariant);
14269 }
14270 else
14271 {
14272 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14273 "-- `%s'"), str);
14274 return;
14275 }
14276 output_inst (str);
14277}
14278
14279/* Various frobbings of labels and their addresses. */
14280
14281void
14282arm_start_line_hook (void)
14283{
14284 last_label_seen = NULL;
14285}
14286
14287void
14288arm_frob_label (symbolS * sym)
14289{
14290 last_label_seen = sym;
14291
14292 ARM_SET_THUMB (sym, thumb_mode);
14293
14294#if defined OBJ_COFF || defined OBJ_ELF
14295 ARM_SET_INTERWORK (sym, support_interwork);
14296#endif
14297
14298 /* Note - do not allow local symbols (.Lxxx) to be labeled
14299 as Thumb functions. This is because these labels, whilst
14300 they exist inside Thumb code, are not the entry points for
14301 possible ARM->Thumb calls. Also, these labels can be used
14302 as part of a computed goto or switch statement. eg gcc
14303 can generate code that looks like this:
14304
14305 ldr r2, [pc, .Laaa]
14306 lsl r3, r3, #2
14307 ldr r2, [r3, r2]
14308 mov pc, r2
14309
14310 .Lbbb: .word .Lxxx
14311 .Lccc: .word .Lyyy
14312 ..etc...
14313 .Laaa: .word Lbbb
14314
14315 The first instruction loads the address of the jump table.
14316 The second instruction converts a table index into a byte offset.
14317 The third instruction gets the jump address out of the table.
14318 The fourth instruction performs the jump.
14319
14320 If the address stored at .Laaa is that of a symbol which has the
14321 Thumb_Func bit set, then the linker will arrange for this address
14322 to have the bottom bit set, which in turn would mean that the
14323 address computation performed by the third instruction would end
14324 up with the bottom bit set. Since the ARM is capable of unaligned
14325 word loads, the instruction would then load the incorrect address
14326 out of the jump table, and chaos would ensue. */
14327 if (label_is_thumb_function_name
14328 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
14329 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
14330 {
14331 /* When the address of a Thumb function is taken the bottom
14332 bit of that address should be set. This will allow
14333 interworking between Arm and Thumb functions to work
14334 correctly. */
14335
14336 THUMB_SET_FUNC (sym, 1);
14337
14338 label_is_thumb_function_name = FALSE;
14339 }
14340
14341 dwarf2_emit_label (sym);
14342}
14343
14344int
14345arm_data_in_code (void)
14346{
14347 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
14348 {
14349 *input_line_pointer = '/';
14350 input_line_pointer += 5;
14351 *input_line_pointer = 0;
14352 return 1;
14353 }
14354
14355 return 0;
14356}
14357
14358char *
14359arm_canonicalize_symbol_name (char * name)
14360{
14361 int len;
14362
14363 if (thumb_mode && (len = strlen (name)) > 5
14364 && streq (name + len - 5, "/data"))
14365 *(name + len - 5) = 0;
14366
14367 return name;
14368}
14369
14370/* Table of all register names defined by default. The user can
14371 define additional names with .req. Note that all register names
14372 should appear in both upper and lowercase variants. Some registers
14373 also have mixed-case names. */
14374
14375#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14376#define REGNUM(p,n,t) REGDEF(p##n, n, t)
14377#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14378#define REGSET(p,t) \
14379 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14380 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14381 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14382 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14383#define REGSETH(p,t) \
14384 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14385 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14386 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14387 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14388#define REGSET2(p,t) \
14389 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14390 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14391 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14392 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14393
14394static const struct reg_entry reg_names[] =
14395{
14396 /* ARM integer registers. */
14397 REGSET(r, RN), REGSET(R, RN),
14398
14399 /* ATPCS synonyms. */
14400 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
14401 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
14402 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
14403
14404 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
14405 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
14406 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
14407
14408 /* Well-known aliases. */
14409 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
14410 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
14411
14412 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
14413 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
14414
14415 /* Coprocessor numbers. */
14416 REGSET(p, CP), REGSET(P, CP),
14417
14418 /* Coprocessor register numbers. The "cr" variants are for backward
14419 compatibility. */
14420 REGSET(c, CN), REGSET(C, CN),
14421 REGSET(cr, CN), REGSET(CR, CN),
14422
14423 /* FPA registers. */
14424 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
14425 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
14426
14427 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
14428 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
14429
14430 /* VFP SP registers. */
14431 REGSET(s,VFS), REGSET(S,VFS),
14432 REGSETH(s,VFS), REGSETH(S,VFS),
14433
14434 /* VFP DP Registers. */
14435 REGSET(d,VFD), REGSET(D,VFD),
14436 /* Extra Neon DP registers. */
14437 REGSETH(d,VFD), REGSETH(D,VFD),
14438
14439 /* Neon QP registers. */
14440 REGSET2(q,NQ), REGSET2(Q,NQ),
14441
14442 /* VFP control registers. */
14443 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
14444 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
14445 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
14446 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
14447 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
14448 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
14449
14450 /* Maverick DSP coprocessor registers. */
14451 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
14452 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
14453
14454 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
14455 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
14456 REGDEF(dspsc,0,DSPSC),
14457
14458 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
14459 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
14460 REGDEF(DSPSC,0,DSPSC),
14461
14462 /* iWMMXt data registers - p0, c0-15. */
14463 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
14464
14465 /* iWMMXt control registers - p1, c0-3. */
14466 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
14467 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
14468 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
14469 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
14470
14471 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14472 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
14473 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
14474 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
14475 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
14476
14477 /* XScale accumulator registers. */
14478 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
14479};
14480#undef REGDEF
14481#undef REGNUM
14482#undef REGSET
14483
14484/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14485 within psr_required_here. */
14486static const struct asm_psr psrs[] =
14487{
14488 /* Backward compatibility notation. Note that "all" is no longer
14489 truly all possible PSR bits. */
14490 {"all", PSR_c | PSR_f},
14491 {"flg", PSR_f},
14492 {"ctl", PSR_c},
14493
14494 /* Individual flags. */
14495 {"f", PSR_f},
14496 {"c", PSR_c},
14497 {"x", PSR_x},
14498 {"s", PSR_s},
14499 /* Combinations of flags. */
14500 {"fs", PSR_f | PSR_s},
14501 {"fx", PSR_f | PSR_x},
14502 {"fc", PSR_f | PSR_c},
14503 {"sf", PSR_s | PSR_f},
14504 {"sx", PSR_s | PSR_x},
14505 {"sc", PSR_s | PSR_c},
14506 {"xf", PSR_x | PSR_f},
14507 {"xs", PSR_x | PSR_s},
14508 {"xc", PSR_x | PSR_c},
14509 {"cf", PSR_c | PSR_f},
14510 {"cs", PSR_c | PSR_s},
14511 {"cx", PSR_c | PSR_x},
14512 {"fsx", PSR_f | PSR_s | PSR_x},
14513 {"fsc", PSR_f | PSR_s | PSR_c},
14514 {"fxs", PSR_f | PSR_x | PSR_s},
14515 {"fxc", PSR_f | PSR_x | PSR_c},
14516 {"fcs", PSR_f | PSR_c | PSR_s},
14517 {"fcx", PSR_f | PSR_c | PSR_x},
14518 {"sfx", PSR_s | PSR_f | PSR_x},
14519 {"sfc", PSR_s | PSR_f | PSR_c},
14520 {"sxf", PSR_s | PSR_x | PSR_f},
14521 {"sxc", PSR_s | PSR_x | PSR_c},
14522 {"scf", PSR_s | PSR_c | PSR_f},
14523 {"scx", PSR_s | PSR_c | PSR_x},
14524 {"xfs", PSR_x | PSR_f | PSR_s},
14525 {"xfc", PSR_x | PSR_f | PSR_c},
14526 {"xsf", PSR_x | PSR_s | PSR_f},
14527 {"xsc", PSR_x | PSR_s | PSR_c},
14528 {"xcf", PSR_x | PSR_c | PSR_f},
14529 {"xcs", PSR_x | PSR_c | PSR_s},
14530 {"cfs", PSR_c | PSR_f | PSR_s},
14531 {"cfx", PSR_c | PSR_f | PSR_x},
14532 {"csf", PSR_c | PSR_s | PSR_f},
14533 {"csx", PSR_c | PSR_s | PSR_x},
14534 {"cxf", PSR_c | PSR_x | PSR_f},
14535 {"cxs", PSR_c | PSR_x | PSR_s},
14536 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
14537 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
14538 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
14539 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
14540 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
14541 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
14542 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
14543 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
14544 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
14545 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
14546 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
14547 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
14548 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
14549 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
14550 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
14551 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
14552 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
14553 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
14554 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
14555 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
14556 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
14557 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
14558 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
14559 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
14560};
14561
14562/* Table of V7M psr names. */
14563static const struct asm_psr v7m_psrs[] =
14564{
14565 {"apsr", 0 }, {"APSR", 0 },
14566 {"iapsr", 1 }, {"IAPSR", 1 },
14567 {"eapsr", 2 }, {"EAPSR", 2 },
14568 {"psr", 3 }, {"PSR", 3 },
14569 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
14570 {"ipsr", 5 }, {"IPSR", 5 },
14571 {"epsr", 6 }, {"EPSR", 6 },
14572 {"iepsr", 7 }, {"IEPSR", 7 },
14573 {"msp", 8 }, {"MSP", 8 },
14574 {"psp", 9 }, {"PSP", 9 },
14575 {"primask", 16}, {"PRIMASK", 16},
14576 {"basepri", 17}, {"BASEPRI", 17},
14577 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
14578 {"faultmask", 19}, {"FAULTMASK", 19},
14579 {"control", 20}, {"CONTROL", 20}
14580};
14581
14582/* Table of all shift-in-operand names. */
14583static const struct asm_shift_name shift_names [] =
14584{
14585 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
14586 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
14587 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
14588 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
14589 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
14590 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
14591};
14592
14593/* Table of all explicit relocation names. */
14594#ifdef OBJ_ELF
14595static struct reloc_entry reloc_names[] =
14596{
14597 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
14598 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
14599 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
14600 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
14601 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
14602 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
14603 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
14604 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
14605 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
14606 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
14607 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}
14608};
14609#endif
14610
14611/* Table of all conditional affixes. 0xF is not defined as a condition code. */
14612static const struct asm_cond conds[] =
14613{
14614 {"eq", 0x0},
14615 {"ne", 0x1},
14616 {"cs", 0x2}, {"hs", 0x2},
14617 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14618 {"mi", 0x4},
14619 {"pl", 0x5},
14620 {"vs", 0x6},
14621 {"vc", 0x7},
14622 {"hi", 0x8},
14623 {"ls", 0x9},
14624 {"ge", 0xa},
14625 {"lt", 0xb},
14626 {"gt", 0xc},
14627 {"le", 0xd},
14628 {"al", 0xe}
14629};
14630
14631static struct asm_barrier_opt barrier_opt_names[] =
14632{
14633 { "sy", 0xf },
14634 { "un", 0x7 },
14635 { "st", 0xe },
14636 { "unst", 0x6 }
14637};
14638
14639/* Table of ARM-format instructions. */
14640
14641/* Macros for gluing together operand strings. N.B. In all cases
14642 other than OPS0, the trailing OP_stop comes from default
14643 zero-initialization of the unspecified elements of the array. */
14644#define OPS0() { OP_stop, }
14645#define OPS1(a) { OP_##a, }
14646#define OPS2(a,b) { OP_##a,OP_##b, }
14647#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14648#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14649#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14650#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14651
14652/* These macros abstract out the exact format of the mnemonic table and
14653 save some repeated characters. */
14654
14655/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14656#define TxCE(mnem, op, top, nops, ops, ae, te) \
14657 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14658 THUMB_VARIANT, do_##ae, do_##te }
14659
14660/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14661 a T_MNEM_xyz enumerator. */
14662#define TCE(mnem, aop, top, nops, ops, ae, te) \
14663 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14664#define tCE(mnem, aop, top, nops, ops, ae, te) \
14665 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14666
14667/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14668 infix after the third character. */
14669#define TxC3(mnem, op, top, nops, ops, ae, te) \
14670 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14671 THUMB_VARIANT, do_##ae, do_##te }
14672#define TxC3w(mnem, op, top, nops, ops, ae, te) \
14673 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14674 THUMB_VARIANT, do_##ae, do_##te }
14675#define TC3(mnem, aop, top, nops, ops, ae, te) \
14676 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14677#define TC3w(mnem, aop, top, nops, ops, ae, te) \
14678 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14679#define tC3(mnem, aop, top, nops, ops, ae, te) \
14680 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14681#define tC3w(mnem, aop, top, nops, ops, ae, te) \
14682 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14683
14684/* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14685 appear in the condition table. */
14686#define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14687 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14688 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14689
14690#define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14691 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14692 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14693 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14694 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14695 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14696 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14697 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14698 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14699 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14700 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14701 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14702 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14703 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14704 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14705 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14706 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14707 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14708 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14709 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14710
14711#define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14712 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14713#define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14714 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14715
14716/* Mnemonic that cannot be conditionalized. The ARM condition-code
14717 field is still 0xE. Many of the Thumb variants can be executed
14718 conditionally, so this is checked separately. */
14719#define TUE(mnem, op, top, nops, ops, ae, te) \
14720 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14721 THUMB_VARIANT, do_##ae, do_##te }
14722
14723/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14724 condition code field. */
14725#define TUF(mnem, op, top, nops, ops, ae, te) \
14726 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14727 THUMB_VARIANT, do_##ae, do_##te }
14728
14729/* ARM-only variants of all the above. */
14730#define CE(mnem, op, nops, ops, ae) \
14731 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14732
14733#define C3(mnem, op, nops, ops, ae) \
14734 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14735
14736/* Legacy mnemonics that always have conditional infix after the third
14737 character. */
14738#define CL(mnem, op, nops, ops, ae) \
14739 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14740 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14741
14742/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14743#define cCE(mnem, op, nops, ops, ae) \
14744 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14745
14746/* Legacy coprocessor instructions where conditional infix and conditional
14747 suffix are ambiguous. For consistency this includes all FPA instructions,
14748 not just the potentially ambiguous ones. */
14749#define cCL(mnem, op, nops, ops, ae) \
14750 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14751 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14752
14753/* Coprocessor, takes either a suffix or a position-3 infix
14754 (for an FPA corner case). */
14755#define C3E(mnem, op, nops, ops, ae) \
14756 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14757 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14758
14759#define xCM_(m1, m2, m3, op, nops, ops, ae) \
14760 { #m1 #m2 #m3, OPS##nops ops, \
14761 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14762 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14763
14764#define CM(m1, m2, op, nops, ops, ae) \
14765 xCM_(m1, , m2, op, nops, ops, ae), \
14766 xCM_(m1, eq, m2, op, nops, ops, ae), \
14767 xCM_(m1, ne, m2, op, nops, ops, ae), \
14768 xCM_(m1, cs, m2, op, nops, ops, ae), \
14769 xCM_(m1, hs, m2, op, nops, ops, ae), \
14770 xCM_(m1, cc, m2, op, nops, ops, ae), \
14771 xCM_(m1, ul, m2, op, nops, ops, ae), \
14772 xCM_(m1, lo, m2, op, nops, ops, ae), \
14773 xCM_(m1, mi, m2, op, nops, ops, ae), \
14774 xCM_(m1, pl, m2, op, nops, ops, ae), \
14775 xCM_(m1, vs, m2, op, nops, ops, ae), \
14776 xCM_(m1, vc, m2, op, nops, ops, ae), \
14777 xCM_(m1, hi, m2, op, nops, ops, ae), \
14778 xCM_(m1, ls, m2, op, nops, ops, ae), \
14779 xCM_(m1, ge, m2, op, nops, ops, ae), \
14780 xCM_(m1, lt, m2, op, nops, ops, ae), \
14781 xCM_(m1, gt, m2, op, nops, ops, ae), \
14782 xCM_(m1, le, m2, op, nops, ops, ae), \
14783 xCM_(m1, al, m2, op, nops, ops, ae)
14784
14785#define UE(mnem, op, nops, ops, ae) \
14786 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14787
14788#define UF(mnem, op, nops, ops, ae) \
14789 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14790
14791/* Neon data-processing. ARM versions are unconditional with cond=0xf.
14792 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14793 use the same encoding function for each. */
14794#define NUF(mnem, op, nops, ops, enc) \
14795 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14796 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14797
14798/* Neon data processing, version which indirects through neon_enc_tab for
14799 the various overloaded versions of opcodes. */
14800#define nUF(mnem, op, nops, ops, enc) \
14801 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14802 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14803
14804/* Neon insn with conditional suffix for the ARM version, non-overloaded
14805 version. */
14806#define NCE_tag(mnem, op, nops, ops, enc, tag) \
14807 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14808 THUMB_VARIANT, do_##enc, do_##enc }
14809
14810#define NCE(mnem, op, nops, ops, enc) \
14811 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14812
14813#define NCEF(mnem, op, nops, ops, enc) \
14814 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14815
14816/* Neon insn with conditional suffix for the ARM version, overloaded types. */
14817#define nCE_tag(mnem, op, nops, ops, enc, tag) \
14818 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14819 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14820
14821#define nCE(mnem, op, nops, ops, enc) \
14822 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14823
14824#define nCEF(mnem, op, nops, ops, enc) \
14825 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14826
14827#define do_0 0
14828
14829/* Thumb-only, unconditional. */
14830#define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14831
14832static const struct asm_opcode insns[] =
14833{
14834#define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14835#define THUMB_VARIANT &arm_ext_v4t
14836 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c),
14837 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c),
14838 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c),
14839 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c),
14840 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub),
14841 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub),
14842 tCE(add, 0800000, add, 3, (RR, oRR, SHG), arit, t_add_sub),
14843 tC3(adds, 0900000, adds, 3, (RR, oRR, SHG), arit, t_add_sub),
14844 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c),
14845 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c),
14846 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3),
14847 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3),
14848 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c),
14849 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c),
14850 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3),
14851 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3),
14852
14853 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14854 for setting PSR flag bits. They are obsolete in V6 and do not
14855 have Thumb equivalents. */
14856 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
14857 tC3w(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
14858 CL(tstp, 110f000, 2, (RR, SH), cmp),
14859 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
14860 tC3w(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
14861 CL(cmpp, 150f000, 2, (RR, SH), cmp),
14862 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
14863 tC3w(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
14864 CL(cmnp, 170f000, 2, (RR, SH), cmp),
14865
14866 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp),
14867 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp),
14868 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst),
14869 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst),
14870
14871 tCE(ldr, 4100000, ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
14872 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDRGLDR),ldst, t_ldst),
14873 tCE(str, 4000000, str, 2, (RR, ADDRGLDR),ldst, t_ldst),
14874 tC3(strb, 4400000, strb, 2, (RR, ADDRGLDR),ldst, t_ldst),
14875
14876 tCE(stm, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14877 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14878 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14879 tCE(ldm, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14880 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14881 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14882
14883 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi),
14884 TCE(svc, f000000, df00, 1, (EXPi), swi, t_swi),
14885 tCE(b, a000000, b, 1, (EXPr), branch, t_branch),
14886 TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23),
14887
14888 /* Pseudo ops. */
14889 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr),
14890 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
14891 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop),
14892
14893 /* Thumb-compatibility pseudo ops. */
14894 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift),
14895 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift),
14896 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift),
14897 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift),
14898 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift),
14899 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift),
14900 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift),
14901 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift),
14902 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg),
14903 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg),
14904 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop),
14905 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop),
14906
14907 /* These may simplify to neg. */
14908 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
14909 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
14910
14911 TCE(rrx, 1a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rd_rm),
14912 TCE(rrxs, 1b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rd_rm),
14913
14914#undef THUMB_VARIANT
14915#define THUMB_VARIANT &arm_ext_v6
14916 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
14917
14918 /* V1 instructions with no Thumb analogue prior to V6T2. */
14919#undef THUMB_VARIANT
14920#define THUMB_VARIANT &arm_ext_v6t2
14921 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
14922 TC3w(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
14923 CL(teqp, 130f000, 2, (RR, SH), cmp),
14924
14925 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt),
14926 TC3(ldrbt, 4700000, f8100e00, 2, (RR, ADDR), ldstt, t_ldstt),
14927 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt),
14928 TC3(strbt, 4600000, f8000e00, 2, (RR, ADDR), ldstt, t_ldstt),
14929
14930 TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14931 TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14932
14933 TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14934 TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14935
14936 /* V1 instructions with no Thumb analogue at all. */
14937 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit),
14938 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
14939
14940 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
14941 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
14942 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
14943 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
14944 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
14945 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
14946 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
14947 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
14948
14949#undef ARM_VARIANT
14950#define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
14951#undef THUMB_VARIANT
14952#define THUMB_VARIANT &arm_ext_v4t
14953 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
14954 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
14955
14956#undef THUMB_VARIANT
14957#define THUMB_VARIANT &arm_ext_v6t2
14958 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
14959 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
14960
14961 /* Generic coprocessor instructions. */
14962 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
14963 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
14964 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
14965 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
14966 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
14967 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
14968 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
14969
14970#undef ARM_VARIANT
14971#define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
14972 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
14973 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
14974
14975#undef ARM_VARIANT
14976#define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
14977 TCE(mrs, 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs),
14978 TCE(msr, 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr),
14979
14980#undef ARM_VARIANT
14981#define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
14982 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
14983 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
14984 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
14985 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
14986 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
14987 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
14988 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
14989 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
14990
14991#undef ARM_VARIANT
14992#define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
14993#undef THUMB_VARIANT
14994#define THUMB_VARIANT &arm_ext_v4t
14995 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
14996 tC3(strh, 00000b0, strh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
14997 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
14998 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
14999 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15000 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15001
15002#undef ARM_VARIANT
15003#define ARM_VARIANT &arm_ext_v4t_5
15004 /* ARM Architecture 4T. */
15005 /* Note: bx (and blx) are required on V5, even if the processor does
15006 not support Thumb. */
15007 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx),
15008
15009#undef ARM_VARIANT
15010#define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
15011#undef THUMB_VARIANT
15012#define THUMB_VARIANT &arm_ext_v5t
15013 /* Note: blx has 2 variants; the .value coded here is for
15014 BLX(2). Only this variant has conditional execution. */
15015 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
15016 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
15017
15018#undef THUMB_VARIANT
15019#define THUMB_VARIANT &arm_ext_v6t2
15020 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
15021 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15022 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15023 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15024 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15025 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
15026 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
15027 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
15028
15029#undef ARM_VARIANT
15030#define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
15031 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15032 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15033 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15034 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15035
15036 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15037 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15038
15039 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15040 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15041 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15042 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15043
15044 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15045 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15046 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15047 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15048
15049 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15050 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15051
15052 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15053 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15054 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15055 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15056
15057#undef ARM_VARIANT
15058#define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
15059 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld),
15060 TC3(ldrd, 00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
15061 TC3(strd, 00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
15062
15063 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15064 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15065
15066#undef ARM_VARIANT
15067#define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
15068 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
15069
15070#undef ARM_VARIANT
15071#define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
15072#undef THUMB_VARIANT
15073#define THUMB_VARIANT &arm_ext_v6
15074 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
15075 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
15076 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
15077 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
15078 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
15079 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15080 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15081 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15082 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15083 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend),
15084
15085#undef THUMB_VARIANT
15086#define THUMB_VARIANT &arm_ext_v6t2
15087 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex),
15088 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex),
15089 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15090 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15091
15092 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
15093 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
15094
15095/* ARM V6 not included in V7M (eg. integer SIMD). */
15096#undef THUMB_VARIANT
15097#define THUMB_VARIANT &arm_ext_v6_notm
15098 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, t_cps),
15099 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
15100 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
15101 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15102 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15103 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15104 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15105 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15106 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15107 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15108 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15109 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15110 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15111 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15112 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15113 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15114 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15115 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15116 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15117 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15118 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15119 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15120 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15121 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15122 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15123 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15124 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15125 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15126 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15127 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15128 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15129 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15130 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15131 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15132 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15133 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15134 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15135 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15136 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15137 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe),
15138 UF(rfeib, 9900a00, 1, (RRw), rfe),
15139 UF(rfeda, 8100a00, 1, (RRw), rfe),
15140 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe),
15141 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe),
15142 UF(rfefa, 9900a00, 1, (RRw), rfe),
15143 UF(rfeea, 8100a00, 1, (RRw), rfe),
15144 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe),
15145 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15146 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15147 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15148 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15149 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15150 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15151 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15152 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15153 TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15154 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15155 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15156 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15157 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15158 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15159 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15160 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15161 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15162 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15163 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15164 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15165 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15166 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15167 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15168 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15169 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15170 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15171 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15172 TUF(srsia, 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
15173 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
15174 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
15175 TUF(srsdb, 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
15176 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
15177 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
15178 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15179 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15180 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
15181
15182#undef ARM_VARIANT
15183#define ARM_VARIANT &arm_ext_v6k
15184#undef THUMB_VARIANT
15185#define THUMB_VARIANT &arm_ext_v6k
15186 tCE(yield, 320f001, yield, 0, (), noargs, t_hint),
15187 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint),
15188 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint),
15189 tCE(sev, 320f004, sev, 0, (), noargs, t_hint),
15190
15191#undef THUMB_VARIANT
15192#define THUMB_VARIANT &arm_ext_v6_notm
15193 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd),
15194 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd),
15195
15196#undef THUMB_VARIANT
15197#define THUMB_VARIANT &arm_ext_v6t2
15198 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
15199 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
15200 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
15201 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
15202 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
15203
15204#undef ARM_VARIANT
15205#define ARM_VARIANT &arm_ext_v6z
15206 TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc),
15207
15208#undef ARM_VARIANT
15209#define ARM_VARIANT &arm_ext_v6t2
15210 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
15211 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
15212 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
15213 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
15214
15215 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
15216 TCE(movw, 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
15217 TCE(movt, 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
15218 TCE(rbit, 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
15219
15220 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15221 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15222 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15223 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15224
15225 UT(cbnz, b900, 2, (RR, EXP), t_cbz),
15226 UT(cbz, b100, 2, (RR, EXP), t_cbz),
15227 /* ARM does not really have an IT instruction, so always allow it. */
15228#undef ARM_VARIANT
15229#define ARM_VARIANT &arm_ext_v1
15230 TUE(it, 0, bf08, 1, (COND), it, t_it),
15231 TUE(itt, 0, bf0c, 1, (COND), it, t_it),
15232 TUE(ite, 0, bf04, 1, (COND), it, t_it),
15233 TUE(ittt, 0, bf0e, 1, (COND), it, t_it),
15234 TUE(itet, 0, bf06, 1, (COND), it, t_it),
15235 TUE(itte, 0, bf0a, 1, (COND), it, t_it),
15236 TUE(itee, 0, bf02, 1, (COND), it, t_it),
15237 TUE(itttt, 0, bf0f, 1, (COND), it, t_it),
15238 TUE(itett, 0, bf07, 1, (COND), it, t_it),
15239 TUE(ittet, 0, bf0b, 1, (COND), it, t_it),
15240 TUE(iteet, 0, bf03, 1, (COND), it, t_it),
15241 TUE(ittte, 0, bf0d, 1, (COND), it, t_it),
15242 TUE(itete, 0, bf05, 1, (COND), it, t_it),
15243 TUE(ittee, 0, bf09, 1, (COND), it, t_it),
15244 TUE(iteee, 0, bf01, 1, (COND), it, t_it),
15245
15246 /* Thumb2 only instructions. */
15247#undef ARM_VARIANT
15248#define ARM_VARIANT NULL
15249
15250 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
15251 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
15252 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb),
15253 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb),
15254
15255 /* Thumb-2 hardware division instructions (R and M profiles only). */
15256#undef THUMB_VARIANT
15257#define THUMB_VARIANT &arm_ext_div
15258 TCE(sdiv, 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div),
15259 TCE(udiv, 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div),
15260
15261 /* ARM V7 instructions. */
15262#undef ARM_VARIANT
15263#define ARM_VARIANT &arm_ext_v7
15264#undef THUMB_VARIANT
15265#define THUMB_VARIANT &arm_ext_v7
15266 TUF(pli, 450f000, f910f000, 1, (ADDR), pli, t_pld),
15267 TCE(dbg, 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
15268 TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier),
15269 TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier),
15270 TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier),
15271
15272#undef ARM_VARIANT
15273#define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
15274 cCE(wfs, e200110, 1, (RR), rd),
15275 cCE(rfs, e300110, 1, (RR), rd),
15276 cCE(wfc, e400110, 1, (RR), rd),
15277 cCE(rfc, e500110, 1, (RR), rd),
15278
15279 cCL(ldfs, c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
15280 cCL(ldfd, c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
15281 cCL(ldfe, c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
15282 cCL(ldfp, c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
15283
15284 cCL(stfs, c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
15285 cCL(stfd, c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
15286 cCL(stfe, c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
15287 cCL(stfp, c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
15288
15289 cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm),
15290 cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm),
15291 cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm),
15292 cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm),
15293 cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm),
15294 cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm),
15295 cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm),
15296 cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm),
15297 cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm),
15298 cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm),
15299 cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm),
15300 cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm),
15301
15302 cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm),
15303 cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm),
15304 cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm),
15305 cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm),
15306 cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm),
15307 cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm),
15308 cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm),
15309 cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm),
15310 cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm),
15311 cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm),
15312 cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm),
15313 cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm),
15314
15315 cCL(abss, e208100, 2, (RF, RF_IF), rd_rm),
15316 cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm),
15317 cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm),
15318 cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm),
15319 cCL(absd, e208180, 2, (RF, RF_IF), rd_rm),
15320 cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm),
15321 cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm),
15322 cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm),
15323 cCL(abse, e288100, 2, (RF, RF_IF), rd_rm),
15324 cCL(absep, e288120, 2, (RF, RF_IF), rd_rm),
15325 cCL(absem, e288140, 2, (RF, RF_IF), rd_rm),
15326 cCL(absez, e288160, 2, (RF, RF_IF), rd_rm),
15327
15328 cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm),
15329 cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm),
15330 cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm),
15331 cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm),
15332 cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm),
15333 cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm),
15334 cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm),
15335 cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm),
15336 cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm),
15337 cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm),
15338 cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm),
15339 cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm),
15340
15341 cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm),
15342 cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm),
15343 cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm),
15344 cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm),
15345 cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm),
15346 cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm),
15347 cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm),
15348 cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm),
15349 cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm),
15350 cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm),
15351 cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm),
15352 cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm),
15353
15354 cCL(logs, e508100, 2, (RF, RF_IF), rd_rm),
15355 cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm),
15356 cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm),
15357 cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm),
15358 cCL(logd, e508180, 2, (RF, RF_IF), rd_rm),
15359 cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm),
15360 cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm),
15361 cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm),
15362 cCL(loge, e588100, 2, (RF, RF_IF), rd_rm),
15363 cCL(logep, e588120, 2, (RF, RF_IF), rd_rm),
15364 cCL(logem, e588140, 2, (RF, RF_IF), rd_rm),
15365 cCL(logez, e588160, 2, (RF, RF_IF), rd_rm),
15366
15367 cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm),
15368 cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm),
15369 cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm),
15370 cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm),
15371 cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm),
15372 cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm),
15373 cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm),
15374 cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm),
15375 cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm),
15376 cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm),
15377 cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm),
15378 cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm),
15379
15380 cCL(exps, e708100, 2, (RF, RF_IF), rd_rm),
15381 cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm),
15382 cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm),
15383 cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm),
15384 cCL(expd, e708180, 2, (RF, RF_IF), rd_rm),
15385 cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm),
15386 cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm),
15387 cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm),
15388 cCL(expe, e788100, 2, (RF, RF_IF), rd_rm),
15389 cCL(expep, e788120, 2, (RF, RF_IF), rd_rm),
15390 cCL(expem, e788140, 2, (RF, RF_IF), rd_rm),
15391 cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm),
15392
15393 cCL(sins, e808100, 2, (RF, RF_IF), rd_rm),
15394 cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm),
15395 cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm),
15396 cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm),
15397 cCL(sind, e808180, 2, (RF, RF_IF), rd_rm),
15398 cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm),
15399 cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm),
15400 cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm),
15401 cCL(sine, e888100, 2, (RF, RF_IF), rd_rm),
15402 cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm),
15403 cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm),
15404 cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm),
15405
15406 cCL(coss, e908100, 2, (RF, RF_IF), rd_rm),
15407 cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm),
15408 cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm),
15409 cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm),
15410 cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm),
15411 cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm),
15412 cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm),
15413 cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm),
15414 cCL(cose, e988100, 2, (RF, RF_IF), rd_rm),
15415 cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm),
15416 cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm),
15417 cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm),
15418
15419 cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm),
15420 cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm),
15421 cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm),
15422 cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm),
15423 cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm),
15424 cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm),
15425 cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm),
15426 cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm),
15427 cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm),
15428 cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm),
15429 cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm),
15430 cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm),
15431
15432 cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm),
15433 cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm),
15434 cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm),
15435 cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm),
15436 cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm),
15437 cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm),
15438 cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm),
15439 cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm),
15440 cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm),
15441 cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm),
15442 cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm),
15443 cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm),
15444
15445 cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm),
15446 cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm),
15447 cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm),
15448 cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm),
15449 cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm),
15450 cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm),
15451 cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm),
15452 cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm),
15453 cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm),
15454 cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm),
15455 cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm),
15456 cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm),
15457
15458 cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm),
15459 cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm),
15460 cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm),
15461 cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm),
15462 cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm),
15463 cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm),
15464 cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm),
15465 cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm),
15466 cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm),
15467 cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm),
15468 cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm),
15469 cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm),
15470
15471 cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm),
15472 cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm),
15473 cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm),
15474 cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm),
15475 cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm),
15476 cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm),
15477 cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm),
15478 cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm),
15479 cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm),
15480 cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm),
15481 cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm),
15482 cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm),
15483
15484 cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm),
15485 cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm),
15486 cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm),
15487 cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm),
15488 cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm),
15489 cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm),
15490 cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm),
15491 cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm),
15492 cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm),
15493 cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm),
15494 cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm),
15495 cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm),
15496
15497 cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
15498 cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
15499 cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
15500 cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
15501 cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
15502 cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15503 cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15504 cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15505 cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
15506 cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
15507 cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
15508 cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
15509
15510 cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
15511 cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
15512 cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
15513 cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
15514 cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
15515 cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15516 cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15517 cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15518 cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
15519 cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
15520 cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
15521 cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
15522
15523 cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
15524 cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
15525 cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
15526 cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
15527 cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
15528 cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15529 cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15530 cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15531 cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
15532 cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
15533 cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
15534 cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
15535
15536 cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
15537 cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
15538 cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
15539 cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
15540 cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
15541 cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15542 cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15543 cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15544 cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
15545 cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
15546 cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
15547 cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
15548
15549 cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
15550 cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
15551 cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
15552 cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
15553 cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
15554 cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15555 cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15556 cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15557 cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
15558 cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
15559 cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
15560 cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
15561
15562 cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
15563 cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
15564 cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
15565 cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
15566 cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
15567 cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15568 cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15569 cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15570 cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
15571 cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
15572 cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
15573 cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
15574
15575 cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
15576 cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
15577 cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
15578 cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
15579 cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
15580 cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15581 cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15582 cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15583 cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
15584 cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
15585 cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
15586 cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
15587
15588 cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
15589 cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
15590 cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
15591 cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
15592 cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
15593 cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15594 cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15595 cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15596 cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
15597 cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
15598 cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
15599 cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
15600
15601 cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
15602 cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
15603 cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
15604 cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
15605 cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
15606 cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15607 cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15608 cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15609 cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
15610 cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
15611 cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
15612 cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
15613
15614 cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
15615 cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
15616 cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
15617 cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
15618 cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
15619 cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15620 cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15621 cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15622 cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
15623 cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
15624 cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
15625 cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
15626
15627 cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
15628 cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
15629 cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
15630 cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
15631 cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
15632 cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15633 cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15634 cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15635 cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
15636 cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
15637 cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
15638 cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
15639
15640 cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
15641 cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
15642 cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
15643 cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
15644 cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
15645 cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15646 cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15647 cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15648 cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
15649 cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
15650 cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
15651 cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
15652
15653 cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
15654 cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
15655 cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
15656 cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
15657 cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
15658 cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15659 cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15660 cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15661 cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
15662 cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
15663 cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
15664 cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
15665
15666 cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
15667 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
15668 cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
15669 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
15670
15671 cCL(flts, e000110, 2, (RF, RR), rn_rd),
15672 cCL(fltsp, e000130, 2, (RF, RR), rn_rd),
15673 cCL(fltsm, e000150, 2, (RF, RR), rn_rd),
15674 cCL(fltsz, e000170, 2, (RF, RR), rn_rd),
15675 cCL(fltd, e000190, 2, (RF, RR), rn_rd),
15676 cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd),
15677 cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd),
15678 cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd),
15679 cCL(flte, e080110, 2, (RF, RR), rn_rd),
15680 cCL(fltep, e080130, 2, (RF, RR), rn_rd),
15681 cCL(fltem, e080150, 2, (RF, RR), rn_rd),
15682 cCL(fltez, e080170, 2, (RF, RR), rn_rd),
15683
15684 /* The implementation of the FIX instruction is broken on some
15685 assemblers, in that it accepts a precision specifier as well as a
15686 rounding specifier, despite the fact that this is meaningless.
15687 To be more compatible, we accept it as well, though of course it
15688 does not set any bits. */
15689 cCE(fix, e100110, 2, (RR, RF), rd_rm),
15690 cCL(fixp, e100130, 2, (RR, RF), rd_rm),
15691 cCL(fixm, e100150, 2, (RR, RF), rd_rm),
15692 cCL(fixz, e100170, 2, (RR, RF), rd_rm),
15693 cCL(fixsp, e100130, 2, (RR, RF), rd_rm),
15694 cCL(fixsm, e100150, 2, (RR, RF), rd_rm),
15695 cCL(fixsz, e100170, 2, (RR, RF), rd_rm),
15696 cCL(fixdp, e100130, 2, (RR, RF), rd_rm),
15697 cCL(fixdm, e100150, 2, (RR, RF), rd_rm),
15698 cCL(fixdz, e100170, 2, (RR, RF), rd_rm),
15699 cCL(fixep, e100130, 2, (RR, RF), rd_rm),
15700 cCL(fixem, e100150, 2, (RR, RF), rd_rm),
15701 cCL(fixez, e100170, 2, (RR, RF), rd_rm),
15702
15703 /* Instructions that were new with the real FPA, call them V2. */
15704#undef ARM_VARIANT
15705#define ARM_VARIANT &fpu_fpa_ext_v2
15706 cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15707 cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15708 cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15709 cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15710 cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15711 cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15712
15713#undef ARM_VARIANT
15714#define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15715 /* Moves and type conversions. */
15716 cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
15717 cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
15718 cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
15719 cCE(fmstat, ef1fa10, 0, (), noargs),
15720 cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
15721 cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
15722 cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
15723 cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
15724 cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
15725 cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
15726 cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn),
15727 cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
15728
15729 /* Memory operations. */
15730 cCE(flds, d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
15731 cCE(fsts, d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
15732 cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15733 cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15734 cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15735 cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15736 cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15737 cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15738 cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15739 cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15740 cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15741 cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15742 cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15743 cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15744 cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15745 cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15746 cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15747 cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15748
15749 /* Monadic operations. */
15750 cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
15751 cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
15752 cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
15753
15754 /* Dyadic operations. */
15755 cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15756 cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15757 cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15758 cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15759 cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15760 cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15761 cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15762 cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15763 cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15764
15765 /* Comparisons. */
15766 cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
15767 cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
15768 cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
15769 cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
15770
15771#undef ARM_VARIANT
15772#define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15773 /* Moves and type conversions. */
15774 cCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
15775 cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
15776 cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
15777 cCE(fmdhr, e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
15778 cCE(fmdlr, e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
15779 cCE(fmrdh, e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
15780 cCE(fmrdl, e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
15781 cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
15782 cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
15783 cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
15784 cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
15785 cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
15786 cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
15787
15788 /* Memory operations. */
15789 cCE(fldd, d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
15790 cCE(fstd, d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
15791 cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15792 cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15793 cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15794 cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15795 cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15796 cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15797 cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15798 cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15799
15800 /* Monadic operations. */
15801 cCE(fabsd, eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
15802 cCE(fnegd, eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
15803 cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
15804
15805 /* Dyadic operations. */
15806 cCE(faddd, e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15807 cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15808 cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15809 cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15810 cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15811 cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15812 cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15813 cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15814 cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15815
15816 /* Comparisons. */
15817 cCE(fcmpd, eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
15818 cCE(fcmpzd, eb50b40, 1, (RVD), vfp_dp_rd),
15819 cCE(fcmped, eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
15820 cCE(fcmpezd, eb50bc0, 1, (RVD), vfp_dp_rd),
15821
15822#undef ARM_VARIANT
15823#define ARM_VARIANT &fpu_vfp_ext_v2
15824 cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
15825 cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
15826 cCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
15827 cCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
15828
15829/* Instructions which may belong to either the Neon or VFP instruction sets.
15830 Individual encoder functions perform additional architecture checks. */
15831#undef ARM_VARIANT
15832#define ARM_VARIANT &fpu_vfp_ext_v1xd
15833#undef THUMB_VARIANT
15834#define THUMB_VARIANT &fpu_vfp_ext_v1xd
15835 /* These mnemonics are unique to VFP. */
15836 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
15837 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
15838 nCE(vnmul, vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
15839 nCE(vnmla, vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
15840 nCE(vnmls, vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
15841 nCE(vcmp, vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
15842 nCE(vcmpe, vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
15843 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
15844 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
15845 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
15846
15847 /* Mnemonics shared by Neon and VFP. */
15848 nCEF(vmul, vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
15849 nCEF(vmla, vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
15850 nCEF(vmls, vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
15851
15852 nCEF(vadd, vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
15853 nCEF(vsub, vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
15854
15855 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
15856 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
15857
15858 NCE(vldm, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15859 NCE(vldmia, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15860 NCE(vldmdb, d100b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15861 NCE(vstm, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15862 NCE(vstmia, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15863 NCE(vstmdb, d000b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15864 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
15865 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
15866
15867 nCEF(vcvt, vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt),
15868
15869 /* NOTE: All VMOV encoding is special-cased! */
15870 NCE(vmov, 0, 1, (VMOV), neon_mov),
15871 NCE(vmovq, 0, 1, (VMOV), neon_mov),
15872
15873#undef THUMB_VARIANT
15874#define THUMB_VARIANT &fpu_neon_ext_v1
15875#undef ARM_VARIANT
15876#define ARM_VARIANT &fpu_neon_ext_v1
15877 /* Data processing with three registers of the same length. */
15878 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15879 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
15880 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
15881 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
15882 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
15883 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
15884 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
15885 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
15886 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
15887 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15888 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
15889 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
15890 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
15891 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
15892 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
15893 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
15894 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
15895 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
15896 /* If not immediate, fall back to neon_dyadic_i64_su.
15897 shl_imm should accept I8 I16 I32 I64,
15898 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15899 nUF(vshl, vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
15900 nUF(vshlq, vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
15901 nUF(vqshl, vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
15902 nUF(vqshlq, vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
15903 /* Logic ops, types optional & ignored. */
15904 nUF(vand, vand, 2, (RNDQ, NILO), neon_logic),
15905 nUF(vandq, vand, 2, (RNQ, NILO), neon_logic),
15906 nUF(vbic, vbic, 2, (RNDQ, NILO), neon_logic),
15907 nUF(vbicq, vbic, 2, (RNQ, NILO), neon_logic),
15908 nUF(vorr, vorr, 2, (RNDQ, NILO), neon_logic),
15909 nUF(vorrq, vorr, 2, (RNQ, NILO), neon_logic),
15910 nUF(vorn, vorn, 2, (RNDQ, NILO), neon_logic),
15911 nUF(vornq, vorn, 2, (RNQ, NILO), neon_logic),
15912 nUF(veor, veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
15913 nUF(veorq, veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
15914 /* Bitfield ops, untyped. */
15915 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
15916 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
15917 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
15918 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
15919 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
15920 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
15921 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15922 nUF(vabd, vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
15923 nUF(vabdq, vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
15924 nUF(vmax, vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
15925 nUF(vmaxq, vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
15926 nUF(vmin, vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
15927 nUF(vminq, vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
15928 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15929 back to neon_dyadic_if_su. */
15930 nUF(vcge, vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
15931 nUF(vcgeq, vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
15932 nUF(vcgt, vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
15933 nUF(vcgtq, vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
15934 nUF(vclt, vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
15935 nUF(vcltq, vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
15936 nUF(vcle, vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
15937 nUF(vcleq, vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
15938 /* Comparison. Type I8 I16 I32 F32. */
15939 nUF(vceq, vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
15940 nUF(vceqq, vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
15941 /* As above, D registers only. */
15942 nUF(vpmax, vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
15943 nUF(vpmin, vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
15944 /* Int and float variants, signedness unimportant. */
15945 nUF(vmlaq, vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
15946 nUF(vmlsq, vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
15947 nUF(vpadd, vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
15948 /* Add/sub take types I8 I16 I32 I64 F32. */
15949 nUF(vaddq, vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
15950 nUF(vsubq, vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
15951 /* vtst takes sizes 8, 16, 32. */
15952 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
15953 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
15954 /* VMUL takes I8 I16 I32 F32 P8. */
15955 nUF(vmulq, vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
15956 /* VQD{R}MULH takes S16 S32. */
15957 nUF(vqdmulh, vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
15958 nUF(vqdmulhq, vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
15959 nUF(vqrdmulh, vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
15960 nUF(vqrdmulhq, vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
15961 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
15962 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
15963 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
15964 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
15965 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
15966 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
15967 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
15968 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
15969 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
15970 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
15971 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
15972 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
15973
15974 /* Two address, int/float. Types S8 S16 S32 F32. */
15975 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
15976 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
15977
15978 /* Data processing with two registers and a shift amount. */
15979 /* Right shifts, and variants with rounding.
15980 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
15981 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
15982 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
15983 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
15984 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
15985 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
15986 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
15987 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
15988 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
15989 /* Shift and insert. Sizes accepted 8 16 32 64. */
15990 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
15991 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
15992 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
15993 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
15994 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
15995 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
15996 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
15997 /* Right shift immediate, saturating & narrowing, with rounding variants.
15998 Types accepted S16 S32 S64 U16 U32 U64. */
15999 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
16000 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
16001 /* As above, unsigned. Types accepted S16 S32 S64. */
16002 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
16003 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
16004 /* Right shift narrowing. Types accepted I16 I32 I64. */
16005 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
16006 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
16007 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
16008 nUF(vshll, vshll, 3, (RNQ, RND, I32), neon_shll),
16009 /* CVT with optional immediate for fixed-point variant. */
16010 nUF(vcvtq, vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
16011
16012 nUF(vmvn, vmvn, 2, (RNDQ, RNDQ_IMVNb), neon_mvn),
16013 nUF(vmvnq, vmvn, 2, (RNQ, RNDQ_IMVNb), neon_mvn),
16014
16015 /* Data processing, three registers of different lengths. */
16016 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
16017 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
16018 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
16019 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
16020 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
16021 /* If not scalar, fall back to neon_dyadic_long.
16022 Vector types as above, scalar types S16 S32 U16 U32. */
16023 nUF(vmlal, vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
16024 nUF(vmlsl, vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
16025 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
16026 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
16027 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
16028 /* Dyadic, narrowing insns. Types I16 I32 I64. */
16029 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16030 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16031 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16032 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16033 /* Saturating doubling multiplies. Types S16 S32. */
16034 nUF(vqdmlal, vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
16035 nUF(vqdmlsl, vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
16036 nUF(vqdmull, vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
16037 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
16038 S16 S32 U16 U32. */
16039 nUF(vmull, vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
16040
16041 /* Extract. Size 8. */
16042 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
16043 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
16044
16045 /* Two registers, miscellaneous. */
16046 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
16047 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
16048 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
16049 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
16050 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
16051 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
16052 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
16053 /* Vector replicate. Sizes 8 16 32. */
16054 nCE(vdup, vdup, 2, (RNDQ, RR_RNSC), neon_dup),
16055 nCE(vdupq, vdup, 2, (RNQ, RR_RNSC), neon_dup),
16056 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
16057 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
16058 /* VMOVN. Types I16 I32 I64. */
16059 nUF(vmovn, vmovn, 2, (RND, RNQ), neon_movn),
16060 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
16061 nUF(vqmovn, vqmovn, 2, (RND, RNQ), neon_qmovn),
16062 /* VQMOVUN. Types S16 S32 S64. */
16063 nUF(vqmovun, vqmovun, 2, (RND, RNQ), neon_qmovun),
16064 /* VZIP / VUZP. Sizes 8 16 32. */
16065 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
16066 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
16067 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
16068 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
16069 /* VQABS / VQNEG. Types S8 S16 S32. */
16070 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
16071 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
16072 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
16073 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
16074 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
16075 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
16076 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
16077 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
16078 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
16079 /* Reciprocal estimates. Types U32 F32. */
16080 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
16081 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
16082 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
16083 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
16084 /* VCLS. Types S8 S16 S32. */
16085 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
16086 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
16087 /* VCLZ. Types I8 I16 I32. */
16088 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
16089 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
16090 /* VCNT. Size 8. */
16091 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
16092 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
16093 /* Two address, untyped. */
16094 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
16095 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
16096 /* VTRN. Sizes 8 16 32. */
16097 nUF(vtrn, vtrn, 2, (RNDQ, RNDQ), neon_trn),
16098 nUF(vtrnq, vtrn, 2, (RNQ, RNQ), neon_trn),
16099
16100 /* Table lookup. Size 8. */
16101 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
16102 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
16103
16104#undef THUMB_VARIANT
16105#define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
16106#undef ARM_VARIANT
16107#define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
16108 /* Neon element/structure load/store. */
16109 nUF(vld1, vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
16110 nUF(vst1, vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
16111 nUF(vld2, vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
16112 nUF(vst2, vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
16113 nUF(vld3, vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
16114 nUF(vst3, vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
16115 nUF(vld4, vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
16116 nUF(vst4, vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
16117
16118#undef THUMB_VARIANT
16119#define THUMB_VARIANT &fpu_vfp_ext_v3
16120#undef ARM_VARIANT
16121#define ARM_VARIANT &fpu_vfp_ext_v3
16122 cCE(fconsts, eb00a00, 2, (RVS, I255), vfp_sp_const),
16123 cCE(fconstd, eb00b00, 2, (RVD, I255), vfp_dp_const),
16124 cCE(fshtos, eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16125 cCE(fshtod, eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16126 cCE(fsltos, eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16127 cCE(fsltod, eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16128 cCE(fuhtos, ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16129 cCE(fuhtod, ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16130 cCE(fultos, ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16131 cCE(fultod, ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16132 cCE(ftoshs, ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16133 cCE(ftoshd, ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16134 cCE(ftosls, ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16135 cCE(ftosld, ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16136 cCE(ftouhs, ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16137 cCE(ftouhd, ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16138 cCE(ftouls, ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16139 cCE(ftould, ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16140
16141#undef THUMB_VARIANT
16142#undef ARM_VARIANT
16143#define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
16144 cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16145 cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16146 cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16147 cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16148 cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16149 cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16150 cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
16151 cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
16152
16153#undef ARM_VARIANT
16154#define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
16155 cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
16156 cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
16157 cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
16158 cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd),
16159 cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd),
16160 cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd),
16161 cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
16162 cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
16163 cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
16164 cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
16165 cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
16166 cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
16167 cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
16168 cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
16169 cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
16170 cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
16171 cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
16172 cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
16173 cCE(tmcr, e000110, 2, (RIWC_RIWG, RR), rn_rd),
16174 cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
16175 cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16176 cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16177 cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16178 cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16179 cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16180 cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16181 cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
16182 cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
16183 cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
16184 cCE(tmrc, e100110, 2, (RR, RIWC_RIWG), rd_rn),
16185 cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
16186 cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
16187 cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
16188 cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
16189 cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn),
16190 cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn),
16191 cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn),
16192 cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16193 cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16194 cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16195 cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16196 cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16197 cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16198 cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16199 cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16200 cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16201 cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
16202 cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16203 cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16204 cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16205 cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16206 cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16207 cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16208 cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16209 cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16210 cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16211 cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16212 cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16213 cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16214 cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16215 cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16216 cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16217 cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16218 cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16219 cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16220 cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16221 cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16222 cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16223 cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
16224 cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
16225 cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16226 cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16227 cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16228 cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16229 cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16230 cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16231 cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16232 cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16233 cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16234 cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16235 cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16236 cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16237 cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16238 cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16239 cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16240 cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16241 cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16242 cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16243 cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
16244 cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16245 cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16246 cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16247 cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16248 cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16249 cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16250 cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16251 cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16252 cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16253 cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16254 cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16255 cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16256 cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16257 cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16258 cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16259 cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16260 cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16261 cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16262 cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16263 cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16264 cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16265 cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
16266 cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16267 cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16268 cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16269 cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16270 cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16271 cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16272 cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16273 cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16274 cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16275 cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16276 cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16277 cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16278 cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16279 cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16280 cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16281 cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16282 cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16283 cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16284 cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16285 cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16286 cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
16287 cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
16288 cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16289 cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16290 cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16291 cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16292 cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16293 cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16294 cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16295 cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16296 cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16297 cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn),
16298 cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn),
16299 cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn),
16300 cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn),
16301 cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn),
16302 cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn),
16303 cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16304 cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16305 cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16306 cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn),
16307 cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn),
16308 cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn),
16309 cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn),
16310 cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn),
16311 cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn),
16312 cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16313 cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16314 cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16315 cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16316 cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
16317
16318#undef ARM_VARIANT
16319#define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16320 cCE(torvscb, e13f190, 1, (RR), iwmmxt_tandorc),
16321 cCE(torvsch, e53f190, 1, (RR), iwmmxt_tandorc),
16322 cCE(torvscw, e93f190, 1, (RR), iwmmxt_tandorc),
16323 cCE(wabsb, e2001c0, 2, (RIWR, RIWR), rd_rn),
16324 cCE(wabsh, e6001c0, 2, (RIWR, RIWR), rd_rn),
16325 cCE(wabsw, ea001c0, 2, (RIWR, RIWR), rd_rn),
16326 cCE(wabsdiffb, e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16327 cCE(wabsdiffh, e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16328 cCE(wabsdiffw, e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16329 cCE(waddbhusl, e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16330 cCE(waddbhusm, e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16331 cCE(waddhc, e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16332 cCE(waddwc, ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16333 cCE(waddsubhx, ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16334 cCE(wavg4, e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16335 cCE(wavg4r, e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16336 cCE(wmaddsn, ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16337 cCE(wmaddsx, eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16338 cCE(wmaddun, ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16339 cCE(wmaddux, e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16340 cCE(wmerge, e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
16341 cCE(wmiabb, e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16342 cCE(wmiabt, e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16343 cCE(wmiatb, e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16344 cCE(wmiatt, e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16345 cCE(wmiabbn, e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16346 cCE(wmiabtn, e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16347 cCE(wmiatbn, e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16348 cCE(wmiattn, e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16349 cCE(wmiawbb, e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16350 cCE(wmiawbt, e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16351 cCE(wmiawtb, ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16352 cCE(wmiawtt, eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16353 cCE(wmiawbbn, ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16354 cCE(wmiawbtn, ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16355 cCE(wmiawtbn, ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16356 cCE(wmiawttn, ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16357 cCE(wmulsmr, ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16358 cCE(wmulumr, ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16359 cCE(wmulwumr, ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16360 cCE(wmulwsmr, ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16361 cCE(wmulwum, ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16362 cCE(wmulwsm, ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16363 cCE(wmulwl, eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16364 cCE(wqmiabb, e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16365 cCE(wqmiabt, e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16366 cCE(wqmiatb, ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16367 cCE(wqmiatt, eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16368 cCE(wqmiabbn, ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16369 cCE(wqmiabtn, ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16370 cCE(wqmiatbn, ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16371 cCE(wqmiattn, ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16372 cCE(wqmulm, e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16373 cCE(wqmulmr, e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16374 cCE(wqmulwm, ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16375 cCE(wqmulwmr, ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16376 cCE(wsubaddhx, ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16377
16378#undef ARM_VARIANT
16379#define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
16380 cCE(cfldrs, c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
16381 cCE(cfldrd, c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
16382 cCE(cfldr32, c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
16383 cCE(cfldr64, c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
16384 cCE(cfstrs, c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
16385 cCE(cfstrd, c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
16386 cCE(cfstr32, c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
16387 cCE(cfstr64, c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
16388 cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
16389 cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
16390 cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
16391 cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn),
16392 cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd),
16393 cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn),
16394 cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd),
16395 cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn),
16396 cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd),
16397 cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn),
16398 cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn),
16399 cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn),
16400 cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn),
16401 cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn),
16402 cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn),
16403 cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn),
16404 cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn),
16405 cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn),
16406 cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn),
16407 cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn),
16408 cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc),
16409 cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd),
16410 cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn),
16411 cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn),
16412 cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn),
16413 cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn),
16414 cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn),
16415 cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn),
16416 cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn),
16417 cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn),
16418 cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn),
16419 cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn),
16420 cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn),
16421 cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn),
16422 cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple),
16423 cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple),
16424 cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
16425 cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
16426 cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm),
16427 cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
16428 cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
16429 cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
16430 cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn),
16431 cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn),
16432 cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn),
16433 cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn),
16434 cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
16435 cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
16436 cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
16437 cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
16438 cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
16439 cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
16440 cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn),
16441 cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn),
16442 cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn),
16443 cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn),
16444 cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16445 cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
16446 cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16447 cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
16448 cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16449 cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
16450 cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16451 cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16452 cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
16453 cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
16454 cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
16455 cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
16456};
16457#undef ARM_VARIANT
16458#undef THUMB_VARIANT
16459#undef TCE
16460#undef TCM
16461#undef TUE
16462#undef TUF
16463#undef TCC
16464#undef cCE
16465#undef cCL
16466#undef C3E
16467#undef CE
16468#undef CM
16469#undef UE
16470#undef UF
16471#undef UT
16472#undef NUF
16473#undef nUF
16474#undef NCE
16475#undef nCE
16476#undef OPS0
16477#undef OPS1
16478#undef OPS2
16479#undef OPS3
16480#undef OPS4
16481#undef OPS5
16482#undef OPS6
16483#undef do_0
16484
16485/* MD interface: bits in the object file. */
16486
16487/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16488 for use in the a.out file, and stores them in the array pointed to by buf.
16489 This knows about the endian-ness of the target machine and does
16490 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16491 2 (short) and 4 (long) Floating numbers are put out as a series of
16492 LITTLENUMS (shorts, here at least). */
16493
16494void
16495md_number_to_chars (char * buf, valueT val, int n)
16496{
16497 if (target_big_endian)
16498 number_to_chars_bigendian (buf, val, n);
16499 else
16500 number_to_chars_littleendian (buf, val, n);
16501}
16502
16503static valueT
16504md_chars_to_number (char * buf, int n)
16505{
16506 valueT result = 0;
16507 unsigned char * where = (unsigned char *) buf;
16508
16509 if (target_big_endian)
16510 {
16511 while (n--)
16512 {
16513 result <<= 8;
16514 result |= (*where++ & 255);
16515 }
16516 }
16517 else
16518 {
16519 while (n--)
16520 {
16521 result <<= 8;
16522 result |= (where[n] & 255);
16523 }
16524 }
16525
16526 return result;
16527}
16528
16529/* MD interface: Sections. */
16530
16531/* Estimate the size of a frag before relaxing. Assume everything fits in
16532 2 bytes. */
16533
16534int
16535md_estimate_size_before_relax (fragS * fragp,
16536 segT segtype ATTRIBUTE_UNUSED)
16537{
16538 fragp->fr_var = 2;
16539 return 2;
16540}
16541
16542/* Convert a machine dependent frag. */
16543
16544void
16545md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
16546{
16547 unsigned long insn;
16548 unsigned long old_op;
16549 char *buf;
16550 expressionS exp;
16551 fixS *fixp;
16552 int reloc_type;
16553 int pc_rel;
16554 int opcode;
16555
16556 buf = fragp->fr_literal + fragp->fr_fix;
16557
16558 old_op = bfd_get_16(abfd, buf);
16559 if (fragp->fr_symbol) {
16560 exp.X_op = O_symbol;
16561 exp.X_add_symbol = fragp->fr_symbol;
16562 } else {
16563 exp.X_op = O_constant;
16564 }
16565 exp.X_add_number = fragp->fr_offset;
16566 opcode = fragp->fr_subtype;
16567 switch (opcode)
16568 {
16569 case T_MNEM_ldr_pc:
16570 case T_MNEM_ldr_pc2:
16571 case T_MNEM_ldr_sp:
16572 case T_MNEM_str_sp:
16573 case T_MNEM_ldr:
16574 case T_MNEM_ldrb:
16575 case T_MNEM_ldrh:
16576 case T_MNEM_str:
16577 case T_MNEM_strb:
16578 case T_MNEM_strh:
16579 if (fragp->fr_var == 4)
16580 {
16581 insn = THUMB_OP32(opcode);
16582 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
16583 {
16584 insn |= (old_op & 0x700) << 4;
16585 }
16586 else
16587 {
16588 insn |= (old_op & 7) << 12;
16589 insn |= (old_op & 0x38) << 13;
16590 }
16591 insn |= 0x00000c00;
16592 put_thumb32_insn (buf, insn);
16593 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
16594 }
16595 else
16596 {
16597 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
16598 }
16599 pc_rel = (opcode == T_MNEM_ldr_pc2);
16600 break;
16601 case T_MNEM_adr:
16602 if (fragp->fr_var == 4)
16603 {
16604 insn = THUMB_OP32 (opcode);
16605 insn |= (old_op & 0xf0) << 4;
16606 put_thumb32_insn (buf, insn);
16607 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
16608 }
16609 else
16610 {
16611 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
16612 exp.X_add_number -= 4;
16613 }
16614 pc_rel = 1;
16615 break;
16616 case T_MNEM_mov:
16617 case T_MNEM_movs:
16618 case T_MNEM_cmp:
16619 case T_MNEM_cmn:
16620 if (fragp->fr_var == 4)
16621 {
16622 int r0off = (opcode == T_MNEM_mov
16623 || opcode == T_MNEM_movs) ? 0 : 8;
16624 insn = THUMB_OP32 (opcode);
16625 insn = (insn & 0xe1ffffff) | 0x10000000;
16626 insn |= (old_op & 0x700) << r0off;
16627 put_thumb32_insn (buf, insn);
16628 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
16629 }
16630 else
16631 {
16632 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
16633 }
16634 pc_rel = 0;
16635 break;
16636 case T_MNEM_b:
16637 if (fragp->fr_var == 4)
16638 {
16639 insn = THUMB_OP32(opcode);
16640 put_thumb32_insn (buf, insn);
16641 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
16642 }
16643 else
16644 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
16645 pc_rel = 1;
16646 break;
16647 case T_MNEM_bcond:
16648 if (fragp->fr_var == 4)
16649 {
16650 insn = THUMB_OP32(opcode);
16651 insn |= (old_op & 0xf00) << 14;
16652 put_thumb32_insn (buf, insn);
16653 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
16654 }
16655 else
16656 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
16657 pc_rel = 1;
16658 break;
16659 case T_MNEM_add_sp:
16660 case T_MNEM_add_pc:
16661 case T_MNEM_inc_sp:
16662 case T_MNEM_dec_sp:
16663 if (fragp->fr_var == 4)
16664 {
16665 /* ??? Choose between add and addw. */
16666 insn = THUMB_OP32 (opcode);
16667 insn |= (old_op & 0xf0) << 4;
16668 put_thumb32_insn (buf, insn);
16669 if (opcode == T_MNEM_add_pc)
16670 reloc_type = BFD_RELOC_ARM_T32_IMM12;
16671 else
16672 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
16673 }
16674 else
16675 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
16676 pc_rel = 0;
16677 break;
16678
16679 case T_MNEM_addi:
16680 case T_MNEM_addis:
16681 case T_MNEM_subi:
16682 case T_MNEM_subis:
16683 if (fragp->fr_var == 4)
16684 {
16685 insn = THUMB_OP32 (opcode);
16686 insn |= (old_op & 0xf0) << 4;
16687 insn |= (old_op & 0xf) << 16;
16688 put_thumb32_insn (buf, insn);
16689 if (insn & (1 << 20))
16690 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
16691 else
16692 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
16693 }
16694 else
16695 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
16696 pc_rel = 0;
16697 break;
16698 default:
16699 abort();
16700 }
16701 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
16702 reloc_type);
16703 fixp->fx_file = fragp->fr_file;
16704 fixp->fx_line = fragp->fr_line;
16705 fragp->fr_fix += fragp->fr_var;
16706}
16707
16708/* Return the size of a relaxable immediate operand instruction.
16709 SHIFT and SIZE specify the form of the allowable immediate. */
16710static int
16711relax_immediate (fragS *fragp, int size, int shift)
16712{
16713 offsetT offset;
16714 offsetT mask;
16715 offsetT low;
16716
16717 /* ??? Should be able to do better than this. */
16718 if (fragp->fr_symbol)
16719 return 4;
16720
16721 low = (1 << shift) - 1;
16722 mask = (1 << (shift + size)) - (1 << shift);
16723 offset = fragp->fr_offset;
16724 /* Force misaligned offsets to 32-bit variant. */
16725 if (offset & low)
16726 return 4;
16727 if (offset & ~mask)
16728 return 4;
16729 return 2;
16730}
16731
16732/* Get the address of a symbol during relaxation. */
16733static addressT
16734relaxed_symbol_addr(fragS *fragp, long stretch)
16735{
16736 fragS *sym_frag;
16737 addressT addr;
16738 symbolS *sym;
16739
16740 sym = fragp->fr_symbol;
16741 sym_frag = symbol_get_frag (sym);
16742 know (S_GET_SEGMENT (sym) != absolute_section
16743 || sym_frag == &zero_address_frag);
16744 addr = S_GET_VALUE (sym) + fragp->fr_offset;
16745
16746 /* If frag has yet to be reached on this pass, assume it will
16747 move by STRETCH just as we did. If this is not so, it will
16748 be because some frag between grows, and that will force
16749 another pass. */
16750
16751 if (stretch != 0
16752 && sym_frag->relax_marker != fragp->relax_marker)
16753 addr += stretch;
16754
16755 return addr;
16756}
16757
16758/* Return the size of a relaxable adr pseudo-instruction or PC-relative
16759 load. */
16760static int
16761relax_adr (fragS *fragp, asection *sec, long stretch)
16762{
16763 addressT addr;
16764 offsetT val;
16765
16766 /* Assume worst case for symbols not known to be in the same section. */
16767 if (!S_IS_DEFINED(fragp->fr_symbol)
16768 || sec != S_GET_SEGMENT (fragp->fr_symbol))
16769 return 4;
16770
16771 val = relaxed_symbol_addr(fragp, stretch);
16772 addr = fragp->fr_address + fragp->fr_fix;
16773 addr = (addr + 4) & ~3;
16774 /* Force misaligned targets to 32-bit variant. */
16775 if (val & 3)
16776 return 4;
16777 val -= addr;
16778 if (val < 0 || val > 1020)
16779 return 4;
16780 return 2;
16781}
16782
16783/* Return the size of a relaxable add/sub immediate instruction. */
16784static int
16785relax_addsub (fragS *fragp, asection *sec)
16786{
16787 char *buf;
16788 int op;
16789
16790 buf = fragp->fr_literal + fragp->fr_fix;
16791 op = bfd_get_16(sec->owner, buf);
16792 if ((op & 0xf) == ((op >> 4) & 0xf))
16793 return relax_immediate (fragp, 8, 0);
16794 else
16795 return relax_immediate (fragp, 3, 0);
16796}
16797
16798
16799/* Return the size of a relaxable branch instruction. BITS is the
16800 size of the offset field in the narrow instruction. */
16801
16802static int
16803relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
16804{
16805 addressT addr;
16806 offsetT val;
16807 offsetT limit;
16808
16809 /* Assume worst case for symbols not known to be in the same section. */
16810 if (!S_IS_DEFINED(fragp->fr_symbol)
16811 || sec != S_GET_SEGMENT (fragp->fr_symbol))
16812 return 4;
16813
16814 val = relaxed_symbol_addr(fragp, stretch);
16815 addr = fragp->fr_address + fragp->fr_fix + 4;
16816 val -= addr;
16817
16818 /* Offset is a signed value *2 */
16819 limit = 1 << bits;
16820 if (val >= limit || val < -limit)
16821 return 4;
16822 return 2;
16823}
16824
16825
16826/* Relax a machine dependent frag. This returns the amount by which
16827 the current size of the frag should change. */
16828
16829int
16830arm_relax_frag (asection *sec, fragS *fragp, long stretch)
16831{
16832 int oldsize;
16833 int newsize;
16834
16835 oldsize = fragp->fr_var;
16836 switch (fragp->fr_subtype)
16837 {
16838 case T_MNEM_ldr_pc2:
16839 newsize = relax_adr(fragp, sec, stretch);
16840 break;
16841 case T_MNEM_ldr_pc:
16842 case T_MNEM_ldr_sp:
16843 case T_MNEM_str_sp:
16844 newsize = relax_immediate(fragp, 8, 2);
16845 break;
16846 case T_MNEM_ldr:
16847 case T_MNEM_str:
16848 newsize = relax_immediate(fragp, 5, 2);
16849 break;
16850 case T_MNEM_ldrh:
16851 case T_MNEM_strh:
16852 newsize = relax_immediate(fragp, 5, 1);
16853 break;
16854 case T_MNEM_ldrb:
16855 case T_MNEM_strb:
16856 newsize = relax_immediate(fragp, 5, 0);
16857 break;
16858 case T_MNEM_adr:
16859 newsize = relax_adr(fragp, sec, stretch);
16860 break;
16861 case T_MNEM_mov:
16862 case T_MNEM_movs:
16863 case T_MNEM_cmp:
16864 case T_MNEM_cmn:
16865 newsize = relax_immediate(fragp, 8, 0);
16866 break;
16867 case T_MNEM_b:
16868 newsize = relax_branch(fragp, sec, 11, stretch);
16869 break;
16870 case T_MNEM_bcond:
16871 newsize = relax_branch(fragp, sec, 8, stretch);
16872 break;
16873 case T_MNEM_add_sp:
16874 case T_MNEM_add_pc:
16875 newsize = relax_immediate (fragp, 8, 2);
16876 break;
16877 case T_MNEM_inc_sp:
16878 case T_MNEM_dec_sp:
16879 newsize = relax_immediate (fragp, 7, 2);
16880 break;
16881 case T_MNEM_addi:
16882 case T_MNEM_addis:
16883 case T_MNEM_subi:
16884 case T_MNEM_subis:
16885 newsize = relax_addsub (fragp, sec);
16886 break;
16887 default:
16888 abort();
16889 }
16890
16891 fragp->fr_var = newsize;
16892 /* Freeze wide instructions that are at or before the same location as
16893 in the previous pass. This avoids infinite loops.
16894 Don't freeze them unconditionally because targets may be artificialy
16895 misaligned by the expansion of preceeding frags. */
16896 if (stretch <= 0 && newsize > 2)
16897 {
16898 md_convert_frag (sec->owner, sec, fragp);
16899 frag_wane(fragp);
16900 }
16901
16902 return newsize - oldsize;
16903}
16904
16905/* Round up a section size to the appropriate boundary. */
16906
16907valueT
16908md_section_align (segT segment ATTRIBUTE_UNUSED,
16909 valueT size)
16910{
16911#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
16912 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
16913 {
16914 /* For a.out, force the section size to be aligned. If we don't do
16915 this, BFD will align it for us, but it will not write out the
16916 final bytes of the section. This may be a bug in BFD, but it is
16917 easier to fix it here since that is how the other a.out targets
16918 work. */
16919 int align;
16920
16921 align = bfd_get_section_alignment (stdoutput, segment);
16922 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
16923 }
16924#endif
16925
16926 return size;
16927}
16928
16929/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
16930 of an rs_align_code fragment. */
16931
16932void
16933arm_handle_align (fragS * fragP)
16934{
16935 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
16936 static char const thumb_noop[2] = { 0xc0, 0x46 };
16937 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
16938 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
16939
16940 int bytes, fix, noop_size;
16941 char * p;
16942 const char * noop;
16943
16944 if (fragP->fr_type != rs_align_code)
16945 return;
16946
16947 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
16948 p = fragP->fr_literal + fragP->fr_fix;
16949 fix = 0;
16950
16951 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
16952 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
16953
16954 if (fragP->tc_frag_data)
16955 {
16956 if (target_big_endian)
16957 noop = thumb_bigend_noop;
16958 else
16959 noop = thumb_noop;
16960 noop_size = sizeof (thumb_noop);
16961 }
16962 else
16963 {
16964 if (target_big_endian)
16965 noop = arm_bigend_noop;
16966 else
16967 noop = arm_noop;
16968 noop_size = sizeof (arm_noop);
16969 }
16970
16971 if (bytes & (noop_size - 1))
16972 {
16973 fix = bytes & (noop_size - 1);
16974 memset (p, 0, fix);
16975 p += fix;
16976 bytes -= fix;
16977 }
16978
16979 while (bytes >= noop_size)
16980 {
16981 memcpy (p, noop, noop_size);
16982 p += noop_size;
16983 bytes -= noop_size;
16984 fix += noop_size;
16985 }
16986
16987 fragP->fr_fix += fix;
16988 fragP->fr_var = noop_size;
16989}
16990
16991/* Called from md_do_align. Used to create an alignment
16992 frag in a code section. */
16993
16994void
16995arm_frag_align_code (int n, int max)
16996{
16997 char * p;
16998
16999 /* We assume that there will never be a requirement
17000 to support alignments greater than 32 bytes. */
17001 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
17002 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
17003
17004 p = frag_var (rs_align_code,
17005 MAX_MEM_FOR_RS_ALIGN_CODE,
17006 1,
17007 (relax_substateT) max,
17008 (symbolS *) NULL,
17009 (offsetT) n,
17010 (char *) NULL);
17011 *p = 0;
17012}
17013
17014/* Perform target specific initialisation of a frag. */
17015
17016void
17017arm_init_frag (fragS * fragP)
17018{
17019 /* Record whether this frag is in an ARM or a THUMB area. */
17020 fragP->tc_frag_data = thumb_mode;
17021}
17022
17023#ifdef OBJ_ELF
17024/* When we change sections we need to issue a new mapping symbol. */
17025
17026void
17027arm_elf_change_section (void)
17028{
17029 flagword flags;
17030 segment_info_type *seginfo;
17031
17032 /* Link an unlinked unwind index table section to the .text section. */
17033 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
17034 && elf_linked_to_section (now_seg) == NULL)
17035 elf_linked_to_section (now_seg) = text_section;
17036
17037 if (!SEG_NORMAL (now_seg))
17038 return;
17039
17040 flags = bfd_get_section_flags (stdoutput, now_seg);
17041
17042 /* We can ignore sections that only contain debug info. */
17043 if ((flags & SEC_ALLOC) == 0)
17044 return;
17045
17046 seginfo = seg_info (now_seg);
17047 mapstate = seginfo->tc_segment_info_data.mapstate;
17048 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency;
17049}
17050
17051int
17052arm_elf_section_type (const char * str, size_t len)
17053{
17054 if (len == 5 && strncmp (str, "exidx", 5) == 0)
17055 return SHT_ARM_EXIDX;
17056
17057 return -1;
17058}
17059
17060/* Code to deal with unwinding tables. */
17061
17062static void add_unwind_adjustsp (offsetT);
17063
17064/* Cenerate and deferred unwind frame offset. */
17065
17066static void
17067flush_pending_unwind (void)
17068{
17069 offsetT offset;
17070
17071 offset = unwind.pending_offset;
17072 unwind.pending_offset = 0;
17073 if (offset != 0)
17074 add_unwind_adjustsp (offset);
17075}
17076
17077/* Add an opcode to this list for this function. Two-byte opcodes should
17078 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
17079 order. */
17080
17081static void
17082add_unwind_opcode (valueT op, int length)
17083{
17084 /* Add any deferred stack adjustment. */
17085 if (unwind.pending_offset)
17086 flush_pending_unwind ();
17087
17088 unwind.sp_restored = 0;
17089
17090 if (unwind.opcode_count + length > unwind.opcode_alloc)
17091 {
17092 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
17093 if (unwind.opcodes)
17094 unwind.opcodes = xrealloc (unwind.opcodes,
17095 unwind.opcode_alloc);
17096 else
17097 unwind.opcodes = xmalloc (unwind.opcode_alloc);
17098 }
17099 while (length > 0)
17100 {
17101 length--;
17102 unwind.opcodes[unwind.opcode_count] = op & 0xff;
17103 op >>= 8;
17104 unwind.opcode_count++;
17105 }
17106}
17107
17108/* Add unwind opcodes to adjust the stack pointer. */
17109
17110static void
17111add_unwind_adjustsp (offsetT offset)
17112{
17113 valueT op;
17114
17115 if (offset > 0x200)
17116 {
17117 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17118 char bytes[5];
17119 int n;
17120 valueT o;
17121
17122 /* Long form: 0xb2, uleb128. */
17123 /* This might not fit in a word so add the individual bytes,
17124 remembering the list is built in reverse order. */
17125 o = (valueT) ((offset - 0x204) >> 2);
17126 if (o == 0)
17127 add_unwind_opcode (0, 1);
17128
17129 /* Calculate the uleb128 encoding of the offset. */
17130 n = 0;
17131 while (o)
17132 {
17133 bytes[n] = o & 0x7f;
17134 o >>= 7;
17135 if (o)
17136 bytes[n] |= 0x80;
17137 n++;
17138 }
17139 /* Add the insn. */
17140 for (; n; n--)
17141 add_unwind_opcode (bytes[n - 1], 1);
17142 add_unwind_opcode (0xb2, 1);
17143 }
17144 else if (offset > 0x100)
17145 {
17146 /* Two short opcodes. */
17147 add_unwind_opcode (0x3f, 1);
17148 op = (offset - 0x104) >> 2;
17149 add_unwind_opcode (op, 1);
17150 }
17151 else if (offset > 0)
17152 {
17153 /* Short opcode. */
17154 op = (offset - 4) >> 2;
17155 add_unwind_opcode (op, 1);
17156 }
17157 else if (offset < 0)
17158 {
17159 offset = -offset;
17160 while (offset > 0x100)
17161 {
17162 add_unwind_opcode (0x7f, 1);
17163 offset -= 0x100;
17164 }
17165 op = ((offset - 4) >> 2) | 0x40;
17166 add_unwind_opcode (op, 1);
17167 }
17168}
17169
17170/* Finish the list of unwind opcodes for this function. */
17171static void
17172finish_unwind_opcodes (void)
17173{
17174 valueT op;
17175
17176 if (unwind.fp_used)
17177 {
17178 /* Adjust sp as necessary. */
17179 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
17180 flush_pending_unwind ();
17181
17182 /* After restoring sp from the frame pointer. */
17183 op = 0x90 | unwind.fp_reg;
17184 add_unwind_opcode (op, 1);
17185 }
17186 else
17187 flush_pending_unwind ();
17188}
17189
17190
17191/* Start an exception table entry. If idx is nonzero this is an index table
17192 entry. */
17193
17194static void
17195start_unwind_section (const segT text_seg, int idx)
17196{
17197 const char * text_name;
17198 const char * prefix;
17199 const char * prefix_once;
17200 const char * group_name;
17201 size_t prefix_len;
17202 size_t text_len;
17203 char * sec_name;
17204 size_t sec_name_len;
17205 int type;
17206 int flags;
17207 int linkonce;
17208
17209 if (idx)
17210 {
17211 prefix = ELF_STRING_ARM_unwind;
17212 prefix_once = ELF_STRING_ARM_unwind_once;
17213 type = SHT_ARM_EXIDX;
17214 }
17215 else
17216 {
17217 prefix = ELF_STRING_ARM_unwind_info;
17218 prefix_once = ELF_STRING_ARM_unwind_info_once;
17219 type = SHT_PROGBITS;
17220 }
17221
17222 text_name = segment_name (text_seg);
17223 if (streq (text_name, ".text"))
17224 text_name = "";
17225
17226 if (strncmp (text_name, ".gnu.linkonce.t.",
17227 strlen (".gnu.linkonce.t.")) == 0)
17228 {
17229 prefix = prefix_once;
17230 text_name += strlen (".gnu.linkonce.t.");
17231 }
17232
17233 prefix_len = strlen (prefix);
17234 text_len = strlen (text_name);
17235 sec_name_len = prefix_len + text_len;
17236 sec_name = xmalloc (sec_name_len + 1);
17237 memcpy (sec_name, prefix, prefix_len);
17238 memcpy (sec_name + prefix_len, text_name, text_len);
17239 sec_name[prefix_len + text_len] = '\0';
17240
17241 flags = SHF_ALLOC;
17242 linkonce = 0;
17243 group_name = 0;
17244
17245 /* Handle COMDAT group. */
17246 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
17247 {
17248 group_name = elf_group_name (text_seg);
17249 if (group_name == NULL)
17250 {
17251 as_bad ("Group section `%s' has no group signature",
17252 segment_name (text_seg));
17253 ignore_rest_of_line ();
17254 return;
17255 }
17256 flags |= SHF_GROUP;
17257 linkonce = 1;
17258 }
17259
17260 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
17261
17262 /* Set the setion link for index tables. */
17263 if (idx)
17264 elf_linked_to_section (now_seg) = text_seg;
17265}
17266
17267
17268/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17269 personality routine data. Returns zero, or the index table value for
17270 and inline entry. */
17271
17272static valueT
17273create_unwind_entry (int have_data)
17274{
17275 int size;
17276 addressT where;
17277 char *ptr;
17278 /* The current word of data. */
17279 valueT data;
17280 /* The number of bytes left in this word. */
17281 int n;
17282
17283 finish_unwind_opcodes ();
17284
17285 /* Remember the current text section. */
17286 unwind.saved_seg = now_seg;
17287 unwind.saved_subseg = now_subseg;
17288
17289 start_unwind_section (now_seg, 0);
17290
17291 if (unwind.personality_routine == NULL)
17292 {
17293 if (unwind.personality_index == -2)
17294 {
17295 if (have_data)
17296 as_bad (_("handerdata in cantunwind frame"));
17297 return 1; /* EXIDX_CANTUNWIND. */
17298 }
17299
17300 /* Use a default personality routine if none is specified. */
17301 if (unwind.personality_index == -1)
17302 {
17303 if (unwind.opcode_count > 3)
17304 unwind.personality_index = 1;
17305 else
17306 unwind.personality_index = 0;
17307 }
17308
17309 /* Space for the personality routine entry. */
17310 if (unwind.personality_index == 0)
17311 {
17312 if (unwind.opcode_count > 3)
17313 as_bad (_("too many unwind opcodes for personality routine 0"));
17314
17315 if (!have_data)
17316 {
17317 /* All the data is inline in the index table. */
17318 data = 0x80;
17319 n = 3;
17320 while (unwind.opcode_count > 0)
17321 {
17322 unwind.opcode_count--;
17323 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
17324 n--;
17325 }
17326
17327 /* Pad with "finish" opcodes. */
17328 while (n--)
17329 data = (data << 8) | 0xb0;
17330
17331 return data;
17332 }
17333 size = 0;
17334 }
17335 else
17336 /* We get two opcodes "free" in the first word. */
17337 size = unwind.opcode_count - 2;
17338 }
17339 else
17340 /* An extra byte is required for the opcode count. */
17341 size = unwind.opcode_count + 1;
17342
17343 size = (size + 3) >> 2;
17344 if (size > 0xff)
17345 as_bad (_("too many unwind opcodes"));
17346
17347 frag_align (2, 0, 0);
17348 record_alignment (now_seg, 2);
17349 unwind.table_entry = expr_build_dot ();
17350
17351 /* Allocate the table entry. */
17352 ptr = frag_more ((size << 2) + 4);
17353 where = frag_now_fix () - ((size << 2) + 4);
17354
17355 switch (unwind.personality_index)
17356 {
17357 case -1:
17358 /* ??? Should this be a PLT generating relocation? */
17359 /* Custom personality routine. */
17360 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
17361 BFD_RELOC_ARM_PREL31);
17362
17363 where += 4;
17364 ptr += 4;
17365
17366 /* Set the first byte to the number of additional words. */
17367 data = size - 1;
17368 n = 3;
17369 break;
17370
17371 /* ABI defined personality routines. */
17372 case 0:
17373 /* Three opcodes bytes are packed into the first word. */
17374 data = 0x80;
17375 n = 3;
17376 break;
17377
17378 case 1:
17379 case 2:
17380 /* The size and first two opcode bytes go in the first word. */
17381 data = ((0x80 + unwind.personality_index) << 8) | size;
17382 n = 2;
17383 break;
17384
17385 default:
17386 /* Should never happen. */
17387 abort ();
17388 }
17389
17390 /* Pack the opcodes into words (MSB first), reversing the list at the same
17391 time. */
17392 while (unwind.opcode_count > 0)
17393 {
17394 if (n == 0)
17395 {
17396 md_number_to_chars (ptr, data, 4);
17397 ptr += 4;
17398 n = 4;
17399 data = 0;
17400 }
17401 unwind.opcode_count--;
17402 n--;
17403 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
17404 }
17405
17406 /* Finish off the last word. */
17407 if (n < 4)
17408 {
17409 /* Pad with "finish" opcodes. */
17410 while (n--)
17411 data = (data << 8) | 0xb0;
17412
17413 md_number_to_chars (ptr, data, 4);
17414 }
17415
17416 if (!have_data)
17417 {
17418 /* Add an empty descriptor if there is no user-specified data. */
17419 ptr = frag_more (4);
17420 md_number_to_chars (ptr, 0, 4);
17421 }
17422
17423 return 0;
17424}
17425
17426
17427/* Initialize the DWARF-2 unwind information for this procedure. */
17428
17429void
17430tc_arm_frame_initial_instructions (void)
17431{
17432 cfi_add_CFA_def_cfa (REG_SP, 0);
17433}
17434#endif /* OBJ_ELF */
17435
17436/* Convert REGNAME to a DWARF-2 register number. */
17437
17438int
17439tc_arm_regname_to_dw2regnum (char *regname)
17440{
17441 int reg = arm_reg_parse (®name, REG_TYPE_RN);
17442
17443 if (reg == FAIL)
17444 return -1;
17445
17446 return reg;
17447}
17448
17449#ifdef TE_PE
17450void
17451tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
17452{
17453 expressionS expr;
17454
17455 expr.X_op = O_secrel;
17456 expr.X_add_symbol = symbol;
17457 expr.X_add_number = 0;
17458 emit_expr (&expr, size);
17459}
17460#endif
17461
17462/* MD interface: Symbol and relocation handling. */
17463
17464/* Return the address within the segment that a PC-relative fixup is
17465 relative to. For ARM, PC-relative fixups applied to instructions
17466 are generally relative to the location of the fixup plus 8 bytes.
17467 Thumb branches are offset by 4, and Thumb loads relative to PC
17468 require special handling. */
17469
17470long
17471md_pcrel_from_section (fixS * fixP, segT seg)
17472{
17473 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
17474
17475 /* If this is pc-relative and we are going to emit a relocation
17476 then we just want to put out any pipeline compensation that the linker
17477 will need. Otherwise we want to use the calculated base.
17478 For WinCE we skip the bias for externals as well, since this
17479 is how the MS ARM-CE assembler behaves and we want to be compatible. */
17480 if (fixP->fx_pcrel
17481 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
17482 || (arm_force_relocation (fixP)
17483#ifdef TE_WINCE
17484 && !S_IS_EXTERNAL (fixP->fx_addsy)
17485#endif
17486 )))
17487 base = 0;
17488
17489 switch (fixP->fx_r_type)
17490 {
17491 /* PC relative addressing on the Thumb is slightly odd as the
17492 bottom two bits of the PC are forced to zero for the
17493 calculation. This happens *after* application of the
17494 pipeline offset. However, Thumb adrl already adjusts for
17495 this, so we need not do it again. */
17496 case BFD_RELOC_ARM_THUMB_ADD:
17497 return base & ~3;
17498
17499 case BFD_RELOC_ARM_THUMB_OFFSET:
17500 case BFD_RELOC_ARM_T32_OFFSET_IMM:
17501 case BFD_RELOC_ARM_T32_ADD_PC12:
17502 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
17503 return (base + 4) & ~3;
17504
17505 /* Thumb branches are simply offset by +4. */
17506 case BFD_RELOC_THUMB_PCREL_BRANCH7:
17507 case BFD_RELOC_THUMB_PCREL_BRANCH9:
17508 case BFD_RELOC_THUMB_PCREL_BRANCH12:
17509 case BFD_RELOC_THUMB_PCREL_BRANCH20:
17510 case BFD_RELOC_THUMB_PCREL_BRANCH23:
17511 case BFD_RELOC_THUMB_PCREL_BRANCH25:
17512 case BFD_RELOC_THUMB_PCREL_BLX:
17513 return base + 4;
17514
17515 /* ARM mode branches are offset by +8. However, the Windows CE
17516 loader expects the relocation not to take this into account. */
17517 case BFD_RELOC_ARM_PCREL_BRANCH:
17518 case BFD_RELOC_ARM_PCREL_CALL:
17519 case BFD_RELOC_ARM_PCREL_JUMP:
17520 case BFD_RELOC_ARM_PCREL_BLX:
17521 case BFD_RELOC_ARM_PLT32:
17522#ifdef TE_WINCE
17523 /* When handling fixups immediately, because we have already
17524 discovered the value of a symbol, or the address of the frag involved
17525 we must account for the offset by +8, as the OS loader will never see the reloc.
17526 see fixup_segment() in write.c
17527 The S_IS_EXTERNAL test handles the case of global symbols.
17528 Those need the calculated base, not just the pipe compensation the linker will need. */
17529 if (fixP->fx_pcrel
17530 && fixP->fx_addsy != NULL
17531 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
17532 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
17533 return base + 8;
17534 return base;
17535#else
17536 return base + 8;
17537#endif
17538
17539 /* ARM mode loads relative to PC are also offset by +8. Unlike
17540 branches, the Windows CE loader *does* expect the relocation
17541 to take this into account. */
17542 case BFD_RELOC_ARM_OFFSET_IMM:
17543 case BFD_RELOC_ARM_OFFSET_IMM8:
17544 case BFD_RELOC_ARM_HWLITERAL:
17545 case BFD_RELOC_ARM_LITERAL:
17546 case BFD_RELOC_ARM_CP_OFF_IMM:
17547 return base + 8;
17548
17549
17550 /* Other PC-relative relocations are un-offset. */
17551 default:
17552 return base;
17553 }
17554}
17555
17556/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17557 Otherwise we have no need to default values of symbols. */
17558
17559symbolS *
17560md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
17561{
17562#ifdef OBJ_ELF
17563 if (name[0] == '_' && name[1] == 'G'
17564 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
17565 {
17566 if (!GOT_symbol)
17567 {
17568 if (symbol_find (name))
17569 as_bad ("GOT already in the symbol table");
17570
17571 GOT_symbol = symbol_new (name, undefined_section,
17572 (valueT) 0, & zero_address_frag);
17573 }
17574
17575 return GOT_symbol;
17576 }
17577#endif
17578
17579 return 0;
17580}
17581
17582/* Subroutine of md_apply_fix. Check to see if an immediate can be
17583 computed as two separate immediate values, added together. We
17584 already know that this value cannot be computed by just one ARM
17585 instruction. */
17586
17587static unsigned int
17588validate_immediate_twopart (unsigned int val,
17589 unsigned int * highpart)
17590{
17591 unsigned int a;
17592 unsigned int i;
17593
17594 for (i = 0; i < 32; i += 2)
17595 if (((a = rotate_left (val, i)) & 0xff) != 0)
17596 {
17597 if (a & 0xff00)
17598 {
17599 if (a & ~ 0xffff)
17600 continue;
17601 * highpart = (a >> 8) | ((i + 24) << 7);
17602 }
17603 else if (a & 0xff0000)
17604 {
17605 if (a & 0xff000000)
17606 continue;
17607 * highpart = (a >> 16) | ((i + 16) << 7);
17608 }
17609 else
17610 {
17611 assert (a & 0xff000000);
17612 * highpart = (a >> 24) | ((i + 8) << 7);
17613 }
17614
17615 return (a & 0xff) | (i << 7);
17616 }
17617
17618 return FAIL;
17619}
17620
17621static int
17622validate_offset_imm (unsigned int val, int hwse)
17623{
17624 if ((hwse && val > 255) || val > 4095)
17625 return FAIL;
17626 return val;
17627}
17628
17629/* Subroutine of md_apply_fix. Do those data_ops which can take a
17630 negative immediate constant by altering the instruction. A bit of
17631 a hack really.
17632 MOV <-> MVN
17633 AND <-> BIC
17634 ADC <-> SBC
17635 by inverting the second operand, and
17636 ADD <-> SUB
17637 CMP <-> CMN
17638 by negating the second operand. */
17639
17640static int
17641negate_data_op (unsigned long * instruction,
17642 unsigned long value)
17643{
17644 int op, new_inst;
17645 unsigned long negated, inverted;
17646
17647 negated = encode_arm_immediate (-value);
17648 inverted = encode_arm_immediate (~value);
17649
17650 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
17651 switch (op)
17652 {
17653 /* First negates. */
17654 case OPCODE_SUB: /* ADD <-> SUB */
17655 new_inst = OPCODE_ADD;
17656 value = negated;
17657 break;
17658
17659 case OPCODE_ADD:
17660 new_inst = OPCODE_SUB;
17661 value = negated;
17662 break;
17663
17664 case OPCODE_CMP: /* CMP <-> CMN */
17665 new_inst = OPCODE_CMN;
17666 value = negated;
17667 break;
17668
17669 case OPCODE_CMN:
17670 new_inst = OPCODE_CMP;
17671 value = negated;
17672 break;
17673
17674 /* Now Inverted ops. */
17675 case OPCODE_MOV: /* MOV <-> MVN */
17676 new_inst = OPCODE_MVN;
17677 value = inverted;
17678 break;
17679
17680 case OPCODE_MVN:
17681 new_inst = OPCODE_MOV;
17682 value = inverted;
17683 break;
17684
17685 case OPCODE_AND: /* AND <-> BIC */
17686 new_inst = OPCODE_BIC;
17687 value = inverted;
17688 break;
17689
17690 case OPCODE_BIC:
17691 new_inst = OPCODE_AND;
17692 value = inverted;
17693 break;
17694
17695 case OPCODE_ADC: /* ADC <-> SBC */
17696 new_inst = OPCODE_SBC;
17697 value = inverted;
17698 break;
17699
17700 case OPCODE_SBC:
17701 new_inst = OPCODE_ADC;
17702 value = inverted;
17703 break;
17704
17705 /* We cannot do anything. */
17706 default:
17707 return FAIL;
17708 }
17709
17710 if (value == (unsigned) FAIL)
17711 return FAIL;
17712
17713 *instruction &= OPCODE_MASK;
17714 *instruction |= new_inst << DATA_OP_SHIFT;
17715 return value;
17716}
17717
17718/* Like negate_data_op, but for Thumb-2. */
17719
17720static unsigned int
17721thumb32_negate_data_op (offsetT *instruction, unsigned int value)
17722{
17723 int op, new_inst;
17724 int rd;
17725 unsigned int negated, inverted;
17726
17727 negated = encode_thumb32_immediate (-value);
17728 inverted = encode_thumb32_immediate (~value);
17729
17730 rd = (*instruction >> 8) & 0xf;
17731 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
17732 switch (op)
17733 {
17734 /* ADD <-> SUB. Includes CMP <-> CMN. */
17735 case T2_OPCODE_SUB:
17736 new_inst = T2_OPCODE_ADD;
17737 value = negated;
17738 break;
17739
17740 case T2_OPCODE_ADD:
17741 new_inst = T2_OPCODE_SUB;
17742 value = negated;
17743 break;
17744
17745 /* ORR <-> ORN. Includes MOV <-> MVN. */
17746 case T2_OPCODE_ORR:
17747 new_inst = T2_OPCODE_ORN;
17748 value = inverted;
17749 break;
17750
17751 case T2_OPCODE_ORN:
17752 new_inst = T2_OPCODE_ORR;
17753 value = inverted;
17754 break;
17755
17756 /* AND <-> BIC. TST has no inverted equivalent. */
17757 case T2_OPCODE_AND:
17758 new_inst = T2_OPCODE_BIC;
17759 if (rd == 15)
17760 value = FAIL;
17761 else
17762 value = inverted;
17763 break;
17764
17765 case T2_OPCODE_BIC:
17766 new_inst = T2_OPCODE_AND;
17767 value = inverted;
17768 break;
17769
17770 /* ADC <-> SBC */
17771 case T2_OPCODE_ADC:
17772 new_inst = T2_OPCODE_SBC;
17773 value = inverted;
17774 break;
17775
17776 case T2_OPCODE_SBC:
17777 new_inst = T2_OPCODE_ADC;
17778 value = inverted;
17779 break;
17780
17781 /* We cannot do anything. */
17782 default:
17783 return FAIL;
17784 }
17785
17786 if (value == (unsigned int)FAIL)
17787 return FAIL;
17788
17789 *instruction &= T2_OPCODE_MASK;
17790 *instruction |= new_inst << T2_DATA_OP_SHIFT;
17791 return value;
17792}
17793
17794/* Read a 32-bit thumb instruction from buf. */
17795static unsigned long
17796get_thumb32_insn (char * buf)
17797{
17798 unsigned long insn;
17799 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
17800 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
17801
17802 return insn;
17803}
17804
17805
17806/* We usually want to set the low bit on the address of thumb function
17807 symbols. In particular .word foo - . should have the low bit set.
17808 Generic code tries to fold the difference of two symbols to
17809 a constant. Prevent this and force a relocation when the first symbols
17810 is a thumb function. */
17811int
17812arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
17813{
17814 if (op == O_subtract
17815 && l->X_op == O_symbol
17816 && r->X_op == O_symbol
17817 && THUMB_IS_FUNC (l->X_add_symbol))
17818 {
17819 l->X_op = O_subtract;
17820 l->X_op_symbol = r->X_add_symbol;
17821 l->X_add_number -= r->X_add_number;
17822 return 1;
17823 }
17824 /* Process as normal. */
17825 return 0;
17826}
17827
17828void
17829md_apply_fix (fixS * fixP,
17830 valueT * valP,
17831 segT seg)
17832{
17833 offsetT value = * valP;
17834 offsetT newval;
17835 unsigned int newimm;
17836 unsigned long temp;
17837 int sign;
17838 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
17839
17840 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
17841
17842 /* Note whether this will delete the relocation. */
17843
17844 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
17845 fixP->fx_done = 1;
17846
17847 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17848 consistency with the behavior on 32-bit hosts. Remember value
17849 for emit_reloc. */
17850 value &= 0xffffffff;
17851 value ^= 0x80000000;
17852 value -= 0x80000000;
17853
17854 *valP = value;
17855 fixP->fx_addnumber = value;
17856
17857 /* Same treatment for fixP->fx_offset. */
17858 fixP->fx_offset &= 0xffffffff;
17859 fixP->fx_offset ^= 0x80000000;
17860 fixP->fx_offset -= 0x80000000;
17861
17862 switch (fixP->fx_r_type)
17863 {
17864 case BFD_RELOC_NONE:
17865 /* This will need to go in the object file. */
17866 fixP->fx_done = 0;
17867 break;
17868
17869 case BFD_RELOC_ARM_IMMEDIATE:
17870 /* We claim that this fixup has been processed here,
17871 even if in fact we generate an error because we do
17872 not have a reloc for it, so tc_gen_reloc will reject it. */
17873 fixP->fx_done = 1;
17874
17875 if (fixP->fx_addsy
17876 && ! S_IS_DEFINED (fixP->fx_addsy))
17877 {
17878 as_bad_where (fixP->fx_file, fixP->fx_line,
17879 _("undefined symbol %s used as an immediate value"),
17880 S_GET_NAME (fixP->fx_addsy));
17881 break;
17882 }
17883
17884 newimm = encode_arm_immediate (value);
17885 temp = md_chars_to_number (buf, INSN_SIZE);
17886
17887 /* If the instruction will fail, see if we can fix things up by
17888 changing the opcode. */
17889 if (newimm == (unsigned int) FAIL
17890 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
17891 {
17892 as_bad_where (fixP->fx_file, fixP->fx_line,
17893 _("invalid constant (%lx) after fixup"),
17894 (unsigned long) value);
17895 break;
17896 }
17897
17898 newimm |= (temp & 0xfffff000);
17899 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
17900 break;
17901
17902 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
17903 {
17904 unsigned int highpart = 0;
17905 unsigned int newinsn = 0xe1a00000; /* nop. */
17906
17907 newimm = encode_arm_immediate (value);
17908 temp = md_chars_to_number (buf, INSN_SIZE);
17909
17910 /* If the instruction will fail, see if we can fix things up by
17911 changing the opcode. */
17912 if (newimm == (unsigned int) FAIL
17913 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
17914 {
17915 /* No ? OK - try using two ADD instructions to generate
17916 the value. */
17917 newimm = validate_immediate_twopart (value, & highpart);
17918
17919 /* Yes - then make sure that the second instruction is
17920 also an add. */
17921 if (newimm != (unsigned int) FAIL)
17922 newinsn = temp;
17923 /* Still No ? Try using a negated value. */
17924 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
17925 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
17926 /* Otherwise - give up. */
17927 else
17928 {
17929 as_bad_where (fixP->fx_file, fixP->fx_line,
17930 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
17931 (long) value);
17932 break;
17933 }
17934
17935 /* Replace the first operand in the 2nd instruction (which
17936 is the PC) with the destination register. We have
17937 already added in the PC in the first instruction and we
17938 do not want to do it again. */
17939 newinsn &= ~ 0xf0000;
17940 newinsn |= ((newinsn & 0x0f000) << 4);
17941 }
17942
17943 newimm |= (temp & 0xfffff000);
17944 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
17945
17946 highpart |= (newinsn & 0xfffff000);
17947 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
17948 }
17949 break;
17950
17951 case BFD_RELOC_ARM_OFFSET_IMM:
17952 if (!fixP->fx_done && seg->use_rela_p)
17953 value = 0;
17954
17955 case BFD_RELOC_ARM_LITERAL:
17956 sign = value >= 0;
17957
17958 if (value < 0)
17959 value = - value;
17960
17961 if (validate_offset_imm (value, 0) == FAIL)
17962 {
17963 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
17964 as_bad_where (fixP->fx_file, fixP->fx_line,
17965 _("invalid literal constant: pool needs to be closer"));
17966 else
17967 as_bad_where (fixP->fx_file, fixP->fx_line,
17968 _("bad immediate value for offset (%ld)"),
17969 (long) value);
17970 break;
17971 }
17972
17973 newval = md_chars_to_number (buf, INSN_SIZE);
17974 newval &= 0xff7ff000;
17975 newval |= value | (sign ? INDEX_UP : 0);
17976 md_number_to_chars (buf, newval, INSN_SIZE);
17977 break;
17978
17979 case BFD_RELOC_ARM_OFFSET_IMM8:
17980 case BFD_RELOC_ARM_HWLITERAL:
17981 sign = value >= 0;
17982
17983 if (value < 0)
17984 value = - value;
17985
17986 if (validate_offset_imm (value, 1) == FAIL)
17987 {
17988 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
17989 as_bad_where (fixP->fx_file, fixP->fx_line,
17990 _("invalid literal constant: pool needs to be closer"));
17991 else
17992 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
17993 (long) value);
17994 break;
17995 }
17996
17997 newval = md_chars_to_number (buf, INSN_SIZE);
17998 newval &= 0xff7ff0f0;
17999 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
18000 md_number_to_chars (buf, newval, INSN_SIZE);
18001 break;
18002
18003 case BFD_RELOC_ARM_T32_OFFSET_U8:
18004 if (value < 0 || value > 1020 || value % 4 != 0)
18005 as_bad_where (fixP->fx_file, fixP->fx_line,
18006 _("bad immediate value for offset (%ld)"), (long) value);
18007 value /= 4;
18008
18009 newval = md_chars_to_number (buf+2, THUMB_SIZE);
18010 newval |= value;
18011 md_number_to_chars (buf+2, newval, THUMB_SIZE);
18012 break;
18013
18014 case BFD_RELOC_ARM_T32_OFFSET_IMM:
18015 /* This is a complicated relocation used for all varieties of Thumb32
18016 load/store instruction with immediate offset:
18017
18018 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
18019 *4, optional writeback(W)
18020 (doubleword load/store)
18021
18022 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
18023 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
18024 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
18025 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
18026 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
18027
18028 Uppercase letters indicate bits that are already encoded at
18029 this point. Lowercase letters are our problem. For the
18030 second block of instructions, the secondary opcode nybble
18031 (bits 8..11) is present, and bit 23 is zero, even if this is
18032 a PC-relative operation. */
18033 newval = md_chars_to_number (buf, THUMB_SIZE);
18034 newval <<= 16;
18035 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
18036
18037 if ((newval & 0xf0000000) == 0xe0000000)
18038 {
18039 /* Doubleword load/store: 8-bit offset, scaled by 4. */
18040 if (value >= 0)
18041 newval |= (1 << 23);
18042 else
18043 value = -value;
18044 if (value % 4 != 0)
18045 {
18046 as_bad_where (fixP->fx_file, fixP->fx_line,
18047 _("offset not a multiple of 4"));
18048 break;
18049 }
18050 value /= 4;
18051 if (value > 0xff)
18052 {
18053 as_bad_where (fixP->fx_file, fixP->fx_line,
18054 _("offset out of range"));
18055 break;
18056 }
18057 newval &= ~0xff;
18058 }
18059 else if ((newval & 0x000f0000) == 0x000f0000)
18060 {
18061 /* PC-relative, 12-bit offset. */
18062 if (value >= 0)
18063 newval |= (1 << 23);
18064 else
18065 value = -value;
18066 if (value > 0xfff)
18067 {
18068 as_bad_where (fixP->fx_file, fixP->fx_line,
18069 _("offset out of range"));
18070 break;
18071 }
18072 newval &= ~0xfff;
18073 }
18074 else if ((newval & 0x00000100) == 0x00000100)
18075 {
18076 /* Writeback: 8-bit, +/- offset. */
18077 if (value >= 0)
18078 newval |= (1 << 9);
18079 else
18080 value = -value;
18081 if (value > 0xff)
18082 {
18083 as_bad_where (fixP->fx_file, fixP->fx_line,
18084 _("offset out of range"));
18085 break;
18086 }
18087 newval &= ~0xff;
18088 }
18089 else if ((newval & 0x00000f00) == 0x00000e00)
18090 {
18091 /* T-instruction: positive 8-bit offset. */
18092 if (value < 0 || value > 0xff)
18093 {
18094 as_bad_where (fixP->fx_file, fixP->fx_line,
18095 _("offset out of range"));
18096 break;
18097 }
18098 newval &= ~0xff;
18099 newval |= value;
18100 }
18101 else
18102 {
18103 /* Positive 12-bit or negative 8-bit offset. */
18104 int limit;
18105 if (value >= 0)
18106 {
18107 newval |= (1 << 23);
18108 limit = 0xfff;
18109 }
18110 else
18111 {
18112 value = -value;
18113 limit = 0xff;
18114 }
18115 if (value > limit)
18116 {
18117 as_bad_where (fixP->fx_file, fixP->fx_line,
18118 _("offset out of range"));
18119 break;
18120 }
18121 newval &= ~limit;
18122 }
18123
18124 newval |= value;
18125 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
18126 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
18127 break;
18128
18129 case BFD_RELOC_ARM_SHIFT_IMM:
18130 newval = md_chars_to_number (buf, INSN_SIZE);
18131 if (((unsigned long) value) > 32
18132 || (value == 32
18133 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
18134 {
18135 as_bad_where (fixP->fx_file, fixP->fx_line,
18136 _("shift expression is too large"));
18137 break;
18138 }
18139
18140 if (value == 0)
18141 /* Shifts of zero must be done as lsl. */
18142 newval &= ~0x60;
18143 else if (value == 32)
18144 value = 0;
18145 newval &= 0xfffff07f;
18146 newval |= (value & 0x1f) << 7;
18147 md_number_to_chars (buf, newval, INSN_SIZE);
18148 break;
18149
18150 case BFD_RELOC_ARM_T32_IMMEDIATE:
18151 case BFD_RELOC_ARM_T32_ADD_IMM:
18152 case BFD_RELOC_ARM_T32_IMM12:
18153 case BFD_RELOC_ARM_T32_ADD_PC12:
18154 /* We claim that this fixup has been processed here,
18155 even if in fact we generate an error because we do
18156 not have a reloc for it, so tc_gen_reloc will reject it. */
18157 fixP->fx_done = 1;
18158
18159 if (fixP->fx_addsy
18160 && ! S_IS_DEFINED (fixP->fx_addsy))
18161 {
18162 as_bad_where (fixP->fx_file, fixP->fx_line,
18163 _("undefined symbol %s used as an immediate value"),
18164 S_GET_NAME (fixP->fx_addsy));
18165 break;
18166 }
18167
18168 newval = md_chars_to_number (buf, THUMB_SIZE);
18169 newval <<= 16;
18170 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
18171
18172 newimm = FAIL;
18173 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
18174 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
18175 {
18176 newimm = encode_thumb32_immediate (value);
18177 if (newimm == (unsigned int) FAIL)
18178 newimm = thumb32_negate_data_op (&newval, value);
18179 }
18180 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
18181 && newimm == (unsigned int) FAIL)
18182 {
18183 /* Turn add/sum into addw/subw. */
18184 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
18185 newval = (newval & 0xfeffffff) | 0x02000000;
18186
18187 /* 12 bit immediate for addw/subw. */
18188 if (value < 0)
18189 {
18190 value = -value;
18191 newval ^= 0x00a00000;
18192 }
18193 if (value > 0xfff)
18194 newimm = (unsigned int) FAIL;
18195 else
18196 newimm = value;
18197 }
18198
18199 if (newimm == (unsigned int)FAIL)
18200 {
18201 as_bad_where (fixP->fx_file, fixP->fx_line,
18202 _("invalid constant (%lx) after fixup"),
18203 (unsigned long) value);
18204 break;
18205 }
18206
18207 newval |= (newimm & 0x800) << 15;
18208 newval |= (newimm & 0x700) << 4;
18209 newval |= (newimm & 0x0ff);
18210
18211 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
18212 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
18213 break;
18214
18215 case BFD_RELOC_ARM_SMC:
18216 if (((unsigned long) value) > 0xffff)
18217 as_bad_where (fixP->fx_file, fixP->fx_line,
18218 _("invalid smc expression"));
18219 newval = md_chars_to_number (buf, INSN_SIZE);
18220 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
18221 md_number_to_chars (buf, newval, INSN_SIZE);
18222 break;
18223
18224 case BFD_RELOC_ARM_SWI:
18225 if (fixP->tc_fix_data != 0)
18226 {
18227 if (((unsigned long) value) > 0xff)
18228 as_bad_where (fixP->fx_file, fixP->fx_line,
18229 _("invalid swi expression"));
18230 newval = md_chars_to_number (buf, THUMB_SIZE);
18231 newval |= value;
18232 md_number_to_chars (buf, newval, THUMB_SIZE);
18233 }
18234 else
18235 {
18236 if (((unsigned long) value) > 0x00ffffff)
18237 as_bad_where (fixP->fx_file, fixP->fx_line,
18238 _("invalid swi expression"));
18239 newval = md_chars_to_number (buf, INSN_SIZE);
18240 newval |= value;
18241 md_number_to_chars (buf, newval, INSN_SIZE);
18242 }
18243 break;
18244
18245 case BFD_RELOC_ARM_MULTI:
18246 if (((unsigned long) value) > 0xffff)
18247 as_bad_where (fixP->fx_file, fixP->fx_line,
18248 _("invalid expression in load/store multiple"));
18249 newval = value | md_chars_to_number (buf, INSN_SIZE);
18250 md_number_to_chars (buf, newval, INSN_SIZE);
18251 break;
18252
18253#ifdef OBJ_ELF
18254 case BFD_RELOC_ARM_PCREL_CALL:
18255 newval = md_chars_to_number (buf, INSN_SIZE);
18256 if ((newval & 0xf0000000) == 0xf0000000)
18257 temp = 1;
18258 else
18259 temp = 3;
18260 goto arm_branch_common;
18261
18262 case BFD_RELOC_ARM_PCREL_JUMP:
18263 case BFD_RELOC_ARM_PLT32:
18264#endif
18265 case BFD_RELOC_ARM_PCREL_BRANCH:
18266 temp = 3;
18267 goto arm_branch_common;
18268
18269 case BFD_RELOC_ARM_PCREL_BLX:
18270 temp = 1;
18271 arm_branch_common:
18272 /* We are going to store value (shifted right by two) in the
18273 instruction, in a 24 bit, signed field. Bits 26 through 32 either
18274 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
18275 also be be clear. */
18276 if (value & temp)
18277 as_bad_where (fixP->fx_file, fixP->fx_line,
18278 _("misaligned branch destination"));
18279 if ((value & (offsetT)0xfe000000) != (offsetT)0
18280 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
18281 as_bad_where (fixP->fx_file, fixP->fx_line,
18282 _("branch out of range"));
18283
18284 if (fixP->fx_done || !seg->use_rela_p)
18285 {
18286 newval = md_chars_to_number (buf, INSN_SIZE);
18287 newval |= (value >> 2) & 0x00ffffff;
18288 /* Set the H bit on BLX instructions. */
18289 if (temp == 1)
18290 {
18291 if (value & 2)
18292 newval |= 0x01000000;
18293 else
18294 newval &= ~0x01000000;
18295 }
18296 md_number_to_chars (buf, newval, INSN_SIZE);
18297 }
18298 break;
18299
18300 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
18301 /* CBZ can only branch forward. */
18302
18303 /* Attempts to use CBZ to branch to the next instruction
18304 (which, strictly speaking, are prohibited) will be turned into
18305 no-ops.
18306
18307 FIXME: It may be better to remove the instruction completely and
18308 perform relaxation. */
18309 if (value == -2)
18310 {
18311 newval = md_chars_to_number (buf, THUMB_SIZE);
18312 newval = 0xbf00; /* NOP encoding T1 */
18313 md_number_to_chars (buf, newval, THUMB_SIZE);
18314 }
18315 else
18316 {
18317 if (value & ~0x7e)
18318 as_bad_where (fixP->fx_file, fixP->fx_line,
18319 _("branch out of range"));
18320
18321 if (fixP->fx_done || !seg->use_rela_p)
18322 {
18323 newval = md_chars_to_number (buf, THUMB_SIZE);
18324 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
18325 md_number_to_chars (buf, newval, THUMB_SIZE);
18326 }
18327 }
18328 break;
18329
18330 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
18331 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
18332 as_bad_where (fixP->fx_file, fixP->fx_line,
18333 _("branch out of range"));
18334
18335 if (fixP->fx_done || !seg->use_rela_p)
18336 {
18337 newval = md_chars_to_number (buf, THUMB_SIZE);
18338 newval |= (value & 0x1ff) >> 1;
18339 md_number_to_chars (buf, newval, THUMB_SIZE);
18340 }
18341 break;
18342
18343 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
18344 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
18345 as_bad_where (fixP->fx_file, fixP->fx_line,
18346 _("branch out of range"));
18347
18348 if (fixP->fx_done || !seg->use_rela_p)
18349 {
18350 newval = md_chars_to_number (buf, THUMB_SIZE);
18351 newval |= (value & 0xfff) >> 1;
18352 md_number_to_chars (buf, newval, THUMB_SIZE);
18353 }
18354 break;
18355
18356 case BFD_RELOC_THUMB_PCREL_BRANCH20:
18357 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
18358 as_bad_where (fixP->fx_file, fixP->fx_line,
18359 _("conditional branch out of range"));
18360
18361 if (fixP->fx_done || !seg->use_rela_p)
18362 {
18363 offsetT newval2;
18364 addressT S, J1, J2, lo, hi;
18365
18366 S = (value & 0x00100000) >> 20;
18367 J2 = (value & 0x00080000) >> 19;
18368 J1 = (value & 0x00040000) >> 18;
18369 hi = (value & 0x0003f000) >> 12;
18370 lo = (value & 0x00000ffe) >> 1;
18371
18372 newval = md_chars_to_number (buf, THUMB_SIZE);
18373 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
18374 newval |= (S << 10) | hi;
18375 newval2 |= (J1 << 13) | (J2 << 11) | lo;
18376 md_number_to_chars (buf, newval, THUMB_SIZE);
18377 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
18378 }
18379 break;
18380
18381 case BFD_RELOC_THUMB_PCREL_BLX:
18382 case BFD_RELOC_THUMB_PCREL_BRANCH23:
18383 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
18384 as_bad_where (fixP->fx_file, fixP->fx_line,
18385 _("branch out of range"));
18386
18387 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
18388 /* For a BLX instruction, make sure that the relocation is rounded up
18389 to a word boundary. This follows the semantics of the instruction
18390 which specifies that bit 1 of the target address will come from bit
18391 1 of the base address. */
18392 value = (value + 1) & ~ 1;
18393
18394 if (fixP->fx_done || !seg->use_rela_p)
18395 {
18396 offsetT newval2;
18397
18398 newval = md_chars_to_number (buf, THUMB_SIZE);
18399 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
18400 newval |= (value & 0x7fffff) >> 12;
18401 newval2 |= (value & 0xfff) >> 1;
18402 md_number_to_chars (buf, newval, THUMB_SIZE);
18403 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
18404 }
18405 break;
18406
18407 case BFD_RELOC_THUMB_PCREL_BRANCH25:
18408 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
18409 as_bad_where (fixP->fx_file, fixP->fx_line,
18410 _("branch out of range"));
18411
18412 if (fixP->fx_done || !seg->use_rela_p)
18413 {
18414 offsetT newval2;
18415 addressT S, I1, I2, lo, hi;
18416
18417 S = (value & 0x01000000) >> 24;
18418 I1 = (value & 0x00800000) >> 23;
18419 I2 = (value & 0x00400000) >> 22;
18420 hi = (value & 0x003ff000) >> 12;
18421 lo = (value & 0x00000ffe) >> 1;
18422
18423 I1 = !(I1 ^ S);
18424 I2 = !(I2 ^ S);
18425
18426 newval = md_chars_to_number (buf, THUMB_SIZE);
18427 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
18428 newval |= (S << 10) | hi;
18429 newval2 |= (I1 << 13) | (I2 << 11) | lo;
18430 md_number_to_chars (buf, newval, THUMB_SIZE);
18431 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
18432 }
18433 break;
18434
18435 case BFD_RELOC_8:
18436 if (fixP->fx_done || !seg->use_rela_p)
18437 md_number_to_chars (buf, value, 1);
18438 break;
18439
18440 case BFD_RELOC_16:
18441 if (fixP->fx_done || !seg->use_rela_p)
18442 md_number_to_chars (buf, value, 2);
18443 break;
18444
18445#ifdef OBJ_ELF
18446 case BFD_RELOC_ARM_TLS_GD32:
18447 case BFD_RELOC_ARM_TLS_LE32:
18448 case BFD_RELOC_ARM_TLS_IE32:
18449 case BFD_RELOC_ARM_TLS_LDM32:
18450 case BFD_RELOC_ARM_TLS_LDO32:
18451 S_SET_THREAD_LOCAL (fixP->fx_addsy);
18452 /* fall through */
18453
18454 case BFD_RELOC_ARM_GOT32:
18455 case BFD_RELOC_ARM_GOTOFF:
18456 case BFD_RELOC_ARM_TARGET2:
18457 if (fixP->fx_done || !seg->use_rela_p)
18458 md_number_to_chars (buf, 0, 4);
18459 break;
18460#endif
18461
18462 case BFD_RELOC_RVA:
18463 case BFD_RELOC_32:
18464 case BFD_RELOC_ARM_TARGET1:
18465 case BFD_RELOC_ARM_ROSEGREL32:
18466 case BFD_RELOC_ARM_SBREL32:
18467 case BFD_RELOC_32_PCREL:
18468#ifdef TE_PE
18469 case BFD_RELOC_32_SECREL:
18470#endif
18471 if (fixP->fx_done || !seg->use_rela_p)
18472#ifdef TE_WINCE
18473 /* For WinCE we only do this for pcrel fixups. */
18474 if (fixP->fx_done || fixP->fx_pcrel)
18475#endif
18476 md_number_to_chars (buf, value, 4);
18477 break;
18478
18479#ifdef OBJ_ELF
18480 case BFD_RELOC_ARM_PREL31:
18481 if (fixP->fx_done || !seg->use_rela_p)
18482 {
18483 newval = md_chars_to_number (buf, 4) & 0x80000000;
18484 if ((value ^ (value >> 1)) & 0x40000000)
18485 {
18486 as_bad_where (fixP->fx_file, fixP->fx_line,
18487 _("rel31 relocation overflow"));
18488 }
18489 newval |= value & 0x7fffffff;
18490 md_number_to_chars (buf, newval, 4);
18491 }
18492 break;
18493#endif
18494
18495 case BFD_RELOC_ARM_CP_OFF_IMM:
18496 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
18497 if (value < -1023 || value > 1023 || (value & 3))
18498 as_bad_where (fixP->fx_file, fixP->fx_line,
18499 _("co-processor offset out of range"));
18500 cp_off_common:
18501 sign = value >= 0;
18502 if (value < 0)
18503 value = -value;
18504 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
18505 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
18506 newval = md_chars_to_number (buf, INSN_SIZE);
18507 else
18508 newval = get_thumb32_insn (buf);
18509 newval &= 0xff7fff00;
18510 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
18511 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
18512 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
18513 md_number_to_chars (buf, newval, INSN_SIZE);
18514 else
18515 put_thumb32_insn (buf, newval);
18516 break;
18517
18518 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
18519 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
18520 if (value < -255 || value > 255)
18521 as_bad_where (fixP->fx_file, fixP->fx_line,
18522 _("co-processor offset out of range"));
18523 value *= 4;
18524 goto cp_off_common;
18525
18526 case BFD_RELOC_ARM_THUMB_OFFSET:
18527 newval = md_chars_to_number (buf, THUMB_SIZE);
18528 /* Exactly what ranges, and where the offset is inserted depends
18529 on the type of instruction, we can establish this from the
18530 top 4 bits. */
18531 switch (newval >> 12)
18532 {
18533 case 4: /* PC load. */
18534 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18535 forced to zero for these loads; md_pcrel_from has already
18536 compensated for this. */
18537 if (value & 3)
18538 as_bad_where (fixP->fx_file, fixP->fx_line,
18539 _("invalid offset, target not word aligned (0x%08lX)"),
18540 (((unsigned long) fixP->fx_frag->fr_address
18541 + (unsigned long) fixP->fx_where) & ~3)
18542 + (unsigned long) value);
18543
18544 if (value & ~0x3fc)
18545 as_bad_where (fixP->fx_file, fixP->fx_line,
18546 _("invalid offset, value too big (0x%08lX)"),
18547 (long) value);
18548
18549 newval |= value >> 2;
18550 break;
18551
18552 case 9: /* SP load/store. */
18553 if (value & ~0x3fc)
18554 as_bad_where (fixP->fx_file, fixP->fx_line,
18555 _("invalid offset, value too big (0x%08lX)"),
18556 (long) value);
18557 newval |= value >> 2;
18558 break;
18559
18560 case 6: /* Word load/store. */
18561 if (value & ~0x7c)
18562 as_bad_where (fixP->fx_file, fixP->fx_line,
18563 _("invalid offset, value too big (0x%08lX)"),
18564 (long) value);
18565 newval |= value << 4; /* 6 - 2. */
18566 break;
18567
18568 case 7: /* Byte load/store. */
18569 if (value & ~0x1f)
18570 as_bad_where (fixP->fx_file, fixP->fx_line,
18571 _("invalid offset, value too big (0x%08lX)"),
18572 (long) value);
18573 newval |= value << 6;
18574 break;
18575
18576 case 8: /* Halfword load/store. */
18577 if (value & ~0x3e)
18578 as_bad_where (fixP->fx_file, fixP->fx_line,
18579 _("invalid offset, value too big (0x%08lX)"),
18580 (long) value);
18581 newval |= value << 5; /* 6 - 1. */
18582 break;
18583
18584 default:
18585 as_bad_where (fixP->fx_file, fixP->fx_line,
18586 "Unable to process relocation for thumb opcode: %lx",
18587 (unsigned long) newval);
18588 break;
18589 }
18590 md_number_to_chars (buf, newval, THUMB_SIZE);
18591 break;
18592
18593 case BFD_RELOC_ARM_THUMB_ADD:
18594 /* This is a complicated relocation, since we use it for all of
18595 the following immediate relocations:
18596
18597 3bit ADD/SUB
18598 8bit ADD/SUB
18599 9bit ADD/SUB SP word-aligned
18600 10bit ADD PC/SP word-aligned
18601
18602 The type of instruction being processed is encoded in the
18603 instruction field:
18604
18605 0x8000 SUB
18606 0x00F0 Rd
18607 0x000F Rs
18608 */
18609 newval = md_chars_to_number (buf, THUMB_SIZE);
18610 {
18611 int rd = (newval >> 4) & 0xf;
18612 int rs = newval & 0xf;
18613 int subtract = !!(newval & 0x8000);
18614
18615 /* Check for HI regs, only very restricted cases allowed:
18616 Adjusting SP, and using PC or SP to get an address. */
18617 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
18618 || (rs > 7 && rs != REG_SP && rs != REG_PC))
18619 as_bad_where (fixP->fx_file, fixP->fx_line,
18620 _("invalid Hi register with immediate"));
18621
18622 /* If value is negative, choose the opposite instruction. */
18623 if (value < 0)
18624 {
18625 value = -value;
18626 subtract = !subtract;
18627 if (value < 0)
18628 as_bad_where (fixP->fx_file, fixP->fx_line,
18629 _("immediate value out of range"));
18630 }
18631
18632 if (rd == REG_SP)
18633 {
18634 if (value & ~0x1fc)
18635 as_bad_where (fixP->fx_file, fixP->fx_line,
18636 _("invalid immediate for stack address calculation"));
18637 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
18638 newval |= value >> 2;
18639 }
18640 else if (rs == REG_PC || rs == REG_SP)
18641 {
18642 if (subtract || value & ~0x3fc)
18643 as_bad_where (fixP->fx_file, fixP->fx_line,
18644 _("invalid immediate for address calculation (value = 0x%08lX)"),
18645 (unsigned long) value);
18646 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
18647 newval |= rd << 8;
18648 newval |= value >> 2;
18649 }
18650 else if (rs == rd)
18651 {
18652 if (value & ~0xff)
18653 as_bad_where (fixP->fx_file, fixP->fx_line,
18654 _("immediate value out of range"));
18655 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
18656 newval |= (rd << 8) | value;
18657 }
18658 else
18659 {
18660 if (value & ~0x7)
18661 as_bad_where (fixP->fx_file, fixP->fx_line,
18662 _("immediate value out of range"));
18663 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
18664 newval |= rd | (rs << 3) | (value << 6);
18665 }
18666 }
18667 md_number_to_chars (buf, newval, THUMB_SIZE);
18668 break;
18669
18670 case BFD_RELOC_ARM_THUMB_IMM:
18671 newval = md_chars_to_number (buf, THUMB_SIZE);
18672 if (value < 0 || value > 255)
18673 as_bad_where (fixP->fx_file, fixP->fx_line,
18674 _("invalid immediate: %ld is too large"),
18675 (long) value);
18676 newval |= value;
18677 md_number_to_chars (buf, newval, THUMB_SIZE);
18678 break;
18679
18680 case BFD_RELOC_ARM_THUMB_SHIFT:
18681 /* 5bit shift value (0..32). LSL cannot take 32. */
18682 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
18683 temp = newval & 0xf800;
18684 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
18685 as_bad_where (fixP->fx_file, fixP->fx_line,
18686 _("invalid shift value: %ld"), (long) value);
18687 /* Shifts of zero must be encoded as LSL. */
18688 if (value == 0)
18689 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
18690 /* Shifts of 32 are encoded as zero. */
18691 else if (value == 32)
18692 value = 0;
18693 newval |= value << 6;
18694 md_number_to_chars (buf, newval, THUMB_SIZE);
18695 break;
18696
18697 case BFD_RELOC_VTABLE_INHERIT:
18698 case BFD_RELOC_VTABLE_ENTRY:
18699 fixP->fx_done = 0;
18700 return;
18701
18702 case BFD_RELOC_ARM_MOVW:
18703 case BFD_RELOC_ARM_MOVT:
18704 case BFD_RELOC_ARM_THUMB_MOVW:
18705 case BFD_RELOC_ARM_THUMB_MOVT:
18706 if (fixP->fx_done || !seg->use_rela_p)
18707 {
18708 /* REL format relocations are limited to a 16-bit addend. */
18709 if (!fixP->fx_done)
18710 {
18711 if (value < -0x1000 || value > 0xffff)
18712 as_bad_where (fixP->fx_file, fixP->fx_line,
18713 _("offset too big"));
18714 }
18715 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
18716 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
18717 {
18718 value >>= 16;
18719 }
18720
18721 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
18722 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
18723 {
18724 newval = get_thumb32_insn (buf);
18725 newval &= 0xfbf08f00;
18726 newval |= (value & 0xf000) << 4;
18727 newval |= (value & 0x0800) << 15;
18728 newval |= (value & 0x0700) << 4;
18729 newval |= (value & 0x00ff);
18730 put_thumb32_insn (buf, newval);
18731 }
18732 else
18733 {
18734 newval = md_chars_to_number (buf, 4);
18735 newval &= 0xfff0f000;
18736 newval |= value & 0x0fff;
18737 newval |= (value & 0xf000) << 4;
18738 md_number_to_chars (buf, newval, 4);
18739 }
18740 }
18741 return;
18742
18743 case BFD_RELOC_ARM_ALU_PC_G0_NC:
18744 case BFD_RELOC_ARM_ALU_PC_G0:
18745 case BFD_RELOC_ARM_ALU_PC_G1_NC:
18746 case BFD_RELOC_ARM_ALU_PC_G1:
18747 case BFD_RELOC_ARM_ALU_PC_G2:
18748 case BFD_RELOC_ARM_ALU_SB_G0_NC:
18749 case BFD_RELOC_ARM_ALU_SB_G0:
18750 case BFD_RELOC_ARM_ALU_SB_G1_NC:
18751 case BFD_RELOC_ARM_ALU_SB_G1:
18752 case BFD_RELOC_ARM_ALU_SB_G2:
18753 assert (!fixP->fx_done);
18754 if (!seg->use_rela_p)
18755 {
18756 bfd_vma insn;
18757 bfd_vma encoded_addend;
18758 bfd_vma addend_abs = abs (value);
18759
18760 /* Check that the absolute value of the addend can be
18761 expressed as an 8-bit constant plus a rotation. */
18762 encoded_addend = encode_arm_immediate (addend_abs);
18763 if (encoded_addend == (unsigned int) FAIL)
18764 as_bad_where (fixP->fx_file, fixP->fx_line,
18765 _("the offset 0x%08lX is not representable"),
18766 (unsigned long) addend_abs);
18767
18768 /* Extract the instruction. */
18769 insn = md_chars_to_number (buf, INSN_SIZE);
18770
18771 /* If the addend is positive, use an ADD instruction.
18772 Otherwise use a SUB. Take care not to destroy the S bit. */
18773 insn &= 0xff1fffff;
18774 if (value < 0)
18775 insn |= 1 << 22;
18776 else
18777 insn |= 1 << 23;
18778
18779 /* Place the encoded addend into the first 12 bits of the
18780 instruction. */
18781 insn &= 0xfffff000;
18782 insn |= encoded_addend;
18783
18784 /* Update the instruction. */
18785 md_number_to_chars (buf, insn, INSN_SIZE);
18786 }
18787 break;
18788
18789 case BFD_RELOC_ARM_LDR_PC_G0:
18790 case BFD_RELOC_ARM_LDR_PC_G1:
18791 case BFD_RELOC_ARM_LDR_PC_G2:
18792 case BFD_RELOC_ARM_LDR_SB_G0:
18793 case BFD_RELOC_ARM_LDR_SB_G1:
18794 case BFD_RELOC_ARM_LDR_SB_G2:
18795 assert (!fixP->fx_done);
18796 if (!seg->use_rela_p)
18797 {
18798 bfd_vma insn;
18799 bfd_vma addend_abs = abs (value);
18800
18801 /* Check that the absolute value of the addend can be
18802 encoded in 12 bits. */
18803 if (addend_abs >= 0x1000)
18804 as_bad_where (fixP->fx_file, fixP->fx_line,
18805 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18806 (unsigned long) addend_abs);
18807
18808 /* Extract the instruction. */
18809 insn = md_chars_to_number (buf, INSN_SIZE);
18810
18811 /* If the addend is negative, clear bit 23 of the instruction.
18812 Otherwise set it. */
18813 if (value < 0)
18814 insn &= ~(1 << 23);
18815 else
18816 insn |= 1 << 23;
18817
18818 /* Place the absolute value of the addend into the first 12 bits
18819 of the instruction. */
18820 insn &= 0xfffff000;
18821 insn |= addend_abs;
18822
18823 /* Update the instruction. */
18824 md_number_to_chars (buf, insn, INSN_SIZE);
18825 }
18826 break;
18827
18828 case BFD_RELOC_ARM_LDRS_PC_G0:
18829 case BFD_RELOC_ARM_LDRS_PC_G1:
18830 case BFD_RELOC_ARM_LDRS_PC_G2:
18831 case BFD_RELOC_ARM_LDRS_SB_G0:
18832 case BFD_RELOC_ARM_LDRS_SB_G1:
18833 case BFD_RELOC_ARM_LDRS_SB_G2:
18834 assert (!fixP->fx_done);
18835 if (!seg->use_rela_p)
18836 {
18837 bfd_vma insn;
18838 bfd_vma addend_abs = abs (value);
18839
18840 /* Check that the absolute value of the addend can be
18841 encoded in 8 bits. */
18842 if (addend_abs >= 0x100)
18843 as_bad_where (fixP->fx_file, fixP->fx_line,
18844 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18845 (unsigned long) addend_abs);
18846
18847 /* Extract the instruction. */
18848 insn = md_chars_to_number (buf, INSN_SIZE);
18849
18850 /* If the addend is negative, clear bit 23 of the instruction.
18851 Otherwise set it. */
18852 if (value < 0)
18853 insn &= ~(1 << 23);
18854 else
18855 insn |= 1 << 23;
18856
18857 /* Place the first four bits of the absolute value of the addend
18858 into the first 4 bits of the instruction, and the remaining
18859 four into bits 8 .. 11. */
18860 insn &= 0xfffff0f0;
18861 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
18862
18863 /* Update the instruction. */
18864 md_number_to_chars (buf, insn, INSN_SIZE);
18865 }
18866 break;
18867
18868 case BFD_RELOC_ARM_LDC_PC_G0:
18869 case BFD_RELOC_ARM_LDC_PC_G1:
18870 case BFD_RELOC_ARM_LDC_PC_G2:
18871 case BFD_RELOC_ARM_LDC_SB_G0:
18872 case BFD_RELOC_ARM_LDC_SB_G1:
18873 case BFD_RELOC_ARM_LDC_SB_G2:
18874 assert (!fixP->fx_done);
18875 if (!seg->use_rela_p)
18876 {
18877 bfd_vma insn;
18878 bfd_vma addend_abs = abs (value);
18879
18880 /* Check that the absolute value of the addend is a multiple of
18881 four and, when divided by four, fits in 8 bits. */
18882 if (addend_abs & 0x3)
18883 as_bad_where (fixP->fx_file, fixP->fx_line,
18884 _("bad offset 0x%08lX (must be word-aligned)"),
18885 (unsigned long) addend_abs);
18886
18887 if ((addend_abs >> 2) > 0xff)
18888 as_bad_where (fixP->fx_file, fixP->fx_line,
18889 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18890 (unsigned long) addend_abs);
18891
18892 /* Extract the instruction. */
18893 insn = md_chars_to_number (buf, INSN_SIZE);
18894
18895 /* If the addend is negative, clear bit 23 of the instruction.
18896 Otherwise set it. */
18897 if (value < 0)
18898 insn &= ~(1 << 23);
18899 else
18900 insn |= 1 << 23;
18901
18902 /* Place the addend (divided by four) into the first eight
18903 bits of the instruction. */
18904 insn &= 0xfffffff0;
18905 insn |= addend_abs >> 2;
18906
18907 /* Update the instruction. */
18908 md_number_to_chars (buf, insn, INSN_SIZE);
18909 }
18910 break;
18911
18912 case BFD_RELOC_UNUSED:
18913 default:
18914 as_bad_where (fixP->fx_file, fixP->fx_line,
18915 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
18916 }
18917}
18918
18919/* Translate internal representation of relocation info to BFD target
18920 format. */
18921
18922arelent *
18923tc_gen_reloc (asection *section, fixS *fixp)
18924{
18925 arelent * reloc;
18926 bfd_reloc_code_real_type code;
18927
18928 reloc = xmalloc (sizeof (arelent));
18929
18930 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
18931 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
18932 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
18933
18934 if (fixp->fx_pcrel)
18935 {
18936 if (section->use_rela_p)
18937 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
18938 else
18939 fixp->fx_offset = reloc->address;
18940 }
18941 reloc->addend = fixp->fx_offset;
18942
18943 switch (fixp->fx_r_type)
18944 {
18945 case BFD_RELOC_8:
18946 if (fixp->fx_pcrel)
18947 {
18948 code = BFD_RELOC_8_PCREL;
18949 break;
18950 }
18951
18952 case BFD_RELOC_16:
18953 if (fixp->fx_pcrel)
18954 {
18955 code = BFD_RELOC_16_PCREL;
18956 break;
18957 }
18958
18959 case BFD_RELOC_32:
18960 if (fixp->fx_pcrel)
18961 {
18962 code = BFD_RELOC_32_PCREL;
18963 break;
18964 }
18965
18966 case BFD_RELOC_ARM_MOVW:
18967 if (fixp->fx_pcrel)
18968 {
18969 code = BFD_RELOC_ARM_MOVW_PCREL;
18970 break;
18971 }
18972
18973 case BFD_RELOC_ARM_MOVT:
18974 if (fixp->fx_pcrel)
18975 {
18976 code = BFD_RELOC_ARM_MOVT_PCREL;
18977 break;
18978 }
18979
18980 case BFD_RELOC_ARM_THUMB_MOVW:
18981 if (fixp->fx_pcrel)
18982 {
18983 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
18984 break;
18985 }
18986
18987 case BFD_RELOC_ARM_THUMB_MOVT:
18988 if (fixp->fx_pcrel)
18989 {
18990 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
18991 break;
18992 }
18993
18994 case BFD_RELOC_NONE:
18995 case BFD_RELOC_ARM_PCREL_BRANCH:
18996 case BFD_RELOC_ARM_PCREL_BLX:
18997 case BFD_RELOC_RVA:
18998 case BFD_RELOC_THUMB_PCREL_BRANCH7:
18999 case BFD_RELOC_THUMB_PCREL_BRANCH9:
19000 case BFD_RELOC_THUMB_PCREL_BRANCH12:
19001 case BFD_RELOC_THUMB_PCREL_BRANCH20:
19002 case BFD_RELOC_THUMB_PCREL_BRANCH23:
19003 case BFD_RELOC_THUMB_PCREL_BRANCH25:
19004 case BFD_RELOC_THUMB_PCREL_BLX:
19005 case BFD_RELOC_VTABLE_ENTRY:
19006 case BFD_RELOC_VTABLE_INHERIT:
19007#ifdef TE_PE
19008 case BFD_RELOC_32_SECREL:
19009#endif
19010 code = fixp->fx_r_type;
19011 break;
19012
19013 case BFD_RELOC_ARM_LITERAL:
19014 case BFD_RELOC_ARM_HWLITERAL:
19015 /* If this is called then the a literal has
19016 been referenced across a section boundary. */
19017 as_bad_where (fixp->fx_file, fixp->fx_line,
19018 _("literal referenced across section boundary"));
19019 return NULL;
19020
19021#ifdef OBJ_ELF
19022 case BFD_RELOC_ARM_GOT32:
19023 case BFD_RELOC_ARM_GOTOFF:
19024 case BFD_RELOC_ARM_PLT32:
19025 case BFD_RELOC_ARM_TARGET1:
19026 case BFD_RELOC_ARM_ROSEGREL32:
19027 case BFD_RELOC_ARM_SBREL32:
19028 case BFD_RELOC_ARM_PREL31:
19029 case BFD_RELOC_ARM_TARGET2:
19030 case BFD_RELOC_ARM_TLS_LE32:
19031 case BFD_RELOC_ARM_TLS_LDO32:
19032 case BFD_RELOC_ARM_PCREL_CALL:
19033 case BFD_RELOC_ARM_PCREL_JUMP:
19034 case BFD_RELOC_ARM_ALU_PC_G0_NC:
19035 case BFD_RELOC_ARM_ALU_PC_G0:
19036 case BFD_RELOC_ARM_ALU_PC_G1_NC:
19037 case BFD_RELOC_ARM_ALU_PC_G1:
19038 case BFD_RELOC_ARM_ALU_PC_G2:
19039 case BFD_RELOC_ARM_LDR_PC_G0:
19040 case BFD_RELOC_ARM_LDR_PC_G1:
19041 case BFD_RELOC_ARM_LDR_PC_G2:
19042 case BFD_RELOC_ARM_LDRS_PC_G0:
19043 case BFD_RELOC_ARM_LDRS_PC_G1:
19044 case BFD_RELOC_ARM_LDRS_PC_G2:
19045 case BFD_RELOC_ARM_LDC_PC_G0:
19046 case BFD_RELOC_ARM_LDC_PC_G1:
19047 case BFD_RELOC_ARM_LDC_PC_G2:
19048 case BFD_RELOC_ARM_ALU_SB_G0_NC:
19049 case BFD_RELOC_ARM_ALU_SB_G0:
19050 case BFD_RELOC_ARM_ALU_SB_G1_NC:
19051 case BFD_RELOC_ARM_ALU_SB_G1:
19052 case BFD_RELOC_ARM_ALU_SB_G2:
19053 case BFD_RELOC_ARM_LDR_SB_G0:
19054 case BFD_RELOC_ARM_LDR_SB_G1:
19055 case BFD_RELOC_ARM_LDR_SB_G2:
19056 case BFD_RELOC_ARM_LDRS_SB_G0:
19057 case BFD_RELOC_ARM_LDRS_SB_G1:
19058 case BFD_RELOC_ARM_LDRS_SB_G2:
19059 case BFD_RELOC_ARM_LDC_SB_G0:
19060 case BFD_RELOC_ARM_LDC_SB_G1:
19061 case BFD_RELOC_ARM_LDC_SB_G2:
19062 code = fixp->fx_r_type;
19063 break;
19064
19065 case BFD_RELOC_ARM_TLS_GD32:
19066 case BFD_RELOC_ARM_TLS_IE32:
19067 case BFD_RELOC_ARM_TLS_LDM32:
19068 /* BFD will include the symbol's address in the addend.
19069 But we don't want that, so subtract it out again here. */
19070 if (!S_IS_COMMON (fixp->fx_addsy))
19071 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
19072 code = fixp->fx_r_type;
19073 break;
19074#endif
19075
19076 case BFD_RELOC_ARM_IMMEDIATE:
19077 as_bad_where (fixp->fx_file, fixp->fx_line,
19078 _("internal relocation (type: IMMEDIATE) not fixed up"));
19079 return NULL;
19080
19081 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
19082 as_bad_where (fixp->fx_file, fixp->fx_line,
19083 _("ADRL used for a symbol not defined in the same file"));
19084 return NULL;
19085
19086 case BFD_RELOC_ARM_OFFSET_IMM:
19087 if (section->use_rela_p)
19088 {
19089 code = fixp->fx_r_type;
19090 break;
19091 }
19092
19093 if (fixp->fx_addsy != NULL
19094 && !S_IS_DEFINED (fixp->fx_addsy)
19095 && S_IS_LOCAL (fixp->fx_addsy))
19096 {
19097 as_bad_where (fixp->fx_file, fixp->fx_line,
19098 _("undefined local label `%s'"),
19099 S_GET_NAME (fixp->fx_addsy));
19100 return NULL;
19101 }
19102
19103 as_bad_where (fixp->fx_file, fixp->fx_line,
19104 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19105 return NULL;
19106
19107 default:
19108 {
19109 char * type;
19110
19111 switch (fixp->fx_r_type)
19112 {
19113 case BFD_RELOC_NONE: type = "NONE"; break;
19114 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
19115 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
19116 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
19117 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
19118 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
19119 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
19120 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
19121 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
19122 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
19123 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
19124 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
19125 default: type = _("<unknown>"); break;
19126 }
19127 as_bad_where (fixp->fx_file, fixp->fx_line,
19128 _("cannot represent %s relocation in this object file format"),
19129 type);
19130 return NULL;
19131 }
19132 }
19133
19134#ifdef OBJ_ELF
19135 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
19136 && GOT_symbol
19137 && fixp->fx_addsy == GOT_symbol)
19138 {
19139 code = BFD_RELOC_ARM_GOTPC;
19140 reloc->addend = fixp->fx_offset = reloc->address;
19141 }
19142#endif
19143
19144 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
19145
19146 if (reloc->howto == NULL)
19147 {
19148 as_bad_where (fixp->fx_file, fixp->fx_line,
19149 _("cannot represent %s relocation in this object file format"),
19150 bfd_get_reloc_code_name (code));
19151 return NULL;
19152 }
19153
19154 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
19155 vtable entry to be used in the relocation's section offset. */
19156 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
19157 reloc->address = fixp->fx_offset;
19158
19159 return reloc;
19160}
19161
19162/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
19163
19164void
19165cons_fix_new_arm (fragS * frag,
19166 int where,
19167 int size,
19168 expressionS * exp)
19169{
19170 bfd_reloc_code_real_type type;
19171 int pcrel = 0;
19172
19173 /* Pick a reloc.
19174 FIXME: @@ Should look at CPU word size. */
19175 switch (size)
19176 {
19177 case 1:
19178 type = BFD_RELOC_8;
19179 break;
19180 case 2:
19181 type = BFD_RELOC_16;
19182 break;
19183 case 4:
19184 default:
19185 type = BFD_RELOC_32;
19186 break;
19187 case 8:
19188 type = BFD_RELOC_64;
19189 break;
19190 }
19191
19192#ifdef TE_PE
19193 if (exp->X_op == O_secrel)
19194 {
19195 exp->X_op = O_symbol;
19196 type = BFD_RELOC_32_SECREL;
19197 }
19198#endif
19199
19200 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
19201}
19202
19203#if defined OBJ_COFF || defined OBJ_ELF
19204void
19205arm_validate_fix (fixS * fixP)
19206{
19207 /* If the destination of the branch is a defined symbol which does not have
19208 the THUMB_FUNC attribute, then we must be calling a function which has
19209 the (interfacearm) attribute. We look for the Thumb entry point to that
19210 function and change the branch to refer to that function instead. */
19211 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
19212 && fixP->fx_addsy != NULL
19213 && S_IS_DEFINED (fixP->fx_addsy)
19214 && ! THUMB_IS_FUNC (fixP->fx_addsy))
19215 {
19216 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
19217 }
19218}
19219#endif
19220
19221int
19222arm_force_relocation (struct fix * fixp)
19223{
19224#if defined (OBJ_COFF) && defined (TE_PE)
19225 if (fixp->fx_r_type == BFD_RELOC_RVA)
19226 return 1;
19227#endif
19228
19229 /* Resolve these relocations even if the symbol is extern or weak. */
19230 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
19231 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
19232 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
19233 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
19234 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
19235 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
19236 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12)
19237 return 0;
19238
19239 /* Always leave these relocations for the linker. */
19240 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
19241 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
19242 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
19243 return 1;
19244
19245 /* Always generate relocations against function symbols. */
19246 if (fixp->fx_r_type == BFD_RELOC_32
19247 && fixp->fx_addsy
19248 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
19249 return 1;
19250
19251 return generic_force_reloc (fixp);
19252}
19253
19254#if defined (OBJ_ELF) || defined (OBJ_COFF)
19255/* Relocations against function names must be left unadjusted,
19256 so that the linker can use this information to generate interworking
19257 stubs. The MIPS version of this function
19258 also prevents relocations that are mips-16 specific, but I do not
19259 know why it does this.
19260
19261 FIXME:
19262 There is one other problem that ought to be addressed here, but
19263 which currently is not: Taking the address of a label (rather
19264 than a function) and then later jumping to that address. Such
19265 addresses also ought to have their bottom bit set (assuming that
19266 they reside in Thumb code), but at the moment they will not. */
19267
19268bfd_boolean
19269arm_fix_adjustable (fixS * fixP)
19270{
19271 if (fixP->fx_addsy == NULL)
19272 return 1;
19273
19274 /* Preserve relocations against symbols with function type. */
19275 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
19276 return 0;
19277
19278 if (THUMB_IS_FUNC (fixP->fx_addsy)
19279 && fixP->fx_subsy == NULL)
19280 return 0;
19281
19282 /* We need the symbol name for the VTABLE entries. */
19283 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
19284 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
19285 return 0;
19286
19287 /* Don't allow symbols to be discarded on GOT related relocs. */
19288 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
19289 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
19290 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
19291 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
19292 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
19293 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
19294 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
19295 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
19296 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
19297 return 0;
19298
19299 /* Similarly for group relocations. */
19300 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
19301 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
19302 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
19303 return 0;
19304
19305 return 1;
19306}
19307#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
19308
19309#ifdef OBJ_ELF
19310
19311const char *
19312elf32_arm_target_format (void)
19313{
19314#ifdef TE_SYMBIAN
19315 return (target_big_endian
19316 ? "elf32-bigarm-symbian"
19317 : "elf32-littlearm-symbian");
19318#elif defined (TE_VXWORKS)
19319 return (target_big_endian
19320 ? "elf32-bigarm-vxworks"
19321 : "elf32-littlearm-vxworks");
19322#else
19323 if (target_big_endian)
19324 return "elf32-bigarm";
19325 else
19326 return "elf32-littlearm";
19327#endif
19328}
19329
19330void
19331armelf_frob_symbol (symbolS * symp,
19332 int * puntp)
19333{
19334 elf_frob_symbol (symp, puntp);
19335}
19336#endif
19337
19338/* MD interface: Finalization. */
19339
19340/* A good place to do this, although this was probably not intended
19341 for this kind of use. We need to dump the literal pool before
19342 references are made to a null symbol pointer. */
19343
19344void
19345arm_cleanup (void)
19346{
19347 literal_pool * pool;
19348
19349 for (pool = list_of_pools; pool; pool = pool->next)
19350 {
19351 /* Put it at the end of the relevent section. */
19352 subseg_set (pool->section, pool->sub_section);
19353#ifdef OBJ_ELF
19354 arm_elf_change_section ();
19355#endif
19356 s_ltorg (0);
19357 }
19358}
19359
19360/* Adjust the symbol table. This marks Thumb symbols as distinct from
19361 ARM ones. */
19362
19363void
19364arm_adjust_symtab (void)
19365{
19366#ifdef OBJ_COFF
19367 symbolS * sym;
19368
19369 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
19370 {
19371 if (ARM_IS_THUMB (sym))
19372 {
19373 if (THUMB_IS_FUNC (sym))
19374 {
19375 /* Mark the symbol as a Thumb function. */
19376 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
19377 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
19378 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
19379
19380 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
19381 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
19382 else
19383 as_bad (_("%s: unexpected function type: %d"),
19384 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
19385 }
19386 else switch (S_GET_STORAGE_CLASS (sym))
19387 {
19388 case C_EXT:
19389 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
19390 break;
19391 case C_STAT:
19392 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
19393 break;
19394 case C_LABEL:
19395 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
19396 break;
19397 default:
19398 /* Do nothing. */
19399 break;
19400 }
19401 }
19402
19403 if (ARM_IS_INTERWORK (sym))
19404 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
19405 }
19406#endif
19407#ifdef OBJ_ELF
19408 symbolS * sym;
19409 char bind;
19410
19411 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
19412 {
19413 if (ARM_IS_THUMB (sym))
19414 {
19415 elf_symbol_type * elf_sym;
19416
19417 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
19418 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
19419
19420 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
19421 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
19422 {
19423 /* If it's a .thumb_func, declare it as so,
19424 otherwise tag label as .code 16. */
19425 if (THUMB_IS_FUNC (sym))
19426 elf_sym->internal_elf_sym.st_info =
19427 ELF_ST_INFO (bind, STT_ARM_TFUNC);
19428 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
19429 elf_sym->internal_elf_sym.st_info =
19430 ELF_ST_INFO (bind, STT_ARM_16BIT);
19431 }
19432 }
19433 }
19434#endif
19435}
19436
19437/* MD interface: Initialization. */
19438
19439static void
19440set_constant_flonums (void)
19441{
19442 int i;
19443
19444 for (i = 0; i < NUM_FLOAT_VALS; i++)
19445 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
19446 abort ();
19447}
19448
19449/* Auto-select Thumb mode if it's the only available instruction set for the
19450 given architecture. */
19451
19452static void
19453autoselect_thumb_from_cpu_variant (void)
19454{
19455 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
19456 opcode_select (16);
19457}
19458
19459void
19460md_begin (void)
19461{
19462 unsigned mach;
19463 unsigned int i;
19464
19465 if ( (arm_ops_hsh = hash_new ()) == NULL
19466 || (arm_cond_hsh = hash_new ()) == NULL
19467 || (arm_shift_hsh = hash_new ()) == NULL
19468 || (arm_psr_hsh = hash_new ()) == NULL
19469 || (arm_v7m_psr_hsh = hash_new ()) == NULL
19470 || (arm_reg_hsh = hash_new ()) == NULL
19471 || (arm_reloc_hsh = hash_new ()) == NULL
19472 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
19473 as_fatal (_("virtual memory exhausted"));
19474
19475 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
19476 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
19477 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
19478 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
19479 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
19480 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
19481 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
19482 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
19483 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
19484 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template, (PTR) (v7m_psrs + i));
19485 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
19486 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i));
19487 for (i = 0;
19488 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
19489 i++)
19490 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template,
19491 (PTR) (barrier_opt_names + i));
19492#ifdef OBJ_ELF
19493 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
19494 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i));
19495#endif
19496
19497 set_constant_flonums ();
19498
19499 /* Set the cpu variant based on the command-line options. We prefer
19500 -mcpu= over -march= if both are set (as for GCC); and we prefer
19501 -mfpu= over any other way of setting the floating point unit.
19502 Use of legacy options with new options are faulted. */
19503 if (legacy_cpu)
19504 {
19505 if (mcpu_cpu_opt || march_cpu_opt)
19506 as_bad (_("use of old and new-style options to set CPU type"));
19507
19508 mcpu_cpu_opt = legacy_cpu;
19509 }
19510 else if (!mcpu_cpu_opt)
19511 mcpu_cpu_opt = march_cpu_opt;
19512
19513 if (legacy_fpu)
19514 {
19515 if (mfpu_opt)
19516 as_bad (_("use of old and new-style options to set FPU type"));
19517
19518 mfpu_opt = legacy_fpu;
19519 }
19520 else if (!mfpu_opt)
19521 {
19522#if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19523 /* Some environments specify a default FPU. If they don't, infer it
19524 from the processor. */
19525 if (mcpu_fpu_opt)
19526 mfpu_opt = mcpu_fpu_opt;
19527 else
19528 mfpu_opt = march_fpu_opt;
19529#else
19530 mfpu_opt = &fpu_default;
19531#endif
19532 }
19533
19534 if (!mfpu_opt)
19535 {
19536 if (mcpu_cpu_opt != NULL)
19537 mfpu_opt = &fpu_default;
19538 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
19539 mfpu_opt = &fpu_arch_vfp_v2;
19540 else
19541 mfpu_opt = &fpu_arch_fpa;
19542 }
19543
19544#ifdef CPU_DEFAULT
19545 if (!mcpu_cpu_opt)
19546 {
19547 mcpu_cpu_opt = &cpu_default;
19548 selected_cpu = cpu_default;
19549 }
19550#else
19551 if (mcpu_cpu_opt)
19552 selected_cpu = *mcpu_cpu_opt;
19553 else
19554 mcpu_cpu_opt = &arm_arch_any;
19555#endif
19556
19557 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
19558
19559 autoselect_thumb_from_cpu_variant ();
19560
19561 arm_arch_used = thumb_arch_used = arm_arch_none;
19562
19563#if defined OBJ_COFF || defined OBJ_ELF
19564 {
19565 unsigned int flags = 0;
19566
19567#if defined OBJ_ELF
19568 flags = meabi_flags;
19569
19570 switch (meabi_flags)
19571 {
19572 case EF_ARM_EABI_UNKNOWN:
19573#endif
19574 /* Set the flags in the private structure. */
19575 if (uses_apcs_26) flags |= F_APCS26;
19576 if (support_interwork) flags |= F_INTERWORK;
19577 if (uses_apcs_float) flags |= F_APCS_FLOAT;
19578 if (pic_code) flags |= F_PIC;
19579 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
19580 flags |= F_SOFT_FLOAT;
19581
19582 switch (mfloat_abi_opt)
19583 {
19584 case ARM_FLOAT_ABI_SOFT:
19585 case ARM_FLOAT_ABI_SOFTFP:
19586 flags |= F_SOFT_FLOAT;
19587 break;
19588
19589 case ARM_FLOAT_ABI_HARD:
19590 if (flags & F_SOFT_FLOAT)
19591 as_bad (_("hard-float conflicts with specified fpu"));
19592 break;
19593 }
19594
19595 /* Using pure-endian doubles (even if soft-float). */
19596 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
19597 flags |= F_VFP_FLOAT;
19598
19599#if defined OBJ_ELF
19600 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
19601 flags |= EF_ARM_MAVERICK_FLOAT;
19602 break;
19603
19604 case EF_ARM_EABI_VER4:
19605 case EF_ARM_EABI_VER5:
19606 /* No additional flags to set. */
19607 break;
19608
19609 default:
19610 abort ();
19611 }
19612#endif
19613 bfd_set_private_flags (stdoutput, flags);
19614
19615 /* We have run out flags in the COFF header to encode the
19616 status of ATPCS support, so instead we create a dummy,
19617 empty, debug section called .arm.atpcs. */
19618 if (atpcs)
19619 {
19620 asection * sec;
19621
19622 sec = bfd_make_section (stdoutput, ".arm.atpcs");
19623
19624 if (sec != NULL)
19625 {
19626 bfd_set_section_flags
19627 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
19628 bfd_set_section_size (stdoutput, sec, 0);
19629 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
19630 }
19631 }
19632 }
19633#endif
19634
19635 /* Record the CPU type as well. */
19636 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
19637 mach = bfd_mach_arm_iWMMXt2;
19638 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
19639 mach = bfd_mach_arm_iWMMXt;
19640 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
19641 mach = bfd_mach_arm_XScale;
19642 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
19643 mach = bfd_mach_arm_ep9312;
19644 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
19645 mach = bfd_mach_arm_5TE;
19646 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
19647 {
19648 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
19649 mach = bfd_mach_arm_5T;
19650 else
19651 mach = bfd_mach_arm_5;
19652 }
19653 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
19654 {
19655 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
19656 mach = bfd_mach_arm_4T;
19657 else
19658 mach = bfd_mach_arm_4;
19659 }
19660 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
19661 mach = bfd_mach_arm_3M;
19662 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
19663 mach = bfd_mach_arm_3;
19664 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
19665 mach = bfd_mach_arm_2a;
19666 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
19667 mach = bfd_mach_arm_2;
19668 else
19669 mach = bfd_mach_arm_unknown;
19670
19671 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
19672}
19673
19674/* Command line processing. */
19675
19676/* md_parse_option
19677 Invocation line includes a switch not recognized by the base assembler.
19678 See if it's a processor-specific option.
19679
19680 This routine is somewhat complicated by the need for backwards
19681 compatibility (since older releases of gcc can't be changed).
19682 The new options try to make the interface as compatible as
19683 possible with GCC.
19684
19685 New options (supported) are:
19686
19687 -mcpu=<cpu name> Assemble for selected processor
19688 -march=<architecture name> Assemble for selected architecture
19689 -mfpu=<fpu architecture> Assemble for selected FPU.
19690 -EB/-mbig-endian Big-endian
19691 -EL/-mlittle-endian Little-endian
19692 -k Generate PIC code
19693 -mthumb Start in Thumb mode
19694 -mthumb-interwork Code supports ARM/Thumb interworking
19695
19696 For now we will also provide support for:
19697
19698 -mapcs-32 32-bit Program counter
19699 -mapcs-26 26-bit Program counter
19700 -macps-float Floats passed in FP registers
19701 -mapcs-reentrant Reentrant code
19702 -matpcs
19703 (sometime these will probably be replaced with -mapcs=<list of options>
19704 and -matpcs=<list of options>)
19705
19706 The remaining options are only supported for back-wards compatibility.
19707 Cpu variants, the arm part is optional:
19708 -m[arm]1 Currently not supported.
19709 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19710 -m[arm]3 Arm 3 processor
19711 -m[arm]6[xx], Arm 6 processors
19712 -m[arm]7[xx][t][[d]m] Arm 7 processors
19713 -m[arm]8[10] Arm 8 processors
19714 -m[arm]9[20][tdmi] Arm 9 processors
19715 -mstrongarm[110[0]] StrongARM processors
19716 -mxscale XScale processors
19717 -m[arm]v[2345[t[e]]] Arm architectures
19718 -mall All (except the ARM1)
19719 FP variants:
19720 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19721 -mfpe-old (No float load/store multiples)
19722 -mvfpxd VFP Single precision
19723 -mvfp All VFP
19724 -mno-fpu Disable all floating point instructions
19725
19726 The following CPU names are recognized:
19727 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19728 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19729 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19730 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19731 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19732 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19733 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19734
19735 */
19736
19737const char * md_shortopts = "m:k";
19738
19739#ifdef ARM_BI_ENDIAN
19740#define OPTION_EB (OPTION_MD_BASE + 0)
19741#define OPTION_EL (OPTION_MD_BASE + 1)
19742#else
19743#if TARGET_BYTES_BIG_ENDIAN
19744#define OPTION_EB (OPTION_MD_BASE + 0)
19745#else
19746#define OPTION_EL (OPTION_MD_BASE + 1)
19747#endif
19748#endif
19749
19750struct option md_longopts[] =
19751{
19752#ifdef OPTION_EB
19753 {"EB", no_argument, NULL, OPTION_EB},
19754#endif
19755#ifdef OPTION_EL
19756 {"EL", no_argument, NULL, OPTION_EL},
19757#endif
19758 {NULL, no_argument, NULL, 0}
19759};
19760
19761size_t md_longopts_size = sizeof (md_longopts);
19762
19763struct arm_option_table
19764{
19765 char *option; /* Option name to match. */
19766 char *help; /* Help information. */
19767 int *var; /* Variable to change. */
19768 int value; /* What to change it to. */
19769 char *deprecated; /* If non-null, print this message. */
19770};
19771
19772struct arm_option_table arm_opts[] =
19773{
19774 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
19775 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
19776 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19777 &support_interwork, 1, NULL},
19778 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
19779 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
19780 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
19781 1, NULL},
19782 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
19783 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
19784 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
19785 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
19786 NULL},
19787
19788 /* These are recognized by the assembler, but have no affect on code. */
19789 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
19790 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
19791 {NULL, NULL, NULL, 0, NULL}
19792};
19793
19794struct arm_legacy_option_table
19795{
19796 char *option; /* Option name to match. */
19797 const arm_feature_set **var; /* Variable to change. */
19798 const arm_feature_set value; /* What to change it to. */
19799 char *deprecated; /* If non-null, print this message. */
19800};
19801
19802const struct arm_legacy_option_table arm_legacy_opts[] =
19803{
19804 /* DON'T add any new processors to this list -- we want the whole list
19805 to go away... Add them to the processors table instead. */
19806 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
19807 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
19808 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
19809 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
19810 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
19811 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
19812 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
19813 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
19814 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
19815 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
19816 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
19817 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
19818 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
19819 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
19820 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
19821 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
19822 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
19823 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
19824 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
19825 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
19826 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
19827 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
19828 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
19829 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
19830 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
19831 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
19832 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
19833 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
19834 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
19835 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
19836 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
19837 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
19838 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
19839 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
19840 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
19841 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
19842 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
19843 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
19844 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
19845 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
19846 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
19847 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
19848 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
19849 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
19850 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
19851 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
19852 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19853 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19854 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19855 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19856 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
19857 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
19858 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
19859 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
19860 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
19861 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
19862 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
19863 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
19864 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
19865 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
19866 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
19867 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
19868 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
19869 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
19870 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
19871 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
19872 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
19873 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
19874 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
19875 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
19876 N_("use -mcpu=strongarm110")},
19877 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
19878 N_("use -mcpu=strongarm1100")},
19879 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
19880 N_("use -mcpu=strongarm1110")},
19881 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
19882 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
19883 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
19884
19885 /* Architecture variants -- don't add any more to this list either. */
19886 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
19887 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
19888 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
19889 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
19890 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
19891 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
19892 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
19893 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
19894 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
19895 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
19896 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
19897 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
19898 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
19899 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
19900 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
19901 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
19902 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
19903 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
19904
19905 /* Floating point variants -- don't add any more to this list either. */
19906 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
19907 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
19908 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
19909 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
19910 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
19911
19912 {NULL, NULL, ARM_ARCH_NONE, NULL}
19913};
19914
19915struct arm_cpu_option_table
19916{
19917 char *name;
19918 const arm_feature_set value;
19919 /* For some CPUs we assume an FPU unless the user explicitly sets
19920 -mfpu=... */
19921 const arm_feature_set default_fpu;
19922 /* The canonical name of the CPU, or NULL to use NAME converted to upper
19923 case. */
19924 const char *canonical_name;
19925};
19926
19927/* This list should, at a minimum, contain all the cpu names
19928 recognized by GCC. */
19929static const struct arm_cpu_option_table arm_cpus[] =
19930{
19931 {"all", ARM_ANY, FPU_ARCH_FPA, NULL},
19932 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL},
19933 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL},
19934 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
19935 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
19936 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19937 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19938 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19939 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19940 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19941 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19942 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
19943 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19944 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
19945 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19946 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
19947 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19948 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19949 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19950 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19951 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19952 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19953 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19954 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19955 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19956 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19957 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19958 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19959 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19960 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19961 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19962 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
19963 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
19964 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
19965 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
19966 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
19967 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
19968 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
19969 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19970 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"},
19971 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19972 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19973 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19974 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19975 /* For V5 or later processors we default to using VFP; but the user
19976 should really set the FPU type explicitly. */
19977 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
19978 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
19979 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
19980 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
19981 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
19982 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
19983 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"},
19984 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
19985 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
19986 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"},
19987 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
19988 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
19989 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
19990 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
19991 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
19992 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"},
19993 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
19994 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
19995 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
19996 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
19997 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
19998 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"},
19999 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL},
20000 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"},
20001 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL},
20002 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL},
20003 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL},
20004 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL},
20005 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
20006 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
20007 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
20008 {"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3
20009 | FPU_NEON_EXT_V1),
20010 NULL},
| 1/* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
10
11 This file is part of GAS, the GNU Assembler.
12
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
16 any later version.
17
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26 02110-1301, USA. */
27
28#include <limits.h>
29#include <stdarg.h>
30#define NO_RELOC 0
31#include "as.h"
32#include "safe-ctype.h"
33#include "subsegs.h"
34#include "obstack.h"
35
36#include "opcode/arm.h"
37
38#ifdef OBJ_ELF
39#include "elf/arm.h"
40#include "dw2gencfi.h"
41#endif
42
43#include "dwarf2dbg.h"
44
45#define WARN_DEPRECATED 1
46
47#ifdef OBJ_ELF
48/* Must be at least the size of the largest unwind opcode (currently two). */
49#define ARM_OPCODE_CHUNK_SIZE 8
50
51/* This structure holds the unwinding state. */
52
53static struct
54{
55 symbolS * proc_start;
56 symbolS * table_entry;
57 symbolS * personality_routine;
58 int personality_index;
59 /* The segment containing the function. */
60 segT saved_seg;
61 subsegT saved_subseg;
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes;
64 int opcode_count;
65 int opcode_alloc;
66 /* The number of bytes pushed to the stack. */
67 offsetT frame_size;
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
74 offsetT fp_offset;
75 int fp_reg;
76 /* Nonzero if an unwind_setfp directive has been seen. */
77 unsigned fp_used:1;
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored:1;
80} unwind;
81
82/* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85static unsigned int marked_pr_dependency = 0;
86
87#endif /* OBJ_ELF */
88
89/* Results from operand parsing worker functions. */
90
91typedef enum
92{
93 PARSE_OPERAND_SUCCESS,
94 PARSE_OPERAND_FAIL,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96} parse_operand_result;
97
98enum arm_float_abi
99{
100 ARM_FLOAT_ABI_HARD,
101 ARM_FLOAT_ABI_SOFTFP,
102 ARM_FLOAT_ABI_SOFT
103};
104
105/* Types of processor to assemble for. */
106#ifndef CPU_DEFAULT
107#if defined __XSCALE__
108#define CPU_DEFAULT ARM_ARCH_XSCALE
109#else
110#if defined __thumb__
111#define CPU_DEFAULT ARM_ARCH_V5T
112#endif
113#endif
114#endif
115
116#ifndef FPU_DEFAULT
117# ifdef TE_LINUX
118# define FPU_DEFAULT FPU_ARCH_FPA
119# elif defined (TE_NetBSD)
120# ifdef OBJ_ELF
121# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
122# else
123 /* Legacy a.out format. */
124# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
125# endif
126# elif defined (TE_VXWORKS)
127# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
128# else
129 /* For backwards compatibility, default to FPA. */
130# define FPU_DEFAULT FPU_ARCH_FPA
131# endif
132#endif /* ifndef FPU_DEFAULT */
133
134#define streq(a, b) (strcmp (a, b) == 0)
135
136static arm_feature_set cpu_variant;
137static arm_feature_set arm_arch_used;
138static arm_feature_set thumb_arch_used;
139
140/* Flags stored in private area of BFD structure. */
141static int uses_apcs_26 = FALSE;
142static int atpcs = FALSE;
143static int support_interwork = FALSE;
144static int uses_apcs_float = FALSE;
145static int pic_code = FALSE;
146
147/* Variables that we set while parsing command-line options. Once all
148 options have been read we re-process these values to set the real
149 assembly flags. */
150static const arm_feature_set *legacy_cpu = NULL;
151static const arm_feature_set *legacy_fpu = NULL;
152
153static const arm_feature_set *mcpu_cpu_opt = NULL;
154static const arm_feature_set *mcpu_fpu_opt = NULL;
155static const arm_feature_set *march_cpu_opt = NULL;
156static const arm_feature_set *march_fpu_opt = NULL;
157static const arm_feature_set *mfpu_opt = NULL;
158static const arm_feature_set *object_arch = NULL;
159
160/* Constants for known architecture features. */
161static const arm_feature_set fpu_default = FPU_DEFAULT;
162static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
163static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
164static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
165static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
166static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
167static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
168static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
169static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
170
171#ifdef CPU_DEFAULT
172static const arm_feature_set cpu_default = CPU_DEFAULT;
173#endif
174
175static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
176static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
177static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
178static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
179static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
180static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
181static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
182static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
183static const arm_feature_set arm_ext_v4t_5 =
184 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
185static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
186static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
187static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
188static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
189static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
190static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
191static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0);
192static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
193static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
194static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
195static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
196static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
197static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
198static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
199
200static const arm_feature_set arm_arch_any = ARM_ANY;
201static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
202static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
203static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
204
205static const arm_feature_set arm_cext_iwmmxt2 =
206 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
207static const arm_feature_set arm_cext_iwmmxt =
208 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
209static const arm_feature_set arm_cext_xscale =
210 ARM_FEATURE (0, ARM_CEXT_XSCALE);
211static const arm_feature_set arm_cext_maverick =
212 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
213static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
214static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
215static const arm_feature_set fpu_vfp_ext_v1xd =
216 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
217static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
218static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
219static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
220static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
221static const arm_feature_set fpu_vfp_v3_or_neon_ext =
222 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
223
224static int mfloat_abi_opt = -1;
225/* Record user cpu selection for object attributes. */
226static arm_feature_set selected_cpu = ARM_ARCH_NONE;
227/* Must be long enough to hold any of the names in arm_cpus. */
228static char selected_cpu_name[16];
229#ifdef OBJ_ELF
230# ifdef EABI_DEFAULT
231static int meabi_flags = EABI_DEFAULT;
232# else
233static int meabi_flags = EF_ARM_EABI_UNKNOWN;
234# endif
235
236bfd_boolean
237arm_is_eabi(void)
238{
239 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
240}
241#endif
242
243#ifdef OBJ_ELF
244/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
245symbolS * GOT_symbol;
246#endif
247
248/* 0: assemble for ARM,
249 1: assemble for Thumb,
250 2: assemble for Thumb even though target CPU does not support thumb
251 instructions. */
252static int thumb_mode = 0;
253
254/* If unified_syntax is true, we are processing the new unified
255 ARM/Thumb syntax. Important differences from the old ARM mode:
256
257 - Immediate operands do not require a # prefix.
258 - Conditional affixes always appear at the end of the
259 instruction. (For backward compatibility, those instructions
260 that formerly had them in the middle, continue to accept them
261 there.)
262 - The IT instruction may appear, and if it does is validated
263 against subsequent conditional affixes. It does not generate
264 machine code.
265
266 Important differences from the old Thumb mode:
267
268 - Immediate operands do not require a # prefix.
269 - Most of the V6T2 instructions are only available in unified mode.
270 - The .N and .W suffixes are recognized and honored (it is an error
271 if they cannot be honored).
272 - All instructions set the flags if and only if they have an 's' affix.
273 - Conditional affixes may be used. They are validated against
274 preceding IT instructions. Unlike ARM mode, you cannot use a
275 conditional affix except in the scope of an IT instruction. */
276
277static bfd_boolean unified_syntax = FALSE;
278
279enum neon_el_type
280{
281 NT_invtype,
282 NT_untyped,
283 NT_integer,
284 NT_float,
285 NT_poly,
286 NT_signed,
287 NT_unsigned
288};
289
290struct neon_type_el
291{
292 enum neon_el_type type;
293 unsigned size;
294};
295
296#define NEON_MAX_TYPE_ELS 4
297
298struct neon_type
299{
300 struct neon_type_el el[NEON_MAX_TYPE_ELS];
301 unsigned elems;
302};
303
304struct arm_it
305{
306 const char * error;
307 unsigned long instruction;
308 int size;
309 int size_req;
310 int cond;
311 /* "uncond_value" is set to the value in place of the conditional field in
312 unconditional versions of the instruction, or -1 if nothing is
313 appropriate. */
314 int uncond_value;
315 struct neon_type vectype;
316 /* Set to the opcode if the instruction needs relaxation.
317 Zero if the instruction is not relaxed. */
318 unsigned long relax;
319 struct
320 {
321 bfd_reloc_code_real_type type;
322 expressionS exp;
323 int pc_rel;
324 } reloc;
325
326 struct
327 {
328 unsigned reg;
329 signed int imm;
330 struct neon_type_el vectype;
331 unsigned present : 1; /* Operand present. */
332 unsigned isreg : 1; /* Operand was a register. */
333 unsigned immisreg : 1; /* .imm field is a second register. */
334 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
335 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
336 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
337 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
338 instructions. This allows us to disambiguate ARM <-> vector insns. */
339 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
340 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
341 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
342 unsigned issingle : 1; /* Operand is VFP single-precision register. */
343 unsigned hasreloc : 1; /* Operand has relocation suffix. */
344 unsigned writeback : 1; /* Operand has trailing ! */
345 unsigned preind : 1; /* Preindexed address. */
346 unsigned postind : 1; /* Postindexed address. */
347 unsigned negative : 1; /* Index register was negated. */
348 unsigned shifted : 1; /* Shift applied to operation. */
349 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
350 } operands[6];
351};
352
353static struct arm_it inst;
354
355#define NUM_FLOAT_VALS 8
356
357const char * fp_const[] =
358{
359 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
360};
361
362/* Number of littlenums required to hold an extended precision number. */
363#define MAX_LITTLENUMS 6
364
365LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
366
367#define FAIL (-1)
368#define SUCCESS (0)
369
370#define SUFF_S 1
371#define SUFF_D 2
372#define SUFF_E 3
373#define SUFF_P 4
374
375#define CP_T_X 0x00008000
376#define CP_T_Y 0x00400000
377
378#define CONDS_BIT 0x00100000
379#define LOAD_BIT 0x00100000
380
381#define DOUBLE_LOAD_FLAG 0x00000001
382
383struct asm_cond
384{
385 const char * template;
386 unsigned long value;
387};
388
389#define COND_ALWAYS 0xE
390
391struct asm_psr
392{
393 const char *template;
394 unsigned long field;
395};
396
397struct asm_barrier_opt
398{
399 const char *template;
400 unsigned long value;
401};
402
403/* The bit that distinguishes CPSR and SPSR. */
404#define SPSR_BIT (1 << 22)
405
406/* The individual PSR flag bits. */
407#define PSR_c (1 << 16)
408#define PSR_x (1 << 17)
409#define PSR_s (1 << 18)
410#define PSR_f (1 << 19)
411
412struct reloc_entry
413{
414 char *name;
415 bfd_reloc_code_real_type reloc;
416};
417
418enum vfp_reg_pos
419{
420 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
421 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
422};
423
424enum vfp_ldstm_type
425{
426 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
427};
428
429/* Bits for DEFINED field in neon_typed_alias. */
430#define NTA_HASTYPE 1
431#define NTA_HASINDEX 2
432
433struct neon_typed_alias
434{
435 unsigned char defined;
436 unsigned char index;
437 struct neon_type_el eltype;
438};
439
440/* ARM register categories. This includes coprocessor numbers and various
441 architecture extensions' registers. */
442enum arm_reg_type
443{
444 REG_TYPE_RN,
445 REG_TYPE_CP,
446 REG_TYPE_CN,
447 REG_TYPE_FN,
448 REG_TYPE_VFS,
449 REG_TYPE_VFD,
450 REG_TYPE_NQ,
451 REG_TYPE_VFSD,
452 REG_TYPE_NDQ,
453 REG_TYPE_NSDQ,
454 REG_TYPE_VFC,
455 REG_TYPE_MVF,
456 REG_TYPE_MVD,
457 REG_TYPE_MVFX,
458 REG_TYPE_MVDX,
459 REG_TYPE_MVAX,
460 REG_TYPE_DSPSC,
461 REG_TYPE_MMXWR,
462 REG_TYPE_MMXWC,
463 REG_TYPE_MMXWCG,
464 REG_TYPE_XSCALE,
465};
466
467/* Structure for a hash table entry for a register.
468 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
469 information which states whether a vector type or index is specified (for a
470 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
471struct reg_entry
472{
473 const char *name;
474 unsigned char number;
475 unsigned char type;
476 unsigned char builtin;
477 struct neon_typed_alias *neon;
478};
479
480/* Diagnostics used when we don't get a register of the expected type. */
481const char *const reg_expected_msgs[] =
482{
483 N_("ARM register expected"),
484 N_("bad or missing co-processor number"),
485 N_("co-processor register expected"),
486 N_("FPA register expected"),
487 N_("VFP single precision register expected"),
488 N_("VFP/Neon double precision register expected"),
489 N_("Neon quad precision register expected"),
490 N_("VFP single or double precision register expected"),
491 N_("Neon double or quad precision register expected"),
492 N_("VFP single, double or Neon quad precision register expected"),
493 N_("VFP system register expected"),
494 N_("Maverick MVF register expected"),
495 N_("Maverick MVD register expected"),
496 N_("Maverick MVFX register expected"),
497 N_("Maverick MVDX register expected"),
498 N_("Maverick MVAX register expected"),
499 N_("Maverick DSPSC register expected"),
500 N_("iWMMXt data register expected"),
501 N_("iWMMXt control register expected"),
502 N_("iWMMXt scalar register expected"),
503 N_("XScale accumulator register expected"),
504};
505
506/* Some well known registers that we refer to directly elsewhere. */
507#define REG_SP 13
508#define REG_LR 14
509#define REG_PC 15
510
511/* ARM instructions take 4bytes in the object file, Thumb instructions
512 take 2: */
513#define INSN_SIZE 4
514
515struct asm_opcode
516{
517 /* Basic string to match. */
518 const char *template;
519
520 /* Parameters to instruction. */
521 unsigned char operands[8];
522
523 /* Conditional tag - see opcode_lookup. */
524 unsigned int tag : 4;
525
526 /* Basic instruction code. */
527 unsigned int avalue : 28;
528
529 /* Thumb-format instruction code. */
530 unsigned int tvalue;
531
532 /* Which architecture variant provides this instruction. */
533 const arm_feature_set *avariant;
534 const arm_feature_set *tvariant;
535
536 /* Function to call to encode instruction in ARM format. */
537 void (* aencode) (void);
538
539 /* Function to call to encode instruction in Thumb format. */
540 void (* tencode) (void);
541};
542
543/* Defines for various bits that we will want to toggle. */
544#define INST_IMMEDIATE 0x02000000
545#define OFFSET_REG 0x02000000
546#define HWOFFSET_IMM 0x00400000
547#define SHIFT_BY_REG 0x00000010
548#define PRE_INDEX 0x01000000
549#define INDEX_UP 0x00800000
550#define WRITE_BACK 0x00200000
551#define LDM_TYPE_2_OR_3 0x00400000
552#define CPSI_MMOD 0x00020000
553
554#define LITERAL_MASK 0xf000f000
555#define OPCODE_MASK 0xfe1fffff
556#define V4_STR_BIT 0x00000020
557
558#define T2_SUBS_PC_LR 0xf3de8f00
559
560#define DATA_OP_SHIFT 21
561
562#define T2_OPCODE_MASK 0xfe1fffff
563#define T2_DATA_OP_SHIFT 21
564
565/* Codes to distinguish the arithmetic instructions. */
566#define OPCODE_AND 0
567#define OPCODE_EOR 1
568#define OPCODE_SUB 2
569#define OPCODE_RSB 3
570#define OPCODE_ADD 4
571#define OPCODE_ADC 5
572#define OPCODE_SBC 6
573#define OPCODE_RSC 7
574#define OPCODE_TST 8
575#define OPCODE_TEQ 9
576#define OPCODE_CMP 10
577#define OPCODE_CMN 11
578#define OPCODE_ORR 12
579#define OPCODE_MOV 13
580#define OPCODE_BIC 14
581#define OPCODE_MVN 15
582
583#define T2_OPCODE_AND 0
584#define T2_OPCODE_BIC 1
585#define T2_OPCODE_ORR 2
586#define T2_OPCODE_ORN 3
587#define T2_OPCODE_EOR 4
588#define T2_OPCODE_ADD 8
589#define T2_OPCODE_ADC 10
590#define T2_OPCODE_SBC 11
591#define T2_OPCODE_SUB 13
592#define T2_OPCODE_RSB 14
593
594#define T_OPCODE_MUL 0x4340
595#define T_OPCODE_TST 0x4200
596#define T_OPCODE_CMN 0x42c0
597#define T_OPCODE_NEG 0x4240
598#define T_OPCODE_MVN 0x43c0
599
600#define T_OPCODE_ADD_R3 0x1800
601#define T_OPCODE_SUB_R3 0x1a00
602#define T_OPCODE_ADD_HI 0x4400
603#define T_OPCODE_ADD_ST 0xb000
604#define T_OPCODE_SUB_ST 0xb080
605#define T_OPCODE_ADD_SP 0xa800
606#define T_OPCODE_ADD_PC 0xa000
607#define T_OPCODE_ADD_I8 0x3000
608#define T_OPCODE_SUB_I8 0x3800
609#define T_OPCODE_ADD_I3 0x1c00
610#define T_OPCODE_SUB_I3 0x1e00
611
612#define T_OPCODE_ASR_R 0x4100
613#define T_OPCODE_LSL_R 0x4080
614#define T_OPCODE_LSR_R 0x40c0
615#define T_OPCODE_ROR_R 0x41c0
616#define T_OPCODE_ASR_I 0x1000
617#define T_OPCODE_LSL_I 0x0000
618#define T_OPCODE_LSR_I 0x0800
619
620#define T_OPCODE_MOV_I8 0x2000
621#define T_OPCODE_CMP_I8 0x2800
622#define T_OPCODE_CMP_LR 0x4280
623#define T_OPCODE_MOV_HR 0x4600
624#define T_OPCODE_CMP_HR 0x4500
625
626#define T_OPCODE_LDR_PC 0x4800
627#define T_OPCODE_LDR_SP 0x9800
628#define T_OPCODE_STR_SP 0x9000
629#define T_OPCODE_LDR_IW 0x6800
630#define T_OPCODE_STR_IW 0x6000
631#define T_OPCODE_LDR_IH 0x8800
632#define T_OPCODE_STR_IH 0x8000
633#define T_OPCODE_LDR_IB 0x7800
634#define T_OPCODE_STR_IB 0x7000
635#define T_OPCODE_LDR_RW 0x5800
636#define T_OPCODE_STR_RW 0x5000
637#define T_OPCODE_LDR_RH 0x5a00
638#define T_OPCODE_STR_RH 0x5200
639#define T_OPCODE_LDR_RB 0x5c00
640#define T_OPCODE_STR_RB 0x5400
641
642#define T_OPCODE_PUSH 0xb400
643#define T_OPCODE_POP 0xbc00
644
645#define T_OPCODE_BRANCH 0xe000
646
647#define THUMB_SIZE 2 /* Size of thumb instruction. */
648#define THUMB_PP_PC_LR 0x0100
649#define THUMB_LOAD_BIT 0x0800
650#define THUMB2_LOAD_BIT 0x00100000
651
652#define BAD_ARGS _("bad arguments to instruction")
653#define BAD_PC _("r15 not allowed here")
654#define BAD_COND _("instruction cannot be conditional")
655#define BAD_OVERLAP _("registers may not be the same")
656#define BAD_HIREG _("lo register required")
657#define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
658#define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
659#define BAD_BRANCH _("branch must be last instruction in IT block")
660#define BAD_NOT_IT _("instruction not allowed in IT block")
661#define BAD_FPU _("selected FPU does not support instruction")
662
663static struct hash_control *arm_ops_hsh;
664static struct hash_control *arm_cond_hsh;
665static struct hash_control *arm_shift_hsh;
666static struct hash_control *arm_psr_hsh;
667static struct hash_control *arm_v7m_psr_hsh;
668static struct hash_control *arm_reg_hsh;
669static struct hash_control *arm_reloc_hsh;
670static struct hash_control *arm_barrier_opt_hsh;
671
672/* Stuff needed to resolve the label ambiguity
673 As:
674 ...
675 label: <insn>
676 may differ from:
677 ...
678 label:
679 <insn>
680*/
681
682symbolS * last_label_seen;
683static int label_is_thumb_function_name = FALSE;
684
685/* Literal pool structure. Held on a per-section
686 and per-sub-section basis. */
687
688#define MAX_LITERAL_POOL_SIZE 1024
689typedef struct literal_pool
690{
691 expressionS literals [MAX_LITERAL_POOL_SIZE];
692 unsigned int next_free_entry;
693 unsigned int id;
694 symbolS * symbol;
695 segT section;
696 subsegT sub_section;
697 struct literal_pool * next;
698} literal_pool;
699
700/* Pointer to a linked list of literal pools. */
701literal_pool * list_of_pools = NULL;
702
703/* State variables for IT block handling. */
704static bfd_boolean current_it_mask = 0;
705static int current_cc;
706
707
708/* Pure syntax. */
709
710/* This array holds the chars that always start a comment. If the
711 pre-processor is disabled, these aren't very useful. */
712const char comment_chars[] = "@";
713
714/* This array holds the chars that only start a comment at the beginning of
715 a line. If the line seems to have the form '# 123 filename'
716 .line and .file directives will appear in the pre-processed output. */
717/* Note that input_file.c hand checks for '#' at the beginning of the
718 first line of the input file. This is because the compiler outputs
719 #NO_APP at the beginning of its output. */
720/* Also note that comments like this one will always work. */
721const char line_comment_chars[] = "#";
722
723const char line_separator_chars[] = ";";
724
725/* Chars that can be used to separate mant
726 from exp in floating point numbers. */
727const char EXP_CHARS[] = "eE";
728
729/* Chars that mean this number is a floating point constant. */
730/* As in 0f12.456 */
731/* or 0d1.2345e12 */
732
733const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
734
735/* Prefix characters that indicate the start of an immediate
736 value. */
737#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
738
739/* Separator character handling. */
740
741#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
742
743static inline int
744skip_past_char (char ** str, char c)
745{
746 if (**str == c)
747 {
748 (*str)++;
749 return SUCCESS;
750 }
751 else
752 return FAIL;
753}
754#define skip_past_comma(str) skip_past_char (str, ',')
755
756/* Arithmetic expressions (possibly involving symbols). */
757
758/* Return TRUE if anything in the expression is a bignum. */
759
760static int
761walk_no_bignums (symbolS * sp)
762{
763 if (symbol_get_value_expression (sp)->X_op == O_big)
764 return 1;
765
766 if (symbol_get_value_expression (sp)->X_add_symbol)
767 {
768 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
769 || (symbol_get_value_expression (sp)->X_op_symbol
770 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
771 }
772
773 return 0;
774}
775
776static int in_my_get_expression = 0;
777
778/* Third argument to my_get_expression. */
779#define GE_NO_PREFIX 0
780#define GE_IMM_PREFIX 1
781#define GE_OPT_PREFIX 2
782/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
783 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
784#define GE_OPT_PREFIX_BIG 3
785
786static int
787my_get_expression (expressionS * ep, char ** str, int prefix_mode)
788{
789 char * save_in;
790 segT seg;
791
792 /* In unified syntax, all prefixes are optional. */
793 if (unified_syntax)
794 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
795 : GE_OPT_PREFIX;
796
797 switch (prefix_mode)
798 {
799 case GE_NO_PREFIX: break;
800 case GE_IMM_PREFIX:
801 if (!is_immediate_prefix (**str))
802 {
803 inst.error = _("immediate expression requires a # prefix");
804 return FAIL;
805 }
806 (*str)++;
807 break;
808 case GE_OPT_PREFIX:
809 case GE_OPT_PREFIX_BIG:
810 if (is_immediate_prefix (**str))
811 (*str)++;
812 break;
813 default: abort ();
814 }
815
816 memset (ep, 0, sizeof (expressionS));
817
818 save_in = input_line_pointer;
819 input_line_pointer = *str;
820 in_my_get_expression = 1;
821 seg = expression (ep);
822 in_my_get_expression = 0;
823
824 if (ep->X_op == O_illegal)
825 {
826 /* We found a bad expression in md_operand(). */
827 *str = input_line_pointer;
828 input_line_pointer = save_in;
829 if (inst.error == NULL)
830 inst.error = _("bad expression");
831 return 1;
832 }
833
834#ifdef OBJ_AOUT
835 if (seg != absolute_section
836 && seg != text_section
837 && seg != data_section
838 && seg != bss_section
839 && seg != undefined_section)
840 {
841 inst.error = _("bad segment");
842 *str = input_line_pointer;
843 input_line_pointer = save_in;
844 return 1;
845 }
846#endif
847
848 /* Get rid of any bignums now, so that we don't generate an error for which
849 we can't establish a line number later on. Big numbers are never valid
850 in instructions, which is where this routine is always called. */
851 if (prefix_mode != GE_OPT_PREFIX_BIG
852 && (ep->X_op == O_big
853 || (ep->X_add_symbol
854 && (walk_no_bignums (ep->X_add_symbol)
855 || (ep->X_op_symbol
856 && walk_no_bignums (ep->X_op_symbol))))))
857 {
858 inst.error = _("invalid constant");
859 *str = input_line_pointer;
860 input_line_pointer = save_in;
861 return 1;
862 }
863
864 *str = input_line_pointer;
865 input_line_pointer = save_in;
866 return 0;
867}
868
869/* Turn a string in input_line_pointer into a floating point constant
870 of type TYPE, and store the appropriate bytes in *LITP. The number
871 of LITTLENUMS emitted is stored in *SIZEP. An error message is
872 returned, or NULL on OK.
873
874 Note that fp constants aren't represent in the normal way on the ARM.
875 In big endian mode, things are as expected. However, in little endian
876 mode fp constants are big-endian word-wise, and little-endian byte-wise
877 within the words. For example, (double) 1.1 in big endian mode is
878 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
879 the byte sequence 99 99 f1 3f 9a 99 99 99.
880
881 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
882
883char *
884md_atof (int type, char * litP, int * sizeP)
885{
886 int prec;
887 LITTLENUM_TYPE words[MAX_LITTLENUMS];
888 char *t;
889 int i;
890
891 switch (type)
892 {
893 case 'f':
894 case 'F':
895 case 's':
896 case 'S':
897 prec = 2;
898 break;
899
900 case 'd':
901 case 'D':
902 case 'r':
903 case 'R':
904 prec = 4;
905 break;
906
907 case 'x':
908 case 'X':
909 prec = 6;
910 break;
911
912 case 'p':
913 case 'P':
914 prec = 6;
915 break;
916
917 default:
918 *sizeP = 0;
919 return _("bad call to MD_ATOF()");
920 }
921
922 t = atof_ieee (input_line_pointer, type, words);
923 if (t)
924 input_line_pointer = t;
925 *sizeP = prec * 2;
926
927 if (target_big_endian)
928 {
929 for (i = 0; i < prec; i++)
930 {
931 md_number_to_chars (litP, (valueT) words[i], 2);
932 litP += 2;
933 }
934 }
935 else
936 {
937 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
938 for (i = prec - 1; i >= 0; i--)
939 {
940 md_number_to_chars (litP, (valueT) words[i], 2);
941 litP += 2;
942 }
943 else
944 /* For a 4 byte float the order of elements in `words' is 1 0.
945 For an 8 byte float the order is 1 0 3 2. */
946 for (i = 0; i < prec; i += 2)
947 {
948 md_number_to_chars (litP, (valueT) words[i + 1], 2);
949 md_number_to_chars (litP + 2, (valueT) words[i], 2);
950 litP += 4;
951 }
952 }
953
954 return 0;
955}
956
957/* We handle all bad expressions here, so that we can report the faulty
958 instruction in the error message. */
959void
960md_operand (expressionS * expr)
961{
962 if (in_my_get_expression)
963 expr->X_op = O_illegal;
964}
965
966/* Immediate values. */
967
968/* Generic immediate-value read function for use in directives.
969 Accepts anything that 'expression' can fold to a constant.
970 *val receives the number. */
971#ifdef OBJ_ELF
972static int
973immediate_for_directive (int *val)
974{
975 expressionS exp;
976 exp.X_op = O_illegal;
977
978 if (is_immediate_prefix (*input_line_pointer))
979 {
980 input_line_pointer++;
981 expression (&exp);
982 }
983
984 if (exp.X_op != O_constant)
985 {
986 as_bad (_("expected #constant"));
987 ignore_rest_of_line ();
988 return FAIL;
989 }
990 *val = exp.X_add_number;
991 return SUCCESS;
992}
993#endif
994
995/* Register parsing. */
996
997/* Generic register parser. CCP points to what should be the
998 beginning of a register name. If it is indeed a valid register
999 name, advance CCP over it and return the reg_entry structure;
1000 otherwise return NULL. Does not issue diagnostics. */
1001
1002static struct reg_entry *
1003arm_reg_parse_multi (char **ccp)
1004{
1005 char *start = *ccp;
1006 char *p;
1007 struct reg_entry *reg;
1008
1009#ifdef REGISTER_PREFIX
1010 if (*start != REGISTER_PREFIX)
1011 return NULL;
1012 start++;
1013#endif
1014#ifdef OPTIONAL_REGISTER_PREFIX
1015 if (*start == OPTIONAL_REGISTER_PREFIX)
1016 start++;
1017#endif
1018
1019 p = start;
1020 if (!ISALPHA (*p) || !is_name_beginner (*p))
1021 return NULL;
1022
1023 do
1024 p++;
1025 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1026
1027 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1028
1029 if (!reg)
1030 return NULL;
1031
1032 *ccp = p;
1033 return reg;
1034}
1035
1036static int
1037arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1038 enum arm_reg_type type)
1039{
1040 /* Alternative syntaxes are accepted for a few register classes. */
1041 switch (type)
1042 {
1043 case REG_TYPE_MVF:
1044 case REG_TYPE_MVD:
1045 case REG_TYPE_MVFX:
1046 case REG_TYPE_MVDX:
1047 /* Generic coprocessor register names are allowed for these. */
1048 if (reg && reg->type == REG_TYPE_CN)
1049 return reg->number;
1050 break;
1051
1052 case REG_TYPE_CP:
1053 /* For backward compatibility, a bare number is valid here. */
1054 {
1055 unsigned long processor = strtoul (start, ccp, 10);
1056 if (*ccp != start && processor <= 15)
1057 return processor;
1058 }
1059
1060 case REG_TYPE_MMXWC:
1061 /* WC includes WCG. ??? I'm not sure this is true for all
1062 instructions that take WC registers. */
1063 if (reg && reg->type == REG_TYPE_MMXWCG)
1064 return reg->number;
1065 break;
1066
1067 default:
1068 break;
1069 }
1070
1071 return FAIL;
1072}
1073
1074/* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1075 return value is the register number or FAIL. */
1076
1077static int
1078arm_reg_parse (char **ccp, enum arm_reg_type type)
1079{
1080 char *start = *ccp;
1081 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1082 int ret;
1083
1084 /* Do not allow a scalar (reg+index) to parse as a register. */
1085 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1086 return FAIL;
1087
1088 if (reg && reg->type == type)
1089 return reg->number;
1090
1091 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1092 return ret;
1093
1094 *ccp = start;
1095 return FAIL;
1096}
1097
1098/* Parse a Neon type specifier. *STR should point at the leading '.'
1099 character. Does no verification at this stage that the type fits the opcode
1100 properly. E.g.,
1101
1102 .i32.i32.s16
1103 .s32.f32
1104 .u16
1105
1106 Can all be legally parsed by this function.
1107
1108 Fills in neon_type struct pointer with parsed information, and updates STR
1109 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1110 type, FAIL if not. */
1111
1112static int
1113parse_neon_type (struct neon_type *type, char **str)
1114{
1115 char *ptr = *str;
1116
1117 if (type)
1118 type->elems = 0;
1119
1120 while (type->elems < NEON_MAX_TYPE_ELS)
1121 {
1122 enum neon_el_type thistype = NT_untyped;
1123 unsigned thissize = -1u;
1124
1125 if (*ptr != '.')
1126 break;
1127
1128 ptr++;
1129
1130 /* Just a size without an explicit type. */
1131 if (ISDIGIT (*ptr))
1132 goto parsesize;
1133
1134 switch (TOLOWER (*ptr))
1135 {
1136 case 'i': thistype = NT_integer; break;
1137 case 'f': thistype = NT_float; break;
1138 case 'p': thistype = NT_poly; break;
1139 case 's': thistype = NT_signed; break;
1140 case 'u': thistype = NT_unsigned; break;
1141 case 'd':
1142 thistype = NT_float;
1143 thissize = 64;
1144 ptr++;
1145 goto done;
1146 default:
1147 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1148 return FAIL;
1149 }
1150
1151 ptr++;
1152
1153 /* .f is an abbreviation for .f32. */
1154 if (thistype == NT_float && !ISDIGIT (*ptr))
1155 thissize = 32;
1156 else
1157 {
1158 parsesize:
1159 thissize = strtoul (ptr, &ptr, 10);
1160
1161 if (thissize != 8 && thissize != 16 && thissize != 32
1162 && thissize != 64)
1163 {
1164 as_bad (_("bad size %d in type specifier"), thissize);
1165 return FAIL;
1166 }
1167 }
1168
1169 done:
1170 if (type)
1171 {
1172 type->el[type->elems].type = thistype;
1173 type->el[type->elems].size = thissize;
1174 type->elems++;
1175 }
1176 }
1177
1178 /* Empty/missing type is not a successful parse. */
1179 if (type->elems == 0)
1180 return FAIL;
1181
1182 *str = ptr;
1183
1184 return SUCCESS;
1185}
1186
1187/* Errors may be set multiple times during parsing or bit encoding
1188 (particularly in the Neon bits), but usually the earliest error which is set
1189 will be the most meaningful. Avoid overwriting it with later (cascading)
1190 errors by calling this function. */
1191
1192static void
1193first_error (const char *err)
1194{
1195 if (!inst.error)
1196 inst.error = err;
1197}
1198
1199/* Parse a single type, e.g. ".s32", leading period included. */
1200static int
1201parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1202{
1203 char *str = *ccp;
1204 struct neon_type optype;
1205
1206 if (*str == '.')
1207 {
1208 if (parse_neon_type (&optype, &str) == SUCCESS)
1209 {
1210 if (optype.elems == 1)
1211 *vectype = optype.el[0];
1212 else
1213 {
1214 first_error (_("only one type should be specified for operand"));
1215 return FAIL;
1216 }
1217 }
1218 else
1219 {
1220 first_error (_("vector type expected"));
1221 return FAIL;
1222 }
1223 }
1224 else
1225 return FAIL;
1226
1227 *ccp = str;
1228
1229 return SUCCESS;
1230}
1231
1232/* Special meanings for indices (which have a range of 0-7), which will fit into
1233 a 4-bit integer. */
1234
1235#define NEON_ALL_LANES 15
1236#define NEON_INTERLEAVE_LANES 14
1237
1238/* Parse either a register or a scalar, with an optional type. Return the
1239 register number, and optionally fill in the actual type of the register
1240 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1241 type/index information in *TYPEINFO. */
1242
1243static int
1244parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1245 enum arm_reg_type *rtype,
1246 struct neon_typed_alias *typeinfo)
1247{
1248 char *str = *ccp;
1249 struct reg_entry *reg = arm_reg_parse_multi (&str);
1250 struct neon_typed_alias atype;
1251 struct neon_type_el parsetype;
1252
1253 atype.defined = 0;
1254 atype.index = -1;
1255 atype.eltype.type = NT_invtype;
1256 atype.eltype.size = -1;
1257
1258 /* Try alternate syntax for some types of register. Note these are mutually
1259 exclusive with the Neon syntax extensions. */
1260 if (reg == NULL)
1261 {
1262 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1263 if (altreg != FAIL)
1264 *ccp = str;
1265 if (typeinfo)
1266 *typeinfo = atype;
1267 return altreg;
1268 }
1269
1270 /* Undo polymorphism when a set of register types may be accepted. */
1271 if ((type == REG_TYPE_NDQ
1272 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1273 || (type == REG_TYPE_VFSD
1274 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1275 || (type == REG_TYPE_NSDQ
1276 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1277 || reg->type == REG_TYPE_NQ))
1278 || (type == REG_TYPE_MMXWC
1279 && (reg->type == REG_TYPE_MMXWCG)))
1280 type = reg->type;
1281
1282 if (type != reg->type)
1283 return FAIL;
1284
1285 if (reg->neon)
1286 atype = *reg->neon;
1287
1288 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1289 {
1290 if ((atype.defined & NTA_HASTYPE) != 0)
1291 {
1292 first_error (_("can't redefine type for operand"));
1293 return FAIL;
1294 }
1295 atype.defined |= NTA_HASTYPE;
1296 atype.eltype = parsetype;
1297 }
1298
1299 if (skip_past_char (&str, '[') == SUCCESS)
1300 {
1301 if (type != REG_TYPE_VFD)
1302 {
1303 first_error (_("only D registers may be indexed"));
1304 return FAIL;
1305 }
1306
1307 if ((atype.defined & NTA_HASINDEX) != 0)
1308 {
1309 first_error (_("can't change index for operand"));
1310 return FAIL;
1311 }
1312
1313 atype.defined |= NTA_HASINDEX;
1314
1315 if (skip_past_char (&str, ']') == SUCCESS)
1316 atype.index = NEON_ALL_LANES;
1317 else
1318 {
1319 expressionS exp;
1320
1321 my_get_expression (&exp, &str, GE_NO_PREFIX);
1322
1323 if (exp.X_op != O_constant)
1324 {
1325 first_error (_("constant expression required"));
1326 return FAIL;
1327 }
1328
1329 if (skip_past_char (&str, ']') == FAIL)
1330 return FAIL;
1331
1332 atype.index = exp.X_add_number;
1333 }
1334 }
1335
1336 if (typeinfo)
1337 *typeinfo = atype;
1338
1339 if (rtype)
1340 *rtype = type;
1341
1342 *ccp = str;
1343
1344 return reg->number;
1345}
1346
1347/* Like arm_reg_parse, but allow allow the following extra features:
1348 - If RTYPE is non-zero, return the (possibly restricted) type of the
1349 register (e.g. Neon double or quad reg when either has been requested).
1350 - If this is a Neon vector type with additional type information, fill
1351 in the struct pointed to by VECTYPE (if non-NULL).
1352 This function will fault on encountering a scalar.
1353*/
1354
1355static int
1356arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1357 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1358{
1359 struct neon_typed_alias atype;
1360 char *str = *ccp;
1361 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1362
1363 if (reg == FAIL)
1364 return FAIL;
1365
1366 /* Do not allow a scalar (reg+index) to parse as a register. */
1367 if ((atype.defined & NTA_HASINDEX) != 0)
1368 {
1369 first_error (_("register operand expected, but got scalar"));
1370 return FAIL;
1371 }
1372
1373 if (vectype)
1374 *vectype = atype.eltype;
1375
1376 *ccp = str;
1377
1378 return reg;
1379}
1380
1381#define NEON_SCALAR_REG(X) ((X) >> 4)
1382#define NEON_SCALAR_INDEX(X) ((X) & 15)
1383
1384/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1385 have enough information to be able to do a good job bounds-checking. So, we
1386 just do easy checks here, and do further checks later. */
1387
1388static int
1389parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1390{
1391 int reg;
1392 char *str = *ccp;
1393 struct neon_typed_alias atype;
1394
1395 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1396
1397 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1398 return FAIL;
1399
1400 if (atype.index == NEON_ALL_LANES)
1401 {
1402 first_error (_("scalar must have an index"));
1403 return FAIL;
1404 }
1405 else if (atype.index >= 64 / elsize)
1406 {
1407 first_error (_("scalar index out of range"));
1408 return FAIL;
1409 }
1410
1411 if (type)
1412 *type = atype.eltype;
1413
1414 *ccp = str;
1415
1416 return reg * 16 + atype.index;
1417}
1418
1419/* Parse an ARM register list. Returns the bitmask, or FAIL. */
1420static long
1421parse_reg_list (char ** strp)
1422{
1423 char * str = * strp;
1424 long range = 0;
1425 int another_range;
1426
1427 /* We come back here if we get ranges concatenated by '+' or '|'. */
1428 do
1429 {
1430 another_range = 0;
1431
1432 if (*str == '{')
1433 {
1434 int in_range = 0;
1435 int cur_reg = -1;
1436
1437 str++;
1438 do
1439 {
1440 int reg;
1441
1442 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1443 {
1444 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1445 return FAIL;
1446 }
1447
1448 if (in_range)
1449 {
1450 int i;
1451
1452 if (reg <= cur_reg)
1453 {
1454 first_error (_("bad range in register list"));
1455 return FAIL;
1456 }
1457
1458 for (i = cur_reg + 1; i < reg; i++)
1459 {
1460 if (range & (1 << i))
1461 as_tsktsk
1462 (_("Warning: duplicated register (r%d) in register list"),
1463 i);
1464 else
1465 range |= 1 << i;
1466 }
1467 in_range = 0;
1468 }
1469
1470 if (range & (1 << reg))
1471 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1472 reg);
1473 else if (reg <= cur_reg)
1474 as_tsktsk (_("Warning: register range not in ascending order"));
1475
1476 range |= 1 << reg;
1477 cur_reg = reg;
1478 }
1479 while (skip_past_comma (&str) != FAIL
1480 || (in_range = 1, *str++ == '-'));
1481 str--;
1482
1483 if (*str++ != '}')
1484 {
1485 first_error (_("missing `}'"));
1486 return FAIL;
1487 }
1488 }
1489 else
1490 {
1491 expressionS expr;
1492
1493 if (my_get_expression (&expr, &str, GE_NO_PREFIX))
1494 return FAIL;
1495
1496 if (expr.X_op == O_constant)
1497 {
1498 if (expr.X_add_number
1499 != (expr.X_add_number & 0x0000ffff))
1500 {
1501 inst.error = _("invalid register mask");
1502 return FAIL;
1503 }
1504
1505 if ((range & expr.X_add_number) != 0)
1506 {
1507 int regno = range & expr.X_add_number;
1508
1509 regno &= -regno;
1510 regno = (1 << regno) - 1;
1511 as_tsktsk
1512 (_("Warning: duplicated register (r%d) in register list"),
1513 regno);
1514 }
1515
1516 range |= expr.X_add_number;
1517 }
1518 else
1519 {
1520 if (inst.reloc.type != 0)
1521 {
1522 inst.error = _("expression too complex");
1523 return FAIL;
1524 }
1525
1526 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
1527 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1528 inst.reloc.pc_rel = 0;
1529 }
1530 }
1531
1532 if (*str == '|' || *str == '+')
1533 {
1534 str++;
1535 another_range = 1;
1536 }
1537 }
1538 while (another_range);
1539
1540 *strp = str;
1541 return range;
1542}
1543
1544/* Types of registers in a list. */
1545
1546enum reg_list_els
1547{
1548 REGLIST_VFP_S,
1549 REGLIST_VFP_D,
1550 REGLIST_NEON_D
1551};
1552
1553/* Parse a VFP register list. If the string is invalid return FAIL.
1554 Otherwise return the number of registers, and set PBASE to the first
1555 register. Parses registers of type ETYPE.
1556 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1557 - Q registers can be used to specify pairs of D registers
1558 - { } can be omitted from around a singleton register list
1559 FIXME: This is not implemented, as it would require backtracking in
1560 some cases, e.g.:
1561 vtbl.8 d3,d4,d5
1562 This could be done (the meaning isn't really ambiguous), but doesn't
1563 fit in well with the current parsing framework.
1564 - 32 D registers may be used (also true for VFPv3).
1565 FIXME: Types are ignored in these register lists, which is probably a
1566 bug. */
1567
1568static int
1569parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1570{
1571 char *str = *ccp;
1572 int base_reg;
1573 int new_base;
1574 enum arm_reg_type regtype = 0;
1575 int max_regs = 0;
1576 int count = 0;
1577 int warned = 0;
1578 unsigned long mask = 0;
1579 int i;
1580
1581 if (*str != '{')
1582 {
1583 inst.error = _("expecting {");
1584 return FAIL;
1585 }
1586
1587 str++;
1588
1589 switch (etype)
1590 {
1591 case REGLIST_VFP_S:
1592 regtype = REG_TYPE_VFS;
1593 max_regs = 32;
1594 break;
1595
1596 case REGLIST_VFP_D:
1597 regtype = REG_TYPE_VFD;
1598 break;
1599
1600 case REGLIST_NEON_D:
1601 regtype = REG_TYPE_NDQ;
1602 break;
1603 }
1604
1605 if (etype != REGLIST_VFP_S)
1606 {
1607 /* VFPv3 allows 32 D registers. */
1608 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
1609 {
1610 max_regs = 32;
1611 if (thumb_mode)
1612 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1613 fpu_vfp_ext_v3);
1614 else
1615 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1616 fpu_vfp_ext_v3);
1617 }
1618 else
1619 max_regs = 16;
1620 }
1621
1622 base_reg = max_regs;
1623
1624 do
1625 {
1626 int setmask = 1, addregs = 1;
1627
1628 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1629
1630 if (new_base == FAIL)
1631 {
1632 first_error (_(reg_expected_msgs[regtype]));
1633 return FAIL;
1634 }
1635
1636 if (new_base >= max_regs)
1637 {
1638 first_error (_("register out of range in list"));
1639 return FAIL;
1640 }
1641
1642 /* Note: a value of 2 * n is returned for the register Q<n>. */
1643 if (regtype == REG_TYPE_NQ)
1644 {
1645 setmask = 3;
1646 addregs = 2;
1647 }
1648
1649 if (new_base < base_reg)
1650 base_reg = new_base;
1651
1652 if (mask & (setmask << new_base))
1653 {
1654 first_error (_("invalid register list"));
1655 return FAIL;
1656 }
1657
1658 if ((mask >> new_base) != 0 && ! warned)
1659 {
1660 as_tsktsk (_("register list not in ascending order"));
1661 warned = 1;
1662 }
1663
1664 mask |= setmask << new_base;
1665 count += addregs;
1666
1667 if (*str == '-') /* We have the start of a range expression */
1668 {
1669 int high_range;
1670
1671 str++;
1672
1673 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1674 == FAIL)
1675 {
1676 inst.error = gettext (reg_expected_msgs[regtype]);
1677 return FAIL;
1678 }
1679
1680 if (high_range >= max_regs)
1681 {
1682 first_error (_("register out of range in list"));
1683 return FAIL;
1684 }
1685
1686 if (regtype == REG_TYPE_NQ)
1687 high_range = high_range + 1;
1688
1689 if (high_range <= new_base)
1690 {
1691 inst.error = _("register range not in ascending order");
1692 return FAIL;
1693 }
1694
1695 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1696 {
1697 if (mask & (setmask << new_base))
1698 {
1699 inst.error = _("invalid register list");
1700 return FAIL;
1701 }
1702
1703 mask |= setmask << new_base;
1704 count += addregs;
1705 }
1706 }
1707 }
1708 while (skip_past_comma (&str) != FAIL);
1709
1710 str++;
1711
1712 /* Sanity check -- should have raised a parse error above. */
1713 if (count == 0 || count > max_regs)
1714 abort ();
1715
1716 *pbase = base_reg;
1717
1718 /* Final test -- the registers must be consecutive. */
1719 mask >>= base_reg;
1720 for (i = 0; i < count; i++)
1721 {
1722 if ((mask & (1u << i)) == 0)
1723 {
1724 inst.error = _("non-contiguous register range");
1725 return FAIL;
1726 }
1727 }
1728
1729 *ccp = str;
1730
1731 return count;
1732}
1733
1734/* True if two alias types are the same. */
1735
1736static int
1737neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1738{
1739 if (!a && !b)
1740 return 1;
1741
1742 if (!a || !b)
1743 return 0;
1744
1745 if (a->defined != b->defined)
1746 return 0;
1747
1748 if ((a->defined & NTA_HASTYPE) != 0
1749 && (a->eltype.type != b->eltype.type
1750 || a->eltype.size != b->eltype.size))
1751 return 0;
1752
1753 if ((a->defined & NTA_HASINDEX) != 0
1754 && (a->index != b->index))
1755 return 0;
1756
1757 return 1;
1758}
1759
1760/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1761 The base register is put in *PBASE.
1762 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1763 the return value.
1764 The register stride (minus one) is put in bit 4 of the return value.
1765 Bits [6:5] encode the list length (minus one).
1766 The type of the list elements is put in *ELTYPE, if non-NULL. */
1767
1768#define NEON_LANE(X) ((X) & 0xf)
1769#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1770#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1771
1772static int
1773parse_neon_el_struct_list (char **str, unsigned *pbase,
1774 struct neon_type_el *eltype)
1775{
1776 char *ptr = *str;
1777 int base_reg = -1;
1778 int reg_incr = -1;
1779 int count = 0;
1780 int lane = -1;
1781 int leading_brace = 0;
1782 enum arm_reg_type rtype = REG_TYPE_NDQ;
1783 int addregs = 1;
1784 const char *const incr_error = "register stride must be 1 or 2";
1785 const char *const type_error = "mismatched element/structure types in list";
1786 struct neon_typed_alias firsttype;
1787
1788 if (skip_past_char (&ptr, '{') == SUCCESS)
1789 leading_brace = 1;
1790
1791 do
1792 {
1793 struct neon_typed_alias atype;
1794 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1795
1796 if (getreg == FAIL)
1797 {
1798 first_error (_(reg_expected_msgs[rtype]));
1799 return FAIL;
1800 }
1801
1802 if (base_reg == -1)
1803 {
1804 base_reg = getreg;
1805 if (rtype == REG_TYPE_NQ)
1806 {
1807 reg_incr = 1;
1808 addregs = 2;
1809 }
1810 firsttype = atype;
1811 }
1812 else if (reg_incr == -1)
1813 {
1814 reg_incr = getreg - base_reg;
1815 if (reg_incr < 1 || reg_incr > 2)
1816 {
1817 first_error (_(incr_error));
1818 return FAIL;
1819 }
1820 }
1821 else if (getreg != base_reg + reg_incr * count)
1822 {
1823 first_error (_(incr_error));
1824 return FAIL;
1825 }
1826
1827 if (!neon_alias_types_same (&atype, &firsttype))
1828 {
1829 first_error (_(type_error));
1830 return FAIL;
1831 }
1832
1833 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1834 modes. */
1835 if (ptr[0] == '-')
1836 {
1837 struct neon_typed_alias htype;
1838 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1839 if (lane == -1)
1840 lane = NEON_INTERLEAVE_LANES;
1841 else if (lane != NEON_INTERLEAVE_LANES)
1842 {
1843 first_error (_(type_error));
1844 return FAIL;
1845 }
1846 if (reg_incr == -1)
1847 reg_incr = 1;
1848 else if (reg_incr != 1)
1849 {
1850 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1851 return FAIL;
1852 }
1853 ptr++;
1854 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
1855 if (hireg == FAIL)
1856 {
1857 first_error (_(reg_expected_msgs[rtype]));
1858 return FAIL;
1859 }
1860 if (!neon_alias_types_same (&htype, &firsttype))
1861 {
1862 first_error (_(type_error));
1863 return FAIL;
1864 }
1865 count += hireg + dregs - getreg;
1866 continue;
1867 }
1868
1869 /* If we're using Q registers, we can't use [] or [n] syntax. */
1870 if (rtype == REG_TYPE_NQ)
1871 {
1872 count += 2;
1873 continue;
1874 }
1875
1876 if ((atype.defined & NTA_HASINDEX) != 0)
1877 {
1878 if (lane == -1)
1879 lane = atype.index;
1880 else if (lane != atype.index)
1881 {
1882 first_error (_(type_error));
1883 return FAIL;
1884 }
1885 }
1886 else if (lane == -1)
1887 lane = NEON_INTERLEAVE_LANES;
1888 else if (lane != NEON_INTERLEAVE_LANES)
1889 {
1890 first_error (_(type_error));
1891 return FAIL;
1892 }
1893 count++;
1894 }
1895 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
1896
1897 /* No lane set by [x]. We must be interleaving structures. */
1898 if (lane == -1)
1899 lane = NEON_INTERLEAVE_LANES;
1900
1901 /* Sanity check. */
1902 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
1903 || (count > 1 && reg_incr == -1))
1904 {
1905 first_error (_("error parsing element/structure list"));
1906 return FAIL;
1907 }
1908
1909 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
1910 {
1911 first_error (_("expected }"));
1912 return FAIL;
1913 }
1914
1915 if (reg_incr == -1)
1916 reg_incr = 1;
1917
1918 if (eltype)
1919 *eltype = firsttype.eltype;
1920
1921 *pbase = base_reg;
1922 *str = ptr;
1923
1924 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
1925}
1926
1927/* Parse an explicit relocation suffix on an expression. This is
1928 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1929 arm_reloc_hsh contains no entries, so this function can only
1930 succeed if there is no () after the word. Returns -1 on error,
1931 BFD_RELOC_UNUSED if there wasn't any suffix. */
1932static int
1933parse_reloc (char **str)
1934{
1935 struct reloc_entry *r;
1936 char *p, *q;
1937
1938 if (**str != '(')
1939 return BFD_RELOC_UNUSED;
1940
1941 p = *str + 1;
1942 q = p;
1943
1944 while (*q && *q != ')' && *q != ',')
1945 q++;
1946 if (*q != ')')
1947 return -1;
1948
1949 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
1950 return -1;
1951
1952 *str = q + 1;
1953 return r->reloc;
1954}
1955
1956/* Directives: register aliases. */
1957
1958static struct reg_entry *
1959insert_reg_alias (char *str, int number, int type)
1960{
1961 struct reg_entry *new;
1962 const char *name;
1963
1964 if ((new = hash_find (arm_reg_hsh, str)) != 0)
1965 {
1966 if (new->builtin)
1967 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
1968
1969 /* Only warn about a redefinition if it's not defined as the
1970 same register. */
1971 else if (new->number != number || new->type != type)
1972 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1973
1974 return 0;
1975 }
1976
1977 name = xstrdup (str);
1978 new = xmalloc (sizeof (struct reg_entry));
1979
1980 new->name = name;
1981 new->number = number;
1982 new->type = type;
1983 new->builtin = FALSE;
1984 new->neon = NULL;
1985
1986 if (hash_insert (arm_reg_hsh, name, (PTR) new))
1987 abort ();
1988
1989 return new;
1990}
1991
1992static void
1993insert_neon_reg_alias (char *str, int number, int type,
1994 struct neon_typed_alias *atype)
1995{
1996 struct reg_entry *reg = insert_reg_alias (str, number, type);
1997
1998 if (!reg)
1999 {
2000 first_error (_("attempt to redefine typed alias"));
2001 return;
2002 }
2003
2004 if (atype)
2005 {
2006 reg->neon = xmalloc (sizeof (struct neon_typed_alias));
2007 *reg->neon = *atype;
2008 }
2009}
2010
2011/* Look for the .req directive. This is of the form:
2012
2013 new_register_name .req existing_register_name
2014
2015 If we find one, or if it looks sufficiently like one that we want to
2016 handle any error here, return non-zero. Otherwise return zero. */
2017
2018static int
2019create_register_alias (char * newname, char *p)
2020{
2021 struct reg_entry *old;
2022 char *oldname, *nbuf;
2023 size_t nlen;
2024
2025 /* The input scrubber ensures that whitespace after the mnemonic is
2026 collapsed to single spaces. */
2027 oldname = p;
2028 if (strncmp (oldname, " .req ", 6) != 0)
2029 return 0;
2030
2031 oldname += 6;
2032 if (*oldname == '\0')
2033 return 0;
2034
2035 old = hash_find (arm_reg_hsh, oldname);
2036 if (!old)
2037 {
2038 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2039 return 1;
2040 }
2041
2042 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2043 the desired alias name, and p points to its end. If not, then
2044 the desired alias name is in the global original_case_string. */
2045#ifdef TC_CASE_SENSITIVE
2046 nlen = p - newname;
2047#else
2048 newname = original_case_string;
2049 nlen = strlen (newname);
2050#endif
2051
2052 nbuf = alloca (nlen + 1);
2053 memcpy (nbuf, newname, nlen);
2054 nbuf[nlen] = '\0';
2055
2056 /* Create aliases under the new name as stated; an all-lowercase
2057 version of the new name; and an all-uppercase version of the new
2058 name. */
2059 insert_reg_alias (nbuf, old->number, old->type);
2060
2061 for (p = nbuf; *p; p++)
2062 *p = TOUPPER (*p);
2063
2064 if (strncmp (nbuf, newname, nlen))
2065 insert_reg_alias (nbuf, old->number, old->type);
2066
2067 for (p = nbuf; *p; p++)
2068 *p = TOLOWER (*p);
2069
2070 if (strncmp (nbuf, newname, nlen))
2071 insert_reg_alias (nbuf, old->number, old->type);
2072
2073 return 1;
2074}
2075
2076/* Create a Neon typed/indexed register alias using directives, e.g.:
2077 X .dn d5.s32[1]
2078 Y .qn 6.s16
2079 Z .dn d7
2080 T .dn Z[0]
2081 These typed registers can be used instead of the types specified after the
2082 Neon mnemonic, so long as all operands given have types. Types can also be
2083 specified directly, e.g.:
2084 vadd d0.s32, d1.s32, d2.s32
2085*/
2086
2087static int
2088create_neon_reg_alias (char *newname, char *p)
2089{
2090 enum arm_reg_type basetype;
2091 struct reg_entry *basereg;
2092 struct reg_entry mybasereg;
2093 struct neon_type ntype;
2094 struct neon_typed_alias typeinfo;
2095 char *namebuf, *nameend;
2096 int namelen;
2097
2098 typeinfo.defined = 0;
2099 typeinfo.eltype.type = NT_invtype;
2100 typeinfo.eltype.size = -1;
2101 typeinfo.index = -1;
2102
2103 nameend = p;
2104
2105 if (strncmp (p, " .dn ", 5) == 0)
2106 basetype = REG_TYPE_VFD;
2107 else if (strncmp (p, " .qn ", 5) == 0)
2108 basetype = REG_TYPE_NQ;
2109 else
2110 return 0;
2111
2112 p += 5;
2113
2114 if (*p == '\0')
2115 return 0;
2116
2117 basereg = arm_reg_parse_multi (&p);
2118
2119 if (basereg && basereg->type != basetype)
2120 {
2121 as_bad (_("bad type for register"));
2122 return 0;
2123 }
2124
2125 if (basereg == NULL)
2126 {
2127 expressionS exp;
2128 /* Try parsing as an integer. */
2129 my_get_expression (&exp, &p, GE_NO_PREFIX);
2130 if (exp.X_op != O_constant)
2131 {
2132 as_bad (_("expression must be constant"));
2133 return 0;
2134 }
2135 basereg = &mybasereg;
2136 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2137 : exp.X_add_number;
2138 basereg->neon = 0;
2139 }
2140
2141 if (basereg->neon)
2142 typeinfo = *basereg->neon;
2143
2144 if (parse_neon_type (&ntype, &p) == SUCCESS)
2145 {
2146 /* We got a type. */
2147 if (typeinfo.defined & NTA_HASTYPE)
2148 {
2149 as_bad (_("can't redefine the type of a register alias"));
2150 return 0;
2151 }
2152
2153 typeinfo.defined |= NTA_HASTYPE;
2154 if (ntype.elems != 1)
2155 {
2156 as_bad (_("you must specify a single type only"));
2157 return 0;
2158 }
2159 typeinfo.eltype = ntype.el[0];
2160 }
2161
2162 if (skip_past_char (&p, '[') == SUCCESS)
2163 {
2164 expressionS exp;
2165 /* We got a scalar index. */
2166
2167 if (typeinfo.defined & NTA_HASINDEX)
2168 {
2169 as_bad (_("can't redefine the index of a scalar alias"));
2170 return 0;
2171 }
2172
2173 my_get_expression (&exp, &p, GE_NO_PREFIX);
2174
2175 if (exp.X_op != O_constant)
2176 {
2177 as_bad (_("scalar index must be constant"));
2178 return 0;
2179 }
2180
2181 typeinfo.defined |= NTA_HASINDEX;
2182 typeinfo.index = exp.X_add_number;
2183
2184 if (skip_past_char (&p, ']') == FAIL)
2185 {
2186 as_bad (_("expecting ]"));
2187 return 0;
2188 }
2189 }
2190
2191 namelen = nameend - newname;
2192 namebuf = alloca (namelen + 1);
2193 strncpy (namebuf, newname, namelen);
2194 namebuf[namelen] = '\0';
2195
2196 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2197 typeinfo.defined != 0 ? &typeinfo : NULL);
2198
2199 /* Insert name in all uppercase. */
2200 for (p = namebuf; *p; p++)
2201 *p = TOUPPER (*p);
2202
2203 if (strncmp (namebuf, newname, namelen))
2204 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2205 typeinfo.defined != 0 ? &typeinfo : NULL);
2206
2207 /* Insert name in all lowercase. */
2208 for (p = namebuf; *p; p++)
2209 *p = TOLOWER (*p);
2210
2211 if (strncmp (namebuf, newname, namelen))
2212 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2213 typeinfo.defined != 0 ? &typeinfo : NULL);
2214
2215 return 1;
2216}
2217
2218/* Should never be called, as .req goes between the alias and the
2219 register name, not at the beginning of the line. */
2220static void
2221s_req (int a ATTRIBUTE_UNUSED)
2222{
2223 as_bad (_("invalid syntax for .req directive"));
2224}
2225
2226static void
2227s_dn (int a ATTRIBUTE_UNUSED)
2228{
2229 as_bad (_("invalid syntax for .dn directive"));
2230}
2231
2232static void
2233s_qn (int a ATTRIBUTE_UNUSED)
2234{
2235 as_bad (_("invalid syntax for .qn directive"));
2236}
2237
2238/* The .unreq directive deletes an alias which was previously defined
2239 by .req. For example:
2240
2241 my_alias .req r11
2242 .unreq my_alias */
2243
2244static void
2245s_unreq (int a ATTRIBUTE_UNUSED)
2246{
2247 char * name;
2248 char saved_char;
2249
2250 name = input_line_pointer;
2251
2252 while (*input_line_pointer != 0
2253 && *input_line_pointer != ' '
2254 && *input_line_pointer != '\n')
2255 ++input_line_pointer;
2256
2257 saved_char = *input_line_pointer;
2258 *input_line_pointer = 0;
2259
2260 if (!*name)
2261 as_bad (_("invalid syntax for .unreq directive"));
2262 else
2263 {
2264 struct reg_entry *reg = hash_find (arm_reg_hsh, name);
2265
2266 if (!reg)
2267 as_bad (_("unknown register alias '%s'"), name);
2268 else if (reg->builtin)
2269 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2270 name);
2271 else
2272 {
2273 hash_delete (arm_reg_hsh, name);
2274 free ((char *) reg->name);
2275 if (reg->neon)
2276 free (reg->neon);
2277 free (reg);
2278 }
2279 }
2280
2281 *input_line_pointer = saved_char;
2282 demand_empty_rest_of_line ();
2283}
2284
2285/* Directives: Instruction set selection. */
2286
2287#ifdef OBJ_ELF
2288/* This code is to handle mapping symbols as defined in the ARM ELF spec.
2289 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2290 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2291 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2292
2293static enum mstate mapstate = MAP_UNDEFINED;
2294
2295void
2296mapping_state (enum mstate state)
2297{
2298 symbolS * symbolP;
2299 const char * symname;
2300 int type;
2301
2302 if (mapstate == state)
2303 /* The mapping symbol has already been emitted.
2304 There is nothing else to do. */
2305 return;
2306
2307 mapstate = state;
2308
2309 switch (state)
2310 {
2311 case MAP_DATA:
2312 symname = "$d";
2313 type = BSF_NO_FLAGS;
2314 break;
2315 case MAP_ARM:
2316 symname = "$a";
2317 type = BSF_NO_FLAGS;
2318 break;
2319 case MAP_THUMB:
2320 symname = "$t";
2321 type = BSF_NO_FLAGS;
2322 break;
2323 case MAP_UNDEFINED:
2324 return;
2325 default:
2326 abort ();
2327 }
2328
2329 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2330
2331 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
2332 symbol_table_insert (symbolP);
2333 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2334
2335 switch (state)
2336 {
2337 case MAP_ARM:
2338 THUMB_SET_FUNC (symbolP, 0);
2339 ARM_SET_THUMB (symbolP, 0);
2340 ARM_SET_INTERWORK (symbolP, support_interwork);
2341 break;
2342
2343 case MAP_THUMB:
2344 THUMB_SET_FUNC (symbolP, 1);
2345 ARM_SET_THUMB (symbolP, 1);
2346 ARM_SET_INTERWORK (symbolP, support_interwork);
2347 break;
2348
2349 case MAP_DATA:
2350 default:
2351 return;
2352 }
2353}
2354#else
2355#define mapping_state(x) /* nothing */
2356#endif
2357
2358/* Find the real, Thumb encoded start of a Thumb function. */
2359
2360static symbolS *
2361find_real_start (symbolS * symbolP)
2362{
2363 char * real_start;
2364 const char * name = S_GET_NAME (symbolP);
2365 symbolS * new_target;
2366
2367 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2368#define STUB_NAME ".real_start_of"
2369
2370 if (name == NULL)
2371 abort ();
2372
2373 /* The compiler may generate BL instructions to local labels because
2374 it needs to perform a branch to a far away location. These labels
2375 do not have a corresponding ".real_start_of" label. We check
2376 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2377 the ".real_start_of" convention for nonlocal branches. */
2378 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2379 return symbolP;
2380
2381 real_start = ACONCAT ((STUB_NAME, name, NULL));
2382 new_target = symbol_find (real_start);
2383
2384 if (new_target == NULL)
2385 {
2386 as_warn ("Failed to find real start of function: %s\n", name);
2387 new_target = symbolP;
2388 }
2389
2390 return new_target;
2391}
2392
2393static void
2394opcode_select (int width)
2395{
2396 switch (width)
2397 {
2398 case 16:
2399 if (! thumb_mode)
2400 {
2401 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2402 as_bad (_("selected processor does not support THUMB opcodes"));
2403
2404 thumb_mode = 1;
2405 /* No need to force the alignment, since we will have been
2406 coming from ARM mode, which is word-aligned. */
2407 record_alignment (now_seg, 1);
2408 }
2409 mapping_state (MAP_THUMB);
2410 break;
2411
2412 case 32:
2413 if (thumb_mode)
2414 {
2415 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2416 as_bad (_("selected processor does not support ARM opcodes"));
2417
2418 thumb_mode = 0;
2419
2420 if (!need_pass_2)
2421 frag_align (2, 0, 0);
2422
2423 record_alignment (now_seg, 1);
2424 }
2425 mapping_state (MAP_ARM);
2426 break;
2427
2428 default:
2429 as_bad (_("invalid instruction size selected (%d)"), width);
2430 }
2431}
2432
2433static void
2434s_arm (int ignore ATTRIBUTE_UNUSED)
2435{
2436 opcode_select (32);
2437 demand_empty_rest_of_line ();
2438}
2439
2440static void
2441s_thumb (int ignore ATTRIBUTE_UNUSED)
2442{
2443 opcode_select (16);
2444 demand_empty_rest_of_line ();
2445}
2446
2447static void
2448s_code (int unused ATTRIBUTE_UNUSED)
2449{
2450 int temp;
2451
2452 temp = get_absolute_expression ();
2453 switch (temp)
2454 {
2455 case 16:
2456 case 32:
2457 opcode_select (temp);
2458 break;
2459
2460 default:
2461 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2462 }
2463}
2464
2465static void
2466s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2467{
2468 /* If we are not already in thumb mode go into it, EVEN if
2469 the target processor does not support thumb instructions.
2470 This is used by gcc/config/arm/lib1funcs.asm for example
2471 to compile interworking support functions even if the
2472 target processor should not support interworking. */
2473 if (! thumb_mode)
2474 {
2475 thumb_mode = 2;
2476 record_alignment (now_seg, 1);
2477 }
2478
2479 demand_empty_rest_of_line ();
2480}
2481
2482static void
2483s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2484{
2485 s_thumb (0);
2486
2487 /* The following label is the name/address of the start of a Thumb function.
2488 We need to know this for the interworking support. */
2489 label_is_thumb_function_name = TRUE;
2490}
2491
2492/* Perform a .set directive, but also mark the alias as
2493 being a thumb function. */
2494
2495static void
2496s_thumb_set (int equiv)
2497{
2498 /* XXX the following is a duplicate of the code for s_set() in read.c
2499 We cannot just call that code as we need to get at the symbol that
2500 is created. */
2501 char * name;
2502 char delim;
2503 char * end_name;
2504 symbolS * symbolP;
2505
2506 /* Especial apologies for the random logic:
2507 This just grew, and could be parsed much more simply!
2508 Dean - in haste. */
2509 name = input_line_pointer;
2510 delim = get_symbol_end ();
2511 end_name = input_line_pointer;
2512 *end_name = delim;
2513
2514 if (*input_line_pointer != ',')
2515 {
2516 *end_name = 0;
2517 as_bad (_("expected comma after name \"%s\""), name);
2518 *end_name = delim;
2519 ignore_rest_of_line ();
2520 return;
2521 }
2522
2523 input_line_pointer++;
2524 *end_name = 0;
2525
2526 if (name[0] == '.' && name[1] == '\0')
2527 {
2528 /* XXX - this should not happen to .thumb_set. */
2529 abort ();
2530 }
2531
2532 if ((symbolP = symbol_find (name)) == NULL
2533 && (symbolP = md_undefined_symbol (name)) == NULL)
2534 {
2535#ifndef NO_LISTING
2536 /* When doing symbol listings, play games with dummy fragments living
2537 outside the normal fragment chain to record the file and line info
2538 for this symbol. */
2539 if (listing & LISTING_SYMBOLS)
2540 {
2541 extern struct list_info_struct * listing_tail;
2542 fragS * dummy_frag = xmalloc (sizeof (fragS));
2543
2544 memset (dummy_frag, 0, sizeof (fragS));
2545 dummy_frag->fr_type = rs_fill;
2546 dummy_frag->line = listing_tail;
2547 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2548 dummy_frag->fr_symbol = symbolP;
2549 }
2550 else
2551#endif
2552 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2553
2554#ifdef OBJ_COFF
2555 /* "set" symbols are local unless otherwise specified. */
2556 SF_SET_LOCAL (symbolP);
2557#endif /* OBJ_COFF */
2558 } /* Make a new symbol. */
2559
2560 symbol_table_insert (symbolP);
2561
2562 * end_name = delim;
2563
2564 if (equiv
2565 && S_IS_DEFINED (symbolP)
2566 && S_GET_SEGMENT (symbolP) != reg_section)
2567 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2568
2569 pseudo_set (symbolP);
2570
2571 demand_empty_rest_of_line ();
2572
2573 /* XXX Now we come to the Thumb specific bit of code. */
2574
2575 THUMB_SET_FUNC (symbolP, 1);
2576 ARM_SET_THUMB (symbolP, 1);
2577#if defined OBJ_ELF || defined OBJ_COFF
2578 ARM_SET_INTERWORK (symbolP, support_interwork);
2579#endif
2580}
2581
2582/* Directives: Mode selection. */
2583
2584/* .syntax [unified|divided] - choose the new unified syntax
2585 (same for Arm and Thumb encoding, modulo slight differences in what
2586 can be represented) or the old divergent syntax for each mode. */
2587static void
2588s_syntax (int unused ATTRIBUTE_UNUSED)
2589{
2590 char *name, delim;
2591
2592 name = input_line_pointer;
2593 delim = get_symbol_end ();
2594
2595 if (!strcasecmp (name, "unified"))
2596 unified_syntax = TRUE;
2597 else if (!strcasecmp (name, "divided"))
2598 unified_syntax = FALSE;
2599 else
2600 {
2601 as_bad (_("unrecognized syntax mode \"%s\""), name);
2602 return;
2603 }
2604 *input_line_pointer = delim;
2605 demand_empty_rest_of_line ();
2606}
2607
2608/* Directives: sectioning and alignment. */
2609
2610/* Same as s_align_ptwo but align 0 => align 2. */
2611
2612static void
2613s_align (int unused ATTRIBUTE_UNUSED)
2614{
2615 int temp;
2616 bfd_boolean fill_p;
2617 long temp_fill;
2618 long max_alignment = 15;
2619
2620 temp = get_absolute_expression ();
2621 if (temp > max_alignment)
2622 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2623 else if (temp < 0)
2624 {
2625 as_bad (_("alignment negative. 0 assumed."));
2626 temp = 0;
2627 }
2628
2629 if (*input_line_pointer == ',')
2630 {
2631 input_line_pointer++;
2632 temp_fill = get_absolute_expression ();
2633 fill_p = TRUE;
2634 }
2635 else
2636 {
2637 fill_p = FALSE;
2638 temp_fill = 0;
2639 }
2640
2641 if (!temp)
2642 temp = 2;
2643
2644 /* Only make a frag if we HAVE to. */
2645 if (temp && !need_pass_2)
2646 {
2647 if (!fill_p && subseg_text_p (now_seg))
2648 frag_align_code (temp, 0);
2649 else
2650 frag_align (temp, (int) temp_fill, 0);
2651 }
2652 demand_empty_rest_of_line ();
2653
2654 record_alignment (now_seg, temp);
2655}
2656
2657static void
2658s_bss (int ignore ATTRIBUTE_UNUSED)
2659{
2660 /* We don't support putting frags in the BSS segment, we fake it by
2661 marking in_bss, then looking at s_skip for clues. */
2662 subseg_set (bss_section, 0);
2663 demand_empty_rest_of_line ();
2664 mapping_state (MAP_DATA);
2665}
2666
2667static void
2668s_even (int ignore ATTRIBUTE_UNUSED)
2669{
2670 /* Never make frag if expect extra pass. */
2671 if (!need_pass_2)
2672 frag_align (1, 0, 0);
2673
2674 record_alignment (now_seg, 1);
2675
2676 demand_empty_rest_of_line ();
2677}
2678
2679/* Directives: Literal pools. */
2680
2681static literal_pool *
2682find_literal_pool (void)
2683{
2684 literal_pool * pool;
2685
2686 for (pool = list_of_pools; pool != NULL; pool = pool->next)
2687 {
2688 if (pool->section == now_seg
2689 && pool->sub_section == now_subseg)
2690 break;
2691 }
2692
2693 return pool;
2694}
2695
2696static literal_pool *
2697find_or_make_literal_pool (void)
2698{
2699 /* Next literal pool ID number. */
2700 static unsigned int latest_pool_num = 1;
2701 literal_pool * pool;
2702
2703 pool = find_literal_pool ();
2704
2705 if (pool == NULL)
2706 {
2707 /* Create a new pool. */
2708 pool = xmalloc (sizeof (* pool));
2709 if (! pool)
2710 return NULL;
2711
2712 pool->next_free_entry = 0;
2713 pool->section = now_seg;
2714 pool->sub_section = now_subseg;
2715 pool->next = list_of_pools;
2716 pool->symbol = NULL;
2717
2718 /* Add it to the list. */
2719 list_of_pools = pool;
2720 }
2721
2722 /* New pools, and emptied pools, will have a NULL symbol. */
2723 if (pool->symbol == NULL)
2724 {
2725 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
2726 (valueT) 0, &zero_address_frag);
2727 pool->id = latest_pool_num ++;
2728 }
2729
2730 /* Done. */
2731 return pool;
2732}
2733
2734/* Add the literal in the global 'inst'
2735 structure to the relevent literal pool. */
2736
2737static int
2738add_to_lit_pool (void)
2739{
2740 literal_pool * pool;
2741 unsigned int entry;
2742
2743 pool = find_or_make_literal_pool ();
2744
2745 /* Check if this literal value is already in the pool. */
2746 for (entry = 0; entry < pool->next_free_entry; entry ++)
2747 {
2748 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
2749 && (inst.reloc.exp.X_op == O_constant)
2750 && (pool->literals[entry].X_add_number
2751 == inst.reloc.exp.X_add_number)
2752 && (pool->literals[entry].X_unsigned
2753 == inst.reloc.exp.X_unsigned))
2754 break;
2755
2756 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
2757 && (inst.reloc.exp.X_op == O_symbol)
2758 && (pool->literals[entry].X_add_number
2759 == inst.reloc.exp.X_add_number)
2760 && (pool->literals[entry].X_add_symbol
2761 == inst.reloc.exp.X_add_symbol)
2762 && (pool->literals[entry].X_op_symbol
2763 == inst.reloc.exp.X_op_symbol))
2764 break;
2765 }
2766
2767 /* Do we need to create a new entry? */
2768 if (entry == pool->next_free_entry)
2769 {
2770 if (entry >= MAX_LITERAL_POOL_SIZE)
2771 {
2772 inst.error = _("literal pool overflow");
2773 return FAIL;
2774 }
2775
2776 pool->literals[entry] = inst.reloc.exp;
2777 pool->next_free_entry += 1;
2778 }
2779
2780 inst.reloc.exp.X_op = O_symbol;
2781 inst.reloc.exp.X_add_number = ((int) entry) * 4;
2782 inst.reloc.exp.X_add_symbol = pool->symbol;
2783
2784 return SUCCESS;
2785}
2786
2787/* Can't use symbol_new here, so have to create a symbol and then at
2788 a later date assign it a value. Thats what these functions do. */
2789
2790static void
2791symbol_locate (symbolS * symbolP,
2792 const char * name, /* It is copied, the caller can modify. */
2793 segT segment, /* Segment identifier (SEG_<something>). */
2794 valueT valu, /* Symbol value. */
2795 fragS * frag) /* Associated fragment. */
2796{
2797 unsigned int name_length;
2798 char * preserved_copy_of_name;
2799
2800 name_length = strlen (name) + 1; /* +1 for \0. */
2801 obstack_grow (¬es, name, name_length);
2802 preserved_copy_of_name = obstack_finish (¬es);
2803
2804#ifdef tc_canonicalize_symbol_name
2805 preserved_copy_of_name =
2806 tc_canonicalize_symbol_name (preserved_copy_of_name);
2807#endif
2808
2809 S_SET_NAME (symbolP, preserved_copy_of_name);
2810
2811 S_SET_SEGMENT (symbolP, segment);
2812 S_SET_VALUE (symbolP, valu);
2813 symbol_clear_list_pointers (symbolP);
2814
2815 symbol_set_frag (symbolP, frag);
2816
2817 /* Link to end of symbol chain. */
2818 {
2819 extern int symbol_table_frozen;
2820
2821 if (symbol_table_frozen)
2822 abort ();
2823 }
2824
2825 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
2826
2827 obj_symbol_new_hook (symbolP);
2828
2829#ifdef tc_symbol_new_hook
2830 tc_symbol_new_hook (symbolP);
2831#endif
2832
2833#ifdef DEBUG_SYMS
2834 verify_symbol_chain (symbol_rootP, symbol_lastP);
2835#endif /* DEBUG_SYMS */
2836}
2837
2838
2839static void
2840s_ltorg (int ignored ATTRIBUTE_UNUSED)
2841{
2842 unsigned int entry;
2843 literal_pool * pool;
2844 char sym_name[20];
2845
2846 pool = find_literal_pool ();
2847 if (pool == NULL
2848 || pool->symbol == NULL
2849 || pool->next_free_entry == 0)
2850 return;
2851
2852 mapping_state (MAP_DATA);
2853
2854 /* Align pool as you have word accesses.
2855 Only make a frag if we have to. */
2856 if (!need_pass_2)
2857 frag_align (2, 0, 0);
2858
2859 record_alignment (now_seg, 2);
2860
2861 sprintf (sym_name, "$$lit_\002%x", pool->id);
2862
2863 symbol_locate (pool->symbol, sym_name, now_seg,
2864 (valueT) frag_now_fix (), frag_now);
2865 symbol_table_insert (pool->symbol);
2866
2867 ARM_SET_THUMB (pool->symbol, thumb_mode);
2868
2869#if defined OBJ_COFF || defined OBJ_ELF
2870 ARM_SET_INTERWORK (pool->symbol, support_interwork);
2871#endif
2872
2873 for (entry = 0; entry < pool->next_free_entry; entry ++)
2874 /* First output the expression in the instruction to the pool. */
2875 emit_expr (&(pool->literals[entry]), 4); /* .word */
2876
2877 /* Mark the pool as empty. */
2878 pool->next_free_entry = 0;
2879 pool->symbol = NULL;
2880}
2881
2882#ifdef OBJ_ELF
2883/* Forward declarations for functions below, in the MD interface
2884 section. */
2885static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
2886static valueT create_unwind_entry (int);
2887static void start_unwind_section (const segT, int);
2888static void add_unwind_opcode (valueT, int);
2889static void flush_pending_unwind (void);
2890
2891/* Directives: Data. */
2892
2893static void
2894s_arm_elf_cons (int nbytes)
2895{
2896 expressionS exp;
2897
2898#ifdef md_flush_pending_output
2899 md_flush_pending_output ();
2900#endif
2901
2902 if (is_it_end_of_statement ())
2903 {
2904 demand_empty_rest_of_line ();
2905 return;
2906 }
2907
2908#ifdef md_cons_align
2909 md_cons_align (nbytes);
2910#endif
2911
2912 mapping_state (MAP_DATA);
2913 do
2914 {
2915 int reloc;
2916 char *base = input_line_pointer;
2917
2918 expression (& exp);
2919
2920 if (exp.X_op != O_symbol)
2921 emit_expr (&exp, (unsigned int) nbytes);
2922 else
2923 {
2924 char *before_reloc = input_line_pointer;
2925 reloc = parse_reloc (&input_line_pointer);
2926 if (reloc == -1)
2927 {
2928 as_bad (_("unrecognized relocation suffix"));
2929 ignore_rest_of_line ();
2930 return;
2931 }
2932 else if (reloc == BFD_RELOC_UNUSED)
2933 emit_expr (&exp, (unsigned int) nbytes);
2934 else
2935 {
2936 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
2937 int size = bfd_get_reloc_size (howto);
2938
2939 if (reloc == BFD_RELOC_ARM_PLT32)
2940 {
2941 as_bad (_("(plt) is only valid on branch targets"));
2942 reloc = BFD_RELOC_UNUSED;
2943 size = 0;
2944 }
2945
2946 if (size > nbytes)
2947 as_bad (_("%s relocations do not fit in %d bytes"),
2948 howto->name, nbytes);
2949 else
2950 {
2951 /* We've parsed an expression stopping at O_symbol.
2952 But there may be more expression left now that we
2953 have parsed the relocation marker. Parse it again.
2954 XXX Surely there is a cleaner way to do this. */
2955 char *p = input_line_pointer;
2956 int offset;
2957 char *save_buf = alloca (input_line_pointer - base);
2958 memcpy (save_buf, base, input_line_pointer - base);
2959 memmove (base + (input_line_pointer - before_reloc),
2960 base, before_reloc - base);
2961
2962 input_line_pointer = base + (input_line_pointer-before_reloc);
2963 expression (&exp);
2964 memcpy (base, save_buf, p - base);
2965
2966 offset = nbytes - size;
2967 p = frag_more ((int) nbytes);
2968 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
2969 size, &exp, 0, reloc);
2970 }
2971 }
2972 }
2973 }
2974 while (*input_line_pointer++ == ',');
2975
2976 /* Put terminator back into stream. */
2977 input_line_pointer --;
2978 demand_empty_rest_of_line ();
2979}
2980
2981
2982/* Parse a .rel31 directive. */
2983
2984static void
2985s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
2986{
2987 expressionS exp;
2988 char *p;
2989 valueT highbit;
2990
2991 highbit = 0;
2992 if (*input_line_pointer == '1')
2993 highbit = 0x80000000;
2994 else if (*input_line_pointer != '0')
2995 as_bad (_("expected 0 or 1"));
2996
2997 input_line_pointer++;
2998 if (*input_line_pointer != ',')
2999 as_bad (_("missing comma"));
3000 input_line_pointer++;
3001
3002#ifdef md_flush_pending_output
3003 md_flush_pending_output ();
3004#endif
3005
3006#ifdef md_cons_align
3007 md_cons_align (4);
3008#endif
3009
3010 mapping_state (MAP_DATA);
3011
3012 expression (&exp);
3013
3014 p = frag_more (4);
3015 md_number_to_chars (p, highbit, 4);
3016 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3017 BFD_RELOC_ARM_PREL31);
3018
3019 demand_empty_rest_of_line ();
3020}
3021
3022/* Directives: AEABI stack-unwind tables. */
3023
3024/* Parse an unwind_fnstart directive. Simply records the current location. */
3025
3026static void
3027s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3028{
3029 demand_empty_rest_of_line ();
3030 /* Mark the start of the function. */
3031 unwind.proc_start = expr_build_dot ();
3032
3033 /* Reset the rest of the unwind info. */
3034 unwind.opcode_count = 0;
3035 unwind.table_entry = NULL;
3036 unwind.personality_routine = NULL;
3037 unwind.personality_index = -1;
3038 unwind.frame_size = 0;
3039 unwind.fp_offset = 0;
3040 unwind.fp_reg = 13;
3041 unwind.fp_used = 0;
3042 unwind.sp_restored = 0;
3043}
3044
3045
3046/* Parse a handlerdata directive. Creates the exception handling table entry
3047 for the function. */
3048
3049static void
3050s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3051{
3052 demand_empty_rest_of_line ();
3053 if (unwind.table_entry)
3054 as_bad (_("dupicate .handlerdata directive"));
3055
3056 create_unwind_entry (1);
3057}
3058
3059/* Parse an unwind_fnend directive. Generates the index table entry. */
3060
3061static void
3062s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3063{
3064 long where;
3065 char *ptr;
3066 valueT val;
3067
3068 demand_empty_rest_of_line ();
3069
3070 /* Add eh table entry. */
3071 if (unwind.table_entry == NULL)
3072 val = create_unwind_entry (0);
3073 else
3074 val = 0;
3075
3076 /* Add index table entry. This is two words. */
3077 start_unwind_section (unwind.saved_seg, 1);
3078 frag_align (2, 0, 0);
3079 record_alignment (now_seg, 2);
3080
3081 ptr = frag_more (8);
3082 where = frag_now_fix () - 8;
3083
3084 /* Self relative offset of the function start. */
3085 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3086 BFD_RELOC_ARM_PREL31);
3087
3088 /* Indicate dependency on EHABI-defined personality routines to the
3089 linker, if it hasn't been done already. */
3090 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3091 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3092 {
3093 static const char *const name[] = {
3094 "__aeabi_unwind_cpp_pr0",
3095 "__aeabi_unwind_cpp_pr1",
3096 "__aeabi_unwind_cpp_pr2"
3097 };
3098 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3099 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3100 marked_pr_dependency |= 1 << unwind.personality_index;
3101 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3102 = marked_pr_dependency;
3103 }
3104
3105 if (val)
3106 /* Inline exception table entry. */
3107 md_number_to_chars (ptr + 4, val, 4);
3108 else
3109 /* Self relative offset of the table entry. */
3110 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3111 BFD_RELOC_ARM_PREL31);
3112
3113 /* Restore the original section. */
3114 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3115}
3116
3117
3118/* Parse an unwind_cantunwind directive. */
3119
3120static void
3121s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3122{
3123 demand_empty_rest_of_line ();
3124 if (unwind.personality_routine || unwind.personality_index != -1)
3125 as_bad (_("personality routine specified for cantunwind frame"));
3126
3127 unwind.personality_index = -2;
3128}
3129
3130
3131/* Parse a personalityindex directive. */
3132
3133static void
3134s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3135{
3136 expressionS exp;
3137
3138 if (unwind.personality_routine || unwind.personality_index != -1)
3139 as_bad (_("duplicate .personalityindex directive"));
3140
3141 expression (&exp);
3142
3143 if (exp.X_op != O_constant
3144 || exp.X_add_number < 0 || exp.X_add_number > 15)
3145 {
3146 as_bad (_("bad personality routine number"));
3147 ignore_rest_of_line ();
3148 return;
3149 }
3150
3151 unwind.personality_index = exp.X_add_number;
3152
3153 demand_empty_rest_of_line ();
3154}
3155
3156
3157/* Parse a personality directive. */
3158
3159static void
3160s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3161{
3162 char *name, *p, c;
3163
3164 if (unwind.personality_routine || unwind.personality_index != -1)
3165 as_bad (_("duplicate .personality directive"));
3166
3167 name = input_line_pointer;
3168 c = get_symbol_end ();
3169 p = input_line_pointer;
3170 unwind.personality_routine = symbol_find_or_make (name);
3171 *p = c;
3172 demand_empty_rest_of_line ();
3173}
3174
3175
3176/* Parse a directive saving core registers. */
3177
3178static void
3179s_arm_unwind_save_core (void)
3180{
3181 valueT op;
3182 long range;
3183 int n;
3184
3185 range = parse_reg_list (&input_line_pointer);
3186 if (range == FAIL)
3187 {
3188 as_bad (_("expected register list"));
3189 ignore_rest_of_line ();
3190 return;
3191 }
3192
3193 demand_empty_rest_of_line ();
3194
3195 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3196 into .unwind_save {..., sp...}. We aren't bothered about the value of
3197 ip because it is clobbered by calls. */
3198 if (unwind.sp_restored && unwind.fp_reg == 12
3199 && (range & 0x3000) == 0x1000)
3200 {
3201 unwind.opcode_count--;
3202 unwind.sp_restored = 0;
3203 range = (range | 0x2000) & ~0x1000;
3204 unwind.pending_offset = 0;
3205 }
3206
3207 /* Pop r4-r15. */
3208 if (range & 0xfff0)
3209 {
3210 /* See if we can use the short opcodes. These pop a block of up to 8
3211 registers starting with r4, plus maybe r14. */
3212 for (n = 0; n < 8; n++)
3213 {
3214 /* Break at the first non-saved register. */
3215 if ((range & (1 << (n + 4))) == 0)
3216 break;
3217 }
3218 /* See if there are any other bits set. */
3219 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3220 {
3221 /* Use the long form. */
3222 op = 0x8000 | ((range >> 4) & 0xfff);
3223 add_unwind_opcode (op, 2);
3224 }
3225 else
3226 {
3227 /* Use the short form. */
3228 if (range & 0x4000)
3229 op = 0xa8; /* Pop r14. */
3230 else
3231 op = 0xa0; /* Do not pop r14. */
3232 op |= (n - 1);
3233 add_unwind_opcode (op, 1);
3234 }
3235 }
3236
3237 /* Pop r0-r3. */
3238 if (range & 0xf)
3239 {
3240 op = 0xb100 | (range & 0xf);
3241 add_unwind_opcode (op, 2);
3242 }
3243
3244 /* Record the number of bytes pushed. */
3245 for (n = 0; n < 16; n++)
3246 {
3247 if (range & (1 << n))
3248 unwind.frame_size += 4;
3249 }
3250}
3251
3252
3253/* Parse a directive saving FPA registers. */
3254
3255static void
3256s_arm_unwind_save_fpa (int reg)
3257{
3258 expressionS exp;
3259 int num_regs;
3260 valueT op;
3261
3262 /* Get Number of registers to transfer. */
3263 if (skip_past_comma (&input_line_pointer) != FAIL)
3264 expression (&exp);
3265 else
3266 exp.X_op = O_illegal;
3267
3268 if (exp.X_op != O_constant)
3269 {
3270 as_bad (_("expected , <constant>"));
3271 ignore_rest_of_line ();
3272 return;
3273 }
3274
3275 num_regs = exp.X_add_number;
3276
3277 if (num_regs < 1 || num_regs > 4)
3278 {
3279 as_bad (_("number of registers must be in the range [1:4]"));
3280 ignore_rest_of_line ();
3281 return;
3282 }
3283
3284 demand_empty_rest_of_line ();
3285
3286 if (reg == 4)
3287 {
3288 /* Short form. */
3289 op = 0xb4 | (num_regs - 1);
3290 add_unwind_opcode (op, 1);
3291 }
3292 else
3293 {
3294 /* Long form. */
3295 op = 0xc800 | (reg << 4) | (num_regs - 1);
3296 add_unwind_opcode (op, 2);
3297 }
3298 unwind.frame_size += num_regs * 12;
3299}
3300
3301
3302/* Parse a directive saving VFP registers for ARMv6 and above. */
3303
3304static void
3305s_arm_unwind_save_vfp_armv6 (void)
3306{
3307 int count;
3308 unsigned int start;
3309 valueT op;
3310 int num_vfpv3_regs = 0;
3311 int num_regs_below_16;
3312
3313 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3314 if (count == FAIL)
3315 {
3316 as_bad (_("expected register list"));
3317 ignore_rest_of_line ();
3318 return;
3319 }
3320
3321 demand_empty_rest_of_line ();
3322
3323 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3324 than FSTMX/FLDMX-style ones). */
3325
3326 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3327 if (start >= 16)
3328 num_vfpv3_regs = count;
3329 else if (start + count > 16)
3330 num_vfpv3_regs = start + count - 16;
3331
3332 if (num_vfpv3_regs > 0)
3333 {
3334 int start_offset = start > 16 ? start - 16 : 0;
3335 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3336 add_unwind_opcode (op, 2);
3337 }
3338
3339 /* Generate opcode for registers numbered in the range 0 .. 15. */
3340 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3341 assert (num_regs_below_16 + num_vfpv3_regs == count);
3342 if (num_regs_below_16 > 0)
3343 {
3344 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3345 add_unwind_opcode (op, 2);
3346 }
3347
3348 unwind.frame_size += count * 8;
3349}
3350
3351
3352/* Parse a directive saving VFP registers for pre-ARMv6. */
3353
3354static void
3355s_arm_unwind_save_vfp (void)
3356{
3357 int count;
3358 unsigned int reg;
3359 valueT op;
3360
3361 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3362 if (count == FAIL)
3363 {
3364 as_bad (_("expected register list"));
3365 ignore_rest_of_line ();
3366 return;
3367 }
3368
3369 demand_empty_rest_of_line ();
3370
3371 if (reg == 8)
3372 {
3373 /* Short form. */
3374 op = 0xb8 | (count - 1);
3375 add_unwind_opcode (op, 1);
3376 }
3377 else
3378 {
3379 /* Long form. */
3380 op = 0xb300 | (reg << 4) | (count - 1);
3381 add_unwind_opcode (op, 2);
3382 }
3383 unwind.frame_size += count * 8 + 4;
3384}
3385
3386
3387/* Parse a directive saving iWMMXt data registers. */
3388
3389static void
3390s_arm_unwind_save_mmxwr (void)
3391{
3392 int reg;
3393 int hi_reg;
3394 int i;
3395 unsigned mask = 0;
3396 valueT op;
3397
3398 if (*input_line_pointer == '{')
3399 input_line_pointer++;
3400
3401 do
3402 {
3403 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3404
3405 if (reg == FAIL)
3406 {
3407 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
3408 goto error;
3409 }
3410
3411 if (mask >> reg)
3412 as_tsktsk (_("register list not in ascending order"));
3413 mask |= 1 << reg;
3414
3415 if (*input_line_pointer == '-')
3416 {
3417 input_line_pointer++;
3418 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3419 if (hi_reg == FAIL)
3420 {
3421 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
3422 goto error;
3423 }
3424 else if (reg >= hi_reg)
3425 {
3426 as_bad (_("bad register range"));
3427 goto error;
3428 }
3429 for (; reg < hi_reg; reg++)
3430 mask |= 1 << reg;
3431 }
3432 }
3433 while (skip_past_comma (&input_line_pointer) != FAIL);
3434
3435 if (*input_line_pointer == '}')
3436 input_line_pointer++;
3437
3438 demand_empty_rest_of_line ();
3439
3440 /* Generate any deferred opcodes because we're going to be looking at
3441 the list. */
3442 flush_pending_unwind ();
3443
3444 for (i = 0; i < 16; i++)
3445 {
3446 if (mask & (1 << i))
3447 unwind.frame_size += 8;
3448 }
3449
3450 /* Attempt to combine with a previous opcode. We do this because gcc
3451 likes to output separate unwind directives for a single block of
3452 registers. */
3453 if (unwind.opcode_count > 0)
3454 {
3455 i = unwind.opcodes[unwind.opcode_count - 1];
3456 if ((i & 0xf8) == 0xc0)
3457 {
3458 i &= 7;
3459 /* Only merge if the blocks are contiguous. */
3460 if (i < 6)
3461 {
3462 if ((mask & 0xfe00) == (1 << 9))
3463 {
3464 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3465 unwind.opcode_count--;
3466 }
3467 }
3468 else if (i == 6 && unwind.opcode_count >= 2)
3469 {
3470 i = unwind.opcodes[unwind.opcode_count - 2];
3471 reg = i >> 4;
3472 i &= 0xf;
3473
3474 op = 0xffff << (reg - 1);
3475 if (reg > 0
3476 && ((mask & op) == (1u << (reg - 1))))
3477 {
3478 op = (1 << (reg + i + 1)) - 1;
3479 op &= ~((1 << reg) - 1);
3480 mask |= op;
3481 unwind.opcode_count -= 2;
3482 }
3483 }
3484 }
3485 }
3486
3487 hi_reg = 15;
3488 /* We want to generate opcodes in the order the registers have been
3489 saved, ie. descending order. */
3490 for (reg = 15; reg >= -1; reg--)
3491 {
3492 /* Save registers in blocks. */
3493 if (reg < 0
3494 || !(mask & (1 << reg)))
3495 {
3496 /* We found an unsaved reg. Generate opcodes to save the
3497 preceeding block. */
3498 if (reg != hi_reg)
3499 {
3500 if (reg == 9)
3501 {
3502 /* Short form. */
3503 op = 0xc0 | (hi_reg - 10);
3504 add_unwind_opcode (op, 1);
3505 }
3506 else
3507 {
3508 /* Long form. */
3509 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3510 add_unwind_opcode (op, 2);
3511 }
3512 }
3513 hi_reg = reg - 1;
3514 }
3515 }
3516
3517 return;
3518error:
3519 ignore_rest_of_line ();
3520}
3521
3522static void
3523s_arm_unwind_save_mmxwcg (void)
3524{
3525 int reg;
3526 int hi_reg;
3527 unsigned mask = 0;
3528 valueT op;
3529
3530 if (*input_line_pointer == '{')
3531 input_line_pointer++;
3532
3533 do
3534 {
3535 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
3536
3537 if (reg == FAIL)
3538 {
3539 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
3540 goto error;
3541 }
3542
3543 reg -= 8;
3544 if (mask >> reg)
3545 as_tsktsk (_("register list not in ascending order"));
3546 mask |= 1 << reg;
3547
3548 if (*input_line_pointer == '-')
3549 {
3550 input_line_pointer++;
3551 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
3552 if (hi_reg == FAIL)
3553 {
3554 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
3555 goto error;
3556 }
3557 else if (reg >= hi_reg)
3558 {
3559 as_bad (_("bad register range"));
3560 goto error;
3561 }
3562 for (; reg < hi_reg; reg++)
3563 mask |= 1 << reg;
3564 }
3565 }
3566 while (skip_past_comma (&input_line_pointer) != FAIL);
3567
3568 if (*input_line_pointer == '}')
3569 input_line_pointer++;
3570
3571 demand_empty_rest_of_line ();
3572
3573 /* Generate any deferred opcodes because we're going to be looking at
3574 the list. */
3575 flush_pending_unwind ();
3576
3577 for (reg = 0; reg < 16; reg++)
3578 {
3579 if (mask & (1 << reg))
3580 unwind.frame_size += 4;
3581 }
3582 op = 0xc700 | mask;
3583 add_unwind_opcode (op, 2);
3584 return;
3585error:
3586 ignore_rest_of_line ();
3587}
3588
3589
3590/* Parse an unwind_save directive.
3591 If the argument is non-zero, this is a .vsave directive. */
3592
3593static void
3594s_arm_unwind_save (int arch_v6)
3595{
3596 char *peek;
3597 struct reg_entry *reg;
3598 bfd_boolean had_brace = FALSE;
3599
3600 /* Figure out what sort of save we have. */
3601 peek = input_line_pointer;
3602
3603 if (*peek == '{')
3604 {
3605 had_brace = TRUE;
3606 peek++;
3607 }
3608
3609 reg = arm_reg_parse_multi (&peek);
3610
3611 if (!reg)
3612 {
3613 as_bad (_("register expected"));
3614 ignore_rest_of_line ();
3615 return;
3616 }
3617
3618 switch (reg->type)
3619 {
3620 case REG_TYPE_FN:
3621 if (had_brace)
3622 {
3623 as_bad (_("FPA .unwind_save does not take a register list"));
3624 ignore_rest_of_line ();
3625 return;
3626 }
3627 s_arm_unwind_save_fpa (reg->number);
3628 return;
3629
3630 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
3631 case REG_TYPE_VFD:
3632 if (arch_v6)
3633 s_arm_unwind_save_vfp_armv6 ();
3634 else
3635 s_arm_unwind_save_vfp ();
3636 return;
3637 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
3638 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
3639
3640 default:
3641 as_bad (_(".unwind_save does not support this kind of register"));
3642 ignore_rest_of_line ();
3643 }
3644}
3645
3646
3647/* Parse an unwind_movsp directive. */
3648
3649static void
3650s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
3651{
3652 int reg;
3653 valueT op;
3654 int offset;
3655
3656 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
3657 if (reg == FAIL)
3658 {
3659 as_bad (_(reg_expected_msgs[REG_TYPE_RN]));
3660 ignore_rest_of_line ();
3661 return;
3662 }
3663
3664 /* Optional constant. */
3665 if (skip_past_comma (&input_line_pointer) != FAIL)
3666 {
3667 if (immediate_for_directive (&offset) == FAIL)
3668 return;
3669 }
3670 else
3671 offset = 0;
3672
3673 demand_empty_rest_of_line ();
3674
3675 if (reg == REG_SP || reg == REG_PC)
3676 {
3677 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3678 return;
3679 }
3680
3681 if (unwind.fp_reg != REG_SP)
3682 as_bad (_("unexpected .unwind_movsp directive"));
3683
3684 /* Generate opcode to restore the value. */
3685 op = 0x90 | reg;
3686 add_unwind_opcode (op, 1);
3687
3688 /* Record the information for later. */
3689 unwind.fp_reg = reg;
3690 unwind.fp_offset = unwind.frame_size - offset;
3691 unwind.sp_restored = 1;
3692}
3693
3694/* Parse an unwind_pad directive. */
3695
3696static void
3697s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
3698{
3699 int offset;
3700
3701 if (immediate_for_directive (&offset) == FAIL)
3702 return;
3703
3704 if (offset & 3)
3705 {
3706 as_bad (_("stack increment must be multiple of 4"));
3707 ignore_rest_of_line ();
3708 return;
3709 }
3710
3711 /* Don't generate any opcodes, just record the details for later. */
3712 unwind.frame_size += offset;
3713 unwind.pending_offset += offset;
3714
3715 demand_empty_rest_of_line ();
3716}
3717
3718/* Parse an unwind_setfp directive. */
3719
3720static void
3721s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
3722{
3723 int sp_reg;
3724 int fp_reg;
3725 int offset;
3726
3727 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
3728 if (skip_past_comma (&input_line_pointer) == FAIL)
3729 sp_reg = FAIL;
3730 else
3731 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
3732
3733 if (fp_reg == FAIL || sp_reg == FAIL)
3734 {
3735 as_bad (_("expected <reg>, <reg>"));
3736 ignore_rest_of_line ();
3737 return;
3738 }
3739
3740 /* Optional constant. */
3741 if (skip_past_comma (&input_line_pointer) != FAIL)
3742 {
3743 if (immediate_for_directive (&offset) == FAIL)
3744 return;
3745 }
3746 else
3747 offset = 0;
3748
3749 demand_empty_rest_of_line ();
3750
3751 if (sp_reg != 13 && sp_reg != unwind.fp_reg)
3752 {
3753 as_bad (_("register must be either sp or set by a previous"
3754 "unwind_movsp directive"));
3755 return;
3756 }
3757
3758 /* Don't generate any opcodes, just record the information for later. */
3759 unwind.fp_reg = fp_reg;
3760 unwind.fp_used = 1;
3761 if (sp_reg == 13)
3762 unwind.fp_offset = unwind.frame_size - offset;
3763 else
3764 unwind.fp_offset -= offset;
3765}
3766
3767/* Parse an unwind_raw directive. */
3768
3769static void
3770s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
3771{
3772 expressionS exp;
3773 /* This is an arbitrary limit. */
3774 unsigned char op[16];
3775 int count;
3776
3777 expression (&exp);
3778 if (exp.X_op == O_constant
3779 && skip_past_comma (&input_line_pointer) != FAIL)
3780 {
3781 unwind.frame_size += exp.X_add_number;
3782 expression (&exp);
3783 }
3784 else
3785 exp.X_op = O_illegal;
3786
3787 if (exp.X_op != O_constant)
3788 {
3789 as_bad (_("expected <offset>, <opcode>"));
3790 ignore_rest_of_line ();
3791 return;
3792 }
3793
3794 count = 0;
3795
3796 /* Parse the opcode. */
3797 for (;;)
3798 {
3799 if (count >= 16)
3800 {
3801 as_bad (_("unwind opcode too long"));
3802 ignore_rest_of_line ();
3803 }
3804 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
3805 {
3806 as_bad (_("invalid unwind opcode"));
3807 ignore_rest_of_line ();
3808 return;
3809 }
3810 op[count++] = exp.X_add_number;
3811
3812 /* Parse the next byte. */
3813 if (skip_past_comma (&input_line_pointer) == FAIL)
3814 break;
3815
3816 expression (&exp);
3817 }
3818
3819 /* Add the opcode bytes in reverse order. */
3820 while (count--)
3821 add_unwind_opcode (op[count], 1);
3822
3823 demand_empty_rest_of_line ();
3824}
3825
3826
3827/* Parse a .eabi_attribute directive. */
3828
3829static void
3830s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
3831{
3832 s_vendor_attribute (OBJ_ATTR_PROC);
3833}
3834#endif /* OBJ_ELF */
3835
3836static void s_arm_arch (int);
3837static void s_arm_object_arch (int);
3838static void s_arm_cpu (int);
3839static void s_arm_fpu (int);
3840
3841#ifdef TE_PE
3842
3843static void
3844pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
3845{
3846 expressionS exp;
3847
3848 do
3849 {
3850 expression (&exp);
3851 if (exp.X_op == O_symbol)
3852 exp.X_op = O_secrel;
3853
3854 emit_expr (&exp, 4);
3855 }
3856 while (*input_line_pointer++ == ',');
3857
3858 input_line_pointer--;
3859 demand_empty_rest_of_line ();
3860}
3861#endif /* TE_PE */
3862
3863/* This table describes all the machine specific pseudo-ops the assembler
3864 has to support. The fields are:
3865 pseudo-op name without dot
3866 function to call to execute this pseudo-op
3867 Integer arg to pass to the function. */
3868
3869const pseudo_typeS md_pseudo_table[] =
3870{
3871 /* Never called because '.req' does not start a line. */
3872 { "req", s_req, 0 },
3873 /* Following two are likewise never called. */
3874 { "dn", s_dn, 0 },
3875 { "qn", s_qn, 0 },
3876 { "unreq", s_unreq, 0 },
3877 { "bss", s_bss, 0 },
3878 { "align", s_align, 0 },
3879 { "arm", s_arm, 0 },
3880 { "thumb", s_thumb, 0 },
3881 { "code", s_code, 0 },
3882 { "force_thumb", s_force_thumb, 0 },
3883 { "thumb_func", s_thumb_func, 0 },
3884 { "thumb_set", s_thumb_set, 0 },
3885 { "even", s_even, 0 },
3886 { "ltorg", s_ltorg, 0 },
3887 { "pool", s_ltorg, 0 },
3888 { "syntax", s_syntax, 0 },
3889 { "cpu", s_arm_cpu, 0 },
3890 { "arch", s_arm_arch, 0 },
3891 { "object_arch", s_arm_object_arch, 0 },
3892 { "fpu", s_arm_fpu, 0 },
3893#ifdef OBJ_ELF
3894 { "word", s_arm_elf_cons, 4 },
3895 { "long", s_arm_elf_cons, 4 },
3896 { "rel31", s_arm_rel31, 0 },
3897 { "fnstart", s_arm_unwind_fnstart, 0 },
3898 { "fnend", s_arm_unwind_fnend, 0 },
3899 { "cantunwind", s_arm_unwind_cantunwind, 0 },
3900 { "personality", s_arm_unwind_personality, 0 },
3901 { "personalityindex", s_arm_unwind_personalityindex, 0 },
3902 { "handlerdata", s_arm_unwind_handlerdata, 0 },
3903 { "save", s_arm_unwind_save, 0 },
3904 { "vsave", s_arm_unwind_save, 1 },
3905 { "movsp", s_arm_unwind_movsp, 0 },
3906 { "pad", s_arm_unwind_pad, 0 },
3907 { "setfp", s_arm_unwind_setfp, 0 },
3908 { "unwind_raw", s_arm_unwind_raw, 0 },
3909 { "eabi_attribute", s_arm_eabi_attribute, 0 },
3910#else
3911 { "word", cons, 4},
3912
3913 /* These are used for dwarf. */
3914 {"2byte", cons, 2},
3915 {"4byte", cons, 4},
3916 {"8byte", cons, 8},
3917 /* These are used for dwarf2. */
3918 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
3919 { "loc", dwarf2_directive_loc, 0 },
3920 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
3921#endif
3922 { "extend", float_cons, 'x' },
3923 { "ldouble", float_cons, 'x' },
3924 { "packed", float_cons, 'p' },
3925#ifdef TE_PE
3926 {"secrel32", pe_directive_secrel, 0},
3927#endif
3928 { 0, 0, 0 }
3929};
3930
3931/* Parser functions used exclusively in instruction operands. */
3932
3933/* Generic immediate-value read function for use in insn parsing.
3934 STR points to the beginning of the immediate (the leading #);
3935 VAL receives the value; if the value is outside [MIN, MAX]
3936 issue an error. PREFIX_OPT is true if the immediate prefix is
3937 optional. */
3938
3939static int
3940parse_immediate (char **str, int *val, int min, int max,
3941 bfd_boolean prefix_opt)
3942{
3943 expressionS exp;
3944 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
3945 if (exp.X_op != O_constant)
3946 {
3947 inst.error = _("constant expression required");
3948 return FAIL;
3949 }
3950
3951 if (exp.X_add_number < min || exp.X_add_number > max)
3952 {
3953 inst.error = _("immediate value out of range");
3954 return FAIL;
3955 }
3956
3957 *val = exp.X_add_number;
3958 return SUCCESS;
3959}
3960
3961/* Less-generic immediate-value read function with the possibility of loading a
3962 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
3963 instructions. Puts the result directly in inst.operands[i]. */
3964
3965static int
3966parse_big_immediate (char **str, int i)
3967{
3968 expressionS exp;
3969 char *ptr = *str;
3970
3971 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
3972
3973 if (exp.X_op == O_constant)
3974 {
3975 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
3976 /* If we're on a 64-bit host, then a 64-bit number can be returned using
3977 O_constant. We have to be careful not to break compilation for
3978 32-bit X_add_number, though. */
3979 if ((exp.X_add_number & ~0xffffffffl) != 0)
3980 {
3981 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
3982 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
3983 inst.operands[i].regisimm = 1;
3984 }
3985 }
3986 else if (exp.X_op == O_big
3987 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32
3988 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64)
3989 {
3990 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
3991 /* Bignums have their least significant bits in
3992 generic_bignum[0]. Make sure we put 32 bits in imm and
3993 32 bits in reg, in a (hopefully) portable way. */
3994 assert (parts != 0);
3995 inst.operands[i].imm = 0;
3996 for (j = 0; j < parts; j++, idx++)
3997 inst.operands[i].imm |= generic_bignum[idx]
3998 << (LITTLENUM_NUMBER_OF_BITS * j);
3999 inst.operands[i].reg = 0;
4000 for (j = 0; j < parts; j++, idx++)
4001 inst.operands[i].reg |= generic_bignum[idx]
4002 << (LITTLENUM_NUMBER_OF_BITS * j);
4003 inst.operands[i].regisimm = 1;
4004 }
4005 else
4006 return FAIL;
4007
4008 *str = ptr;
4009
4010 return SUCCESS;
4011}
4012
4013/* Returns the pseudo-register number of an FPA immediate constant,
4014 or FAIL if there isn't a valid constant here. */
4015
4016static int
4017parse_fpa_immediate (char ** str)
4018{
4019 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4020 char * save_in;
4021 expressionS exp;
4022 int i;
4023 int j;
4024
4025 /* First try and match exact strings, this is to guarantee
4026 that some formats will work even for cross assembly. */
4027
4028 for (i = 0; fp_const[i]; i++)
4029 {
4030 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4031 {
4032 char *start = *str;
4033
4034 *str += strlen (fp_const[i]);
4035 if (is_end_of_line[(unsigned char) **str])
4036 return i + 8;
4037 *str = start;
4038 }
4039 }
4040
4041 /* Just because we didn't get a match doesn't mean that the constant
4042 isn't valid, just that it is in a format that we don't
4043 automatically recognize. Try parsing it with the standard
4044 expression routines. */
4045
4046 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4047
4048 /* Look for a raw floating point number. */
4049 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4050 && is_end_of_line[(unsigned char) *save_in])
4051 {
4052 for (i = 0; i < NUM_FLOAT_VALS; i++)
4053 {
4054 for (j = 0; j < MAX_LITTLENUMS; j++)
4055 {
4056 if (words[j] != fp_values[i][j])
4057 break;
4058 }
4059
4060 if (j == MAX_LITTLENUMS)
4061 {
4062 *str = save_in;
4063 return i + 8;
4064 }
4065 }
4066 }
4067
4068 /* Try and parse a more complex expression, this will probably fail
4069 unless the code uses a floating point prefix (eg "0f"). */
4070 save_in = input_line_pointer;
4071 input_line_pointer = *str;
4072 if (expression (&exp) == absolute_section
4073 && exp.X_op == O_big
4074 && exp.X_add_number < 0)
4075 {
4076 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4077 Ditto for 15. */
4078 if (gen_to_words (words, 5, (long) 15) == 0)
4079 {
4080 for (i = 0; i < NUM_FLOAT_VALS; i++)
4081 {
4082 for (j = 0; j < MAX_LITTLENUMS; j++)
4083 {
4084 if (words[j] != fp_values[i][j])
4085 break;
4086 }
4087
4088 if (j == MAX_LITTLENUMS)
4089 {
4090 *str = input_line_pointer;
4091 input_line_pointer = save_in;
4092 return i + 8;
4093 }
4094 }
4095 }
4096 }
4097
4098 *str = input_line_pointer;
4099 input_line_pointer = save_in;
4100 inst.error = _("invalid FPA immediate expression");
4101 return FAIL;
4102}
4103
4104/* Returns 1 if a number has "quarter-precision" float format
4105 0baBbbbbbc defgh000 00000000 00000000. */
4106
4107static int
4108is_quarter_float (unsigned imm)
4109{
4110 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4111 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4112}
4113
4114/* Parse an 8-bit "quarter-precision" floating point number of the form:
4115 0baBbbbbbc defgh000 00000000 00000000.
4116 The zero and minus-zero cases need special handling, since they can't be
4117 encoded in the "quarter-precision" float format, but can nonetheless be
4118 loaded as integer constants. */
4119
4120static unsigned
4121parse_qfloat_immediate (char **ccp, int *immed)
4122{
4123 char *str = *ccp;
4124 char *fpnum;
4125 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4126 int found_fpchar = 0;
4127
4128 skip_past_char (&str, '#');
4129
4130 /* We must not accidentally parse an integer as a floating-point number. Make
4131 sure that the value we parse is not an integer by checking for special
4132 characters '.' or 'e'.
4133 FIXME: This is a horrible hack, but doing better is tricky because type
4134 information isn't in a very usable state at parse time. */
4135 fpnum = str;
4136 skip_whitespace (fpnum);
4137
4138 if (strncmp (fpnum, "0x", 2) == 0)
4139 return FAIL;
4140 else
4141 {
4142 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4143 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4144 {
4145 found_fpchar = 1;
4146 break;
4147 }
4148
4149 if (!found_fpchar)
4150 return FAIL;
4151 }
4152
4153 if ((str = atof_ieee (str, 's', words)) != NULL)
4154 {
4155 unsigned fpword = 0;
4156 int i;
4157
4158 /* Our FP word must be 32 bits (single-precision FP). */
4159 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4160 {
4161 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4162 fpword |= words[i];
4163 }
4164
4165 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4166 *immed = fpword;
4167 else
4168 return FAIL;
4169
4170 *ccp = str;
4171
4172 return SUCCESS;
4173 }
4174
4175 return FAIL;
4176}
4177
4178/* Shift operands. */
4179enum shift_kind
4180{
4181 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4182};
4183
4184struct asm_shift_name
4185{
4186 const char *name;
4187 enum shift_kind kind;
4188};
4189
4190/* Third argument to parse_shift. */
4191enum parse_shift_mode
4192{
4193 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4194 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4195 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4196 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4197 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4198};
4199
4200/* Parse a <shift> specifier on an ARM data processing instruction.
4201 This has three forms:
4202
4203 (LSL|LSR|ASL|ASR|ROR) Rs
4204 (LSL|LSR|ASL|ASR|ROR) #imm
4205 RRX
4206
4207 Note that ASL is assimilated to LSL in the instruction encoding, and
4208 RRX to ROR #0 (which cannot be written as such). */
4209
4210static int
4211parse_shift (char **str, int i, enum parse_shift_mode mode)
4212{
4213 const struct asm_shift_name *shift_name;
4214 enum shift_kind shift;
4215 char *s = *str;
4216 char *p = s;
4217 int reg;
4218
4219 for (p = *str; ISALPHA (*p); p++)
4220 ;
4221
4222 if (p == *str)
4223 {
4224 inst.error = _("shift expression expected");
4225 return FAIL;
4226 }
4227
4228 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str);
4229
4230 if (shift_name == NULL)
4231 {
4232 inst.error = _("shift expression expected");
4233 return FAIL;
4234 }
4235
4236 shift = shift_name->kind;
4237
4238 switch (mode)
4239 {
4240 case NO_SHIFT_RESTRICT:
4241 case SHIFT_IMMEDIATE: break;
4242
4243 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4244 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4245 {
4246 inst.error = _("'LSL' or 'ASR' required");
4247 return FAIL;
4248 }
4249 break;
4250
4251 case SHIFT_LSL_IMMEDIATE:
4252 if (shift != SHIFT_LSL)
4253 {
4254 inst.error = _("'LSL' required");
4255 return FAIL;
4256 }
4257 break;
4258
4259 case SHIFT_ASR_IMMEDIATE:
4260 if (shift != SHIFT_ASR)
4261 {
4262 inst.error = _("'ASR' required");
4263 return FAIL;
4264 }
4265 break;
4266
4267 default: abort ();
4268 }
4269
4270 if (shift != SHIFT_RRX)
4271 {
4272 /* Whitespace can appear here if the next thing is a bare digit. */
4273 skip_whitespace (p);
4274
4275 if (mode == NO_SHIFT_RESTRICT
4276 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4277 {
4278 inst.operands[i].imm = reg;
4279 inst.operands[i].immisreg = 1;
4280 }
4281 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4282 return FAIL;
4283 }
4284 inst.operands[i].shift_kind = shift;
4285 inst.operands[i].shifted = 1;
4286 *str = p;
4287 return SUCCESS;
4288}
4289
4290/* Parse a <shifter_operand> for an ARM data processing instruction:
4291
4292 #<immediate>
4293 #<immediate>, <rotate>
4294 <Rm>
4295 <Rm>, <shift>
4296
4297 where <shift> is defined by parse_shift above, and <rotate> is a
4298 multiple of 2 between 0 and 30. Validation of immediate operands
4299 is deferred to md_apply_fix. */
4300
4301static int
4302parse_shifter_operand (char **str, int i)
4303{
4304 int value;
4305 expressionS expr;
4306
4307 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4308 {
4309 inst.operands[i].reg = value;
4310 inst.operands[i].isreg = 1;
4311
4312 /* parse_shift will override this if appropriate */
4313 inst.reloc.exp.X_op = O_constant;
4314 inst.reloc.exp.X_add_number = 0;
4315
4316 if (skip_past_comma (str) == FAIL)
4317 return SUCCESS;
4318
4319 /* Shift operation on register. */
4320 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4321 }
4322
4323 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4324 return FAIL;
4325
4326 if (skip_past_comma (str) == SUCCESS)
4327 {
4328 /* #x, y -- ie explicit rotation by Y. */
4329 if (my_get_expression (&expr, str, GE_NO_PREFIX))
4330 return FAIL;
4331
4332 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4333 {
4334 inst.error = _("constant expression expected");
4335 return FAIL;
4336 }
4337
4338 value = expr.X_add_number;
4339 if (value < 0 || value > 30 || value % 2 != 0)
4340 {
4341 inst.error = _("invalid rotation");
4342 return FAIL;
4343 }
4344 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4345 {
4346 inst.error = _("invalid constant");
4347 return FAIL;
4348 }
4349
4350 /* Convert to decoded value. md_apply_fix will put it back. */
4351 inst.reloc.exp.X_add_number
4352 = (((inst.reloc.exp.X_add_number << (32 - value))
4353 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
4354 }
4355
4356 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4357 inst.reloc.pc_rel = 0;
4358 return SUCCESS;
4359}
4360
4361/* Group relocation information. Each entry in the table contains the
4362 textual name of the relocation as may appear in assembler source
4363 and must end with a colon.
4364 Along with this textual name are the relocation codes to be used if
4365 the corresponding instruction is an ALU instruction (ADD or SUB only),
4366 an LDR, an LDRS, or an LDC. */
4367
4368struct group_reloc_table_entry
4369{
4370 const char *name;
4371 int alu_code;
4372 int ldr_code;
4373 int ldrs_code;
4374 int ldc_code;
4375};
4376
4377typedef enum
4378{
4379 /* Varieties of non-ALU group relocation. */
4380
4381 GROUP_LDR,
4382 GROUP_LDRS,
4383 GROUP_LDC
4384} group_reloc_type;
4385
4386static struct group_reloc_table_entry group_reloc_table[] =
4387 { /* Program counter relative: */
4388 { "pc_g0_nc",
4389 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4390 0, /* LDR */
4391 0, /* LDRS */
4392 0 }, /* LDC */
4393 { "pc_g0",
4394 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4395 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4396 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4397 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4398 { "pc_g1_nc",
4399 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4400 0, /* LDR */
4401 0, /* LDRS */
4402 0 }, /* LDC */
4403 { "pc_g1",
4404 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4405 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4406 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4407 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4408 { "pc_g2",
4409 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4410 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4411 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4412 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4413 /* Section base relative */
4414 { "sb_g0_nc",
4415 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4416 0, /* LDR */
4417 0, /* LDRS */
4418 0 }, /* LDC */
4419 { "sb_g0",
4420 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4421 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4422 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4423 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4424 { "sb_g1_nc",
4425 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4426 0, /* LDR */
4427 0, /* LDRS */
4428 0 }, /* LDC */
4429 { "sb_g1",
4430 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4431 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4432 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4433 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4434 { "sb_g2",
4435 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4436 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4437 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4438 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4439
4440/* Given the address of a pointer pointing to the textual name of a group
4441 relocation as may appear in assembler source, attempt to find its details
4442 in group_reloc_table. The pointer will be updated to the character after
4443 the trailing colon. On failure, FAIL will be returned; SUCCESS
4444 otherwise. On success, *entry will be updated to point at the relevant
4445 group_reloc_table entry. */
4446
4447static int
4448find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
4449{
4450 unsigned int i;
4451 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
4452 {
4453 int length = strlen (group_reloc_table[i].name);
4454
4455 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 &&
4456 (*str)[length] == ':')
4457 {
4458 *out = &group_reloc_table[i];
4459 *str += (length + 1);
4460 return SUCCESS;
4461 }
4462 }
4463
4464 return FAIL;
4465}
4466
4467/* Parse a <shifter_operand> for an ARM data processing instruction
4468 (as for parse_shifter_operand) where group relocations are allowed:
4469
4470 #<immediate>
4471 #<immediate>, <rotate>
4472 #:<group_reloc>:<expression>
4473 <Rm>
4474 <Rm>, <shift>
4475
4476 where <group_reloc> is one of the strings defined in group_reloc_table.
4477 The hashes are optional.
4478
4479 Everything else is as for parse_shifter_operand. */
4480
4481static parse_operand_result
4482parse_shifter_operand_group_reloc (char **str, int i)
4483{
4484 /* Determine if we have the sequence of characters #: or just :
4485 coming next. If we do, then we check for a group relocation.
4486 If we don't, punt the whole lot to parse_shifter_operand. */
4487
4488 if (((*str)[0] == '#' && (*str)[1] == ':')
4489 || (*str)[0] == ':')
4490 {
4491 struct group_reloc_table_entry *entry;
4492
4493 if ((*str)[0] == '#')
4494 (*str) += 2;
4495 else
4496 (*str)++;
4497
4498 /* Try to parse a group relocation. Anything else is an error. */
4499 if (find_group_reloc_table_entry (str, &entry) == FAIL)
4500 {
4501 inst.error = _("unknown group relocation");
4502 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4503 }
4504
4505 /* We now have the group relocation table entry corresponding to
4506 the name in the assembler source. Next, we parse the expression. */
4507 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
4508 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4509
4510 /* Record the relocation type (always the ALU variant here). */
4511 inst.reloc.type = entry->alu_code;
4512 assert (inst.reloc.type != 0);
4513
4514 return PARSE_OPERAND_SUCCESS;
4515 }
4516 else
4517 return parse_shifter_operand (str, i) == SUCCESS
4518 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
4519
4520 /* Never reached. */
4521}
4522
4523/* Parse all forms of an ARM address expression. Information is written
4524 to inst.operands[i] and/or inst.reloc.
4525
4526 Preindexed addressing (.preind=1):
4527
4528 [Rn, #offset] .reg=Rn .reloc.exp=offset
4529 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4530 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4531 .shift_kind=shift .reloc.exp=shift_imm
4532
4533 These three may have a trailing ! which causes .writeback to be set also.
4534
4535 Postindexed addressing (.postind=1, .writeback=1):
4536
4537 [Rn], #offset .reg=Rn .reloc.exp=offset
4538 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4539 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4540 .shift_kind=shift .reloc.exp=shift_imm
4541
4542 Unindexed addressing (.preind=0, .postind=0):
4543
4544 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4545
4546 Other:
4547
4548 [Rn]{!} shorthand for [Rn,#0]{!}
4549 =immediate .isreg=0 .reloc.exp=immediate
4550 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4551
4552 It is the caller's responsibility to check for addressing modes not
4553 supported by the instruction, and to set inst.reloc.type. */
4554
4555static parse_operand_result
4556parse_address_main (char **str, int i, int group_relocations,
4557 group_reloc_type group_type)
4558{
4559 char *p = *str;
4560 int reg;
4561
4562 if (skip_past_char (&p, '[') == FAIL)
4563 {
4564 if (skip_past_char (&p, '=') == FAIL)
4565 {
4566 /* bare address - translate to PC-relative offset */
4567 inst.reloc.pc_rel = 1;
4568 inst.operands[i].reg = REG_PC;
4569 inst.operands[i].isreg = 1;
4570 inst.operands[i].preind = 1;
4571 }
4572 /* else a load-constant pseudo op, no special treatment needed here */
4573
4574 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4575 return PARSE_OPERAND_FAIL;
4576
4577 *str = p;
4578 return PARSE_OPERAND_SUCCESS;
4579 }
4580
4581 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
4582 {
4583 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
4584 return PARSE_OPERAND_FAIL;
4585 }
4586 inst.operands[i].reg = reg;
4587 inst.operands[i].isreg = 1;
4588
4589 if (skip_past_comma (&p) == SUCCESS)
4590 {
4591 inst.operands[i].preind = 1;
4592
4593 if (*p == '+') p++;
4594 else if (*p == '-') p++, inst.operands[i].negative = 1;
4595
4596 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4597 {
4598 inst.operands[i].imm = reg;
4599 inst.operands[i].immisreg = 1;
4600
4601 if (skip_past_comma (&p) == SUCCESS)
4602 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4603 return PARSE_OPERAND_FAIL;
4604 }
4605 else if (skip_past_char (&p, ':') == SUCCESS)
4606 {
4607 /* FIXME: '@' should be used here, but it's filtered out by generic
4608 code before we get to see it here. This may be subject to
4609 change. */
4610 expressionS exp;
4611 my_get_expression (&exp, &p, GE_NO_PREFIX);
4612 if (exp.X_op != O_constant)
4613 {
4614 inst.error = _("alignment must be constant");
4615 return PARSE_OPERAND_FAIL;
4616 }
4617 inst.operands[i].imm = exp.X_add_number << 8;
4618 inst.operands[i].immisalign = 1;
4619 /* Alignments are not pre-indexes. */
4620 inst.operands[i].preind = 0;
4621 }
4622 else
4623 {
4624 if (inst.operands[i].negative)
4625 {
4626 inst.operands[i].negative = 0;
4627 p--;
4628 }
4629
4630 if (group_relocations &&
4631 ((*p == '#' && *(p + 1) == ':') || *p == ':'))
4632
4633 {
4634 struct group_reloc_table_entry *entry;
4635
4636 /* Skip over the #: or : sequence. */
4637 if (*p == '#')
4638 p += 2;
4639 else
4640 p++;
4641
4642 /* Try to parse a group relocation. Anything else is an
4643 error. */
4644 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
4645 {
4646 inst.error = _("unknown group relocation");
4647 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4648 }
4649
4650 /* We now have the group relocation table entry corresponding to
4651 the name in the assembler source. Next, we parse the
4652 expression. */
4653 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4654 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4655
4656 /* Record the relocation type. */
4657 switch (group_type)
4658 {
4659 case GROUP_LDR:
4660 inst.reloc.type = entry->ldr_code;
4661 break;
4662
4663 case GROUP_LDRS:
4664 inst.reloc.type = entry->ldrs_code;
4665 break;
4666
4667 case GROUP_LDC:
4668 inst.reloc.type = entry->ldc_code;
4669 break;
4670
4671 default:
4672 assert (0);
4673 }
4674
4675 if (inst.reloc.type == 0)
4676 {
4677 inst.error = _("this group relocation is not allowed on this instruction");
4678 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4679 }
4680 }
4681 else
4682 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4683 return PARSE_OPERAND_FAIL;
4684 }
4685 }
4686
4687 if (skip_past_char (&p, ']') == FAIL)
4688 {
4689 inst.error = _("']' expected");
4690 return PARSE_OPERAND_FAIL;
4691 }
4692
4693 if (skip_past_char (&p, '!') == SUCCESS)
4694 inst.operands[i].writeback = 1;
4695
4696 else if (skip_past_comma (&p) == SUCCESS)
4697 {
4698 if (skip_past_char (&p, '{') == SUCCESS)
4699 {
4700 /* [Rn], {expr} - unindexed, with option */
4701 if (parse_immediate (&p, &inst.operands[i].imm,
4702 0, 255, TRUE) == FAIL)
4703 return PARSE_OPERAND_FAIL;
4704
4705 if (skip_past_char (&p, '}') == FAIL)
4706 {
4707 inst.error = _("'}' expected at end of 'option' field");
4708 return PARSE_OPERAND_FAIL;
4709 }
4710 if (inst.operands[i].preind)
4711 {
4712 inst.error = _("cannot combine index with option");
4713 return PARSE_OPERAND_FAIL;
4714 }
4715 *str = p;
4716 return PARSE_OPERAND_SUCCESS;
4717 }
4718 else
4719 {
4720 inst.operands[i].postind = 1;
4721 inst.operands[i].writeback = 1;
4722
4723 if (inst.operands[i].preind)
4724 {
4725 inst.error = _("cannot combine pre- and post-indexing");
4726 return PARSE_OPERAND_FAIL;
4727 }
4728
4729 if (*p == '+') p++;
4730 else if (*p == '-') p++, inst.operands[i].negative = 1;
4731
4732 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4733 {
4734 /* We might be using the immediate for alignment already. If we
4735 are, OR the register number into the low-order bits. */
4736 if (inst.operands[i].immisalign)
4737 inst.operands[i].imm |= reg;
4738 else
4739 inst.operands[i].imm = reg;
4740 inst.operands[i].immisreg = 1;
4741
4742 if (skip_past_comma (&p) == SUCCESS)
4743 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4744 return PARSE_OPERAND_FAIL;
4745 }
4746 else
4747 {
4748 if (inst.operands[i].negative)
4749 {
4750 inst.operands[i].negative = 0;
4751 p--;
4752 }
4753 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4754 return PARSE_OPERAND_FAIL;
4755 }
4756 }
4757 }
4758
4759 /* If at this point neither .preind nor .postind is set, we have a
4760 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4761 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
4762 {
4763 inst.operands[i].preind = 1;
4764 inst.reloc.exp.X_op = O_constant;
4765 inst.reloc.exp.X_add_number = 0;
4766 }
4767 *str = p;
4768 return PARSE_OPERAND_SUCCESS;
4769}
4770
4771static int
4772parse_address (char **str, int i)
4773{
4774 return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS
4775 ? SUCCESS : FAIL;
4776}
4777
4778static parse_operand_result
4779parse_address_group_reloc (char **str, int i, group_reloc_type type)
4780{
4781 return parse_address_main (str, i, 1, type);
4782}
4783
4784/* Parse an operand for a MOVW or MOVT instruction. */
4785static int
4786parse_half (char **str)
4787{
4788 char * p;
4789
4790 p = *str;
4791 skip_past_char (&p, '#');
4792 if (strncasecmp (p, ":lower16:", 9) == 0)
4793 inst.reloc.type = BFD_RELOC_ARM_MOVW;
4794 else if (strncasecmp (p, ":upper16:", 9) == 0)
4795 inst.reloc.type = BFD_RELOC_ARM_MOVT;
4796
4797 if (inst.reloc.type != BFD_RELOC_UNUSED)
4798 {
4799 p += 9;
4800 skip_whitespace(p);
4801 }
4802
4803 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4804 return FAIL;
4805
4806 if (inst.reloc.type == BFD_RELOC_UNUSED)
4807 {
4808 if (inst.reloc.exp.X_op != O_constant)
4809 {
4810 inst.error = _("constant expression expected");
4811 return FAIL;
4812 }
4813 if (inst.reloc.exp.X_add_number < 0
4814 || inst.reloc.exp.X_add_number > 0xffff)
4815 {
4816 inst.error = _("immediate value out of range");
4817 return FAIL;
4818 }
4819 }
4820 *str = p;
4821 return SUCCESS;
4822}
4823
4824/* Miscellaneous. */
4825
4826/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4827 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4828static int
4829parse_psr (char **str)
4830{
4831 char *p;
4832 unsigned long psr_field;
4833 const struct asm_psr *psr;
4834 char *start;
4835
4836 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4837 feature for ease of use and backwards compatibility. */
4838 p = *str;
4839 if (strncasecmp (p, "SPSR", 4) == 0)
4840 psr_field = SPSR_BIT;
4841 else if (strncasecmp (p, "CPSR", 4) == 0)
4842 psr_field = 0;
4843 else
4844 {
4845 start = p;
4846 do
4847 p++;
4848 while (ISALNUM (*p) || *p == '_');
4849
4850 psr = hash_find_n (arm_v7m_psr_hsh, start, p - start);
4851 if (!psr)
4852 return FAIL;
4853
4854 *str = p;
4855 return psr->field;
4856 }
4857
4858 p += 4;
4859 if (*p == '_')
4860 {
4861 /* A suffix follows. */
4862 p++;
4863 start = p;
4864
4865 do
4866 p++;
4867 while (ISALNUM (*p) || *p == '_');
4868
4869 psr = hash_find_n (arm_psr_hsh, start, p - start);
4870 if (!psr)
4871 goto error;
4872
4873 psr_field |= psr->field;
4874 }
4875 else
4876 {
4877 if (ISALNUM (*p))
4878 goto error; /* Garbage after "[CS]PSR". */
4879
4880 psr_field |= (PSR_c | PSR_f);
4881 }
4882 *str = p;
4883 return psr_field;
4884
4885 error:
4886 inst.error = _("flag for {c}psr instruction expected");
4887 return FAIL;
4888}
4889
4890/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4891 value suitable for splatting into the AIF field of the instruction. */
4892
4893static int
4894parse_cps_flags (char **str)
4895{
4896 int val = 0;
4897 int saw_a_flag = 0;
4898 char *s = *str;
4899
4900 for (;;)
4901 switch (*s++)
4902 {
4903 case '\0': case ',':
4904 goto done;
4905
4906 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
4907 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
4908 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
4909
4910 default:
4911 inst.error = _("unrecognized CPS flag");
4912 return FAIL;
4913 }
4914
4915 done:
4916 if (saw_a_flag == 0)
4917 {
4918 inst.error = _("missing CPS flags");
4919 return FAIL;
4920 }
4921
4922 *str = s - 1;
4923 return val;
4924}
4925
4926/* Parse an endian specifier ("BE" or "LE", case insensitive);
4927 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4928
4929static int
4930parse_endian_specifier (char **str)
4931{
4932 int little_endian;
4933 char *s = *str;
4934
4935 if (strncasecmp (s, "BE", 2))
4936 little_endian = 0;
4937 else if (strncasecmp (s, "LE", 2))
4938 little_endian = 1;
4939 else
4940 {
4941 inst.error = _("valid endian specifiers are be or le");
4942 return FAIL;
4943 }
4944
4945 if (ISALNUM (s[2]) || s[2] == '_')
4946 {
4947 inst.error = _("valid endian specifiers are be or le");
4948 return FAIL;
4949 }
4950
4951 *str = s + 2;
4952 return little_endian;
4953}
4954
4955/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
4956 value suitable for poking into the rotate field of an sxt or sxta
4957 instruction, or FAIL on error. */
4958
4959static int
4960parse_ror (char **str)
4961{
4962 int rot;
4963 char *s = *str;
4964
4965 if (strncasecmp (s, "ROR", 3) == 0)
4966 s += 3;
4967 else
4968 {
4969 inst.error = _("missing rotation field after comma");
4970 return FAIL;
4971 }
4972
4973 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
4974 return FAIL;
4975
4976 switch (rot)
4977 {
4978 case 0: *str = s; return 0x0;
4979 case 8: *str = s; return 0x1;
4980 case 16: *str = s; return 0x2;
4981 case 24: *str = s; return 0x3;
4982
4983 default:
4984 inst.error = _("rotation can only be 0, 8, 16, or 24");
4985 return FAIL;
4986 }
4987}
4988
4989/* Parse a conditional code (from conds[] below). The value returned is in the
4990 range 0 .. 14, or FAIL. */
4991static int
4992parse_cond (char **str)
4993{
4994 char *p, *q;
4995 const struct asm_cond *c;
4996
4997 p = q = *str;
4998 while (ISALPHA (*q))
4999 q++;
5000
5001 c = hash_find_n (arm_cond_hsh, p, q - p);
5002 if (!c)
5003 {
5004 inst.error = _("condition required");
5005 return FAIL;
5006 }
5007
5008 *str = q;
5009 return c->value;
5010}
5011
5012/* Parse an option for a barrier instruction. Returns the encoding for the
5013 option, or FAIL. */
5014static int
5015parse_barrier (char **str)
5016{
5017 char *p, *q;
5018 const struct asm_barrier_opt *o;
5019
5020 p = q = *str;
5021 while (ISALPHA (*q))
5022 q++;
5023
5024 o = hash_find_n (arm_barrier_opt_hsh, p, q - p);
5025 if (!o)
5026 return FAIL;
5027
5028 *str = q;
5029 return o->value;
5030}
5031
5032/* Parse the operands of a table branch instruction. Similar to a memory
5033 operand. */
5034static int
5035parse_tb (char **str)
5036{
5037 char * p = *str;
5038 int reg;
5039
5040 if (skip_past_char (&p, '[') == FAIL)
5041 {
5042 inst.error = _("'[' expected");
5043 return FAIL;
5044 }
5045
5046 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5047 {
5048 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5049 return FAIL;
5050 }
5051 inst.operands[0].reg = reg;
5052
5053 if (skip_past_comma (&p) == FAIL)
5054 {
5055 inst.error = _("',' expected");
5056 return FAIL;
5057 }
5058
5059 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5060 {
5061 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5062 return FAIL;
5063 }
5064 inst.operands[0].imm = reg;
5065
5066 if (skip_past_comma (&p) == SUCCESS)
5067 {
5068 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5069 return FAIL;
5070 if (inst.reloc.exp.X_add_number != 1)
5071 {
5072 inst.error = _("invalid shift");
5073 return FAIL;
5074 }
5075 inst.operands[0].shifted = 1;
5076 }
5077
5078 if (skip_past_char (&p, ']') == FAIL)
5079 {
5080 inst.error = _("']' expected");
5081 return FAIL;
5082 }
5083 *str = p;
5084 return SUCCESS;
5085}
5086
5087/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5088 information on the types the operands can take and how they are encoded.
5089 Up to four operands may be read; this function handles setting the
5090 ".present" field for each read operand itself.
5091 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5092 else returns FAIL. */
5093
5094static int
5095parse_neon_mov (char **str, int *which_operand)
5096{
5097 int i = *which_operand, val;
5098 enum arm_reg_type rtype;
5099 char *ptr = *str;
5100 struct neon_type_el optype;
5101
5102 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5103 {
5104 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5105 inst.operands[i].reg = val;
5106 inst.operands[i].isscalar = 1;
5107 inst.operands[i].vectype = optype;
5108 inst.operands[i++].present = 1;
5109
5110 if (skip_past_comma (&ptr) == FAIL)
5111 goto wanted_comma;
5112
5113 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5114 goto wanted_arm;
5115
5116 inst.operands[i].reg = val;
5117 inst.operands[i].isreg = 1;
5118 inst.operands[i].present = 1;
5119 }
5120 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5121 != FAIL)
5122 {
5123 /* Cases 0, 1, 2, 3, 5 (D only). */
5124 if (skip_past_comma (&ptr) == FAIL)
5125 goto wanted_comma;
5126
5127 inst.operands[i].reg = val;
5128 inst.operands[i].isreg = 1;
5129 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5130 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5131 inst.operands[i].isvec = 1;
5132 inst.operands[i].vectype = optype;
5133 inst.operands[i++].present = 1;
5134
5135 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5136 {
5137 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5138 Case 13: VMOV <Sd>, <Rm> */
5139 inst.operands[i].reg = val;
5140 inst.operands[i].isreg = 1;
5141 inst.operands[i].present = 1;
5142
5143 if (rtype == REG_TYPE_NQ)
5144 {
5145 first_error (_("can't use Neon quad register here"));
5146 return FAIL;
5147 }
5148 else if (rtype != REG_TYPE_VFS)
5149 {
5150 i++;
5151 if (skip_past_comma (&ptr) == FAIL)
5152 goto wanted_comma;
5153 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5154 goto wanted_arm;
5155 inst.operands[i].reg = val;
5156 inst.operands[i].isreg = 1;
5157 inst.operands[i].present = 1;
5158 }
5159 }
5160 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5161 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5162 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5163 Case 10: VMOV.F32 <Sd>, #<imm>
5164 Case 11: VMOV.F64 <Dd>, #<imm> */
5165 inst.operands[i].immisfloat = 1;
5166 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5167 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5168 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5169 ;
5170 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5171 &optype)) != FAIL)
5172 {
5173 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5174 Case 1: VMOV<c><q> <Dd>, <Dm>
5175 Case 8: VMOV.F32 <Sd>, <Sm>
5176 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5177
5178 inst.operands[i].reg = val;
5179 inst.operands[i].isreg = 1;
5180 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5181 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5182 inst.operands[i].isvec = 1;
5183 inst.operands[i].vectype = optype;
5184 inst.operands[i].present = 1;
5185
5186 if (skip_past_comma (&ptr) == SUCCESS)
5187 {
5188 /* Case 15. */
5189 i++;
5190
5191 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5192 goto wanted_arm;
5193
5194 inst.operands[i].reg = val;
5195 inst.operands[i].isreg = 1;
5196 inst.operands[i++].present = 1;
5197
5198 if (skip_past_comma (&ptr) == FAIL)
5199 goto wanted_comma;
5200
5201 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5202 goto wanted_arm;
5203
5204 inst.operands[i].reg = val;
5205 inst.operands[i].isreg = 1;
5206 inst.operands[i++].present = 1;
5207 }
5208 }
5209 else
5210 {
5211 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5212 return FAIL;
5213 }
5214 }
5215 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5216 {
5217 /* Cases 6, 7. */
5218 inst.operands[i].reg = val;
5219 inst.operands[i].isreg = 1;
5220 inst.operands[i++].present = 1;
5221
5222 if (skip_past_comma (&ptr) == FAIL)
5223 goto wanted_comma;
5224
5225 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5226 {
5227 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5228 inst.operands[i].reg = val;
5229 inst.operands[i].isscalar = 1;
5230 inst.operands[i].present = 1;
5231 inst.operands[i].vectype = optype;
5232 }
5233 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5234 {
5235 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5236 inst.operands[i].reg = val;
5237 inst.operands[i].isreg = 1;
5238 inst.operands[i++].present = 1;
5239
5240 if (skip_past_comma (&ptr) == FAIL)
5241 goto wanted_comma;
5242
5243 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
5244 == FAIL)
5245 {
5246 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
5247 return FAIL;
5248 }
5249
5250 inst.operands[i].reg = val;
5251 inst.operands[i].isreg = 1;
5252 inst.operands[i].isvec = 1;
5253 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5254 inst.operands[i].vectype = optype;
5255 inst.operands[i].present = 1;
5256
5257 if (rtype == REG_TYPE_VFS)
5258 {
5259 /* Case 14. */
5260 i++;
5261 if (skip_past_comma (&ptr) == FAIL)
5262 goto wanted_comma;
5263 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
5264 &optype)) == FAIL)
5265 {
5266 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
5267 return FAIL;
5268 }
5269 inst.operands[i].reg = val;
5270 inst.operands[i].isreg = 1;
5271 inst.operands[i].isvec = 1;
5272 inst.operands[i].issingle = 1;
5273 inst.operands[i].vectype = optype;
5274 inst.operands[i].present = 1;
5275 }
5276 }
5277 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
5278 != FAIL)
5279 {
5280 /* Case 13. */
5281 inst.operands[i].reg = val;
5282 inst.operands[i].isreg = 1;
5283 inst.operands[i].isvec = 1;
5284 inst.operands[i].issingle = 1;
5285 inst.operands[i].vectype = optype;
5286 inst.operands[i++].present = 1;
5287 }
5288 }
5289 else
5290 {
5291 first_error (_("parse error"));
5292 return FAIL;
5293 }
5294
5295 /* Successfully parsed the operands. Update args. */
5296 *which_operand = i;
5297 *str = ptr;
5298 return SUCCESS;
5299
5300 wanted_comma:
5301 first_error (_("expected comma"));
5302 return FAIL;
5303
5304 wanted_arm:
5305 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
5306 return FAIL;
5307}
5308
5309/* Matcher codes for parse_operands. */
5310enum operand_parse_code
5311{
5312 OP_stop, /* end of line */
5313
5314 OP_RR, /* ARM register */
5315 OP_RRnpc, /* ARM register, not r15 */
5316 OP_RRnpcb, /* ARM register, not r15, in square brackets */
5317 OP_RRw, /* ARM register, not r15, optional trailing ! */
5318 OP_RCP, /* Coprocessor number */
5319 OP_RCN, /* Coprocessor register */
5320 OP_RF, /* FPA register */
5321 OP_RVS, /* VFP single precision register */
5322 OP_RVD, /* VFP double precision register (0..15) */
5323 OP_RND, /* Neon double precision register (0..31) */
5324 OP_RNQ, /* Neon quad precision register */
5325 OP_RVSD, /* VFP single or double precision register */
5326 OP_RNDQ, /* Neon double or quad precision register */
5327 OP_RNSDQ, /* Neon single, double or quad precision register */
5328 OP_RNSC, /* Neon scalar D[X] */
5329 OP_RVC, /* VFP control register */
5330 OP_RMF, /* Maverick F register */
5331 OP_RMD, /* Maverick D register */
5332 OP_RMFX, /* Maverick FX register */
5333 OP_RMDX, /* Maverick DX register */
5334 OP_RMAX, /* Maverick AX register */
5335 OP_RMDS, /* Maverick DSPSC register */
5336 OP_RIWR, /* iWMMXt wR register */
5337 OP_RIWC, /* iWMMXt wC register */
5338 OP_RIWG, /* iWMMXt wCG register */
5339 OP_RXA, /* XScale accumulator register */
5340
5341 OP_REGLST, /* ARM register list */
5342 OP_VRSLST, /* VFP single-precision register list */
5343 OP_VRDLST, /* VFP double-precision register list */
5344 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
5345 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
5346 OP_NSTRLST, /* Neon element/structure list */
5347
5348 OP_NILO, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5349 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
5350 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
5351 OP_RR_RNSC, /* ARM reg or Neon scalar. */
5352 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
5353 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
5354 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
5355 OP_VMOV, /* Neon VMOV operands. */
5356 OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN. */
5357 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
5358 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5359
5360 OP_I0, /* immediate zero */
5361 OP_I7, /* immediate value 0 .. 7 */
5362 OP_I15, /* 0 .. 15 */
5363 OP_I16, /* 1 .. 16 */
5364 OP_I16z, /* 0 .. 16 */
5365 OP_I31, /* 0 .. 31 */
5366 OP_I31w, /* 0 .. 31, optional trailing ! */
5367 OP_I32, /* 1 .. 32 */
5368 OP_I32z, /* 0 .. 32 */
5369 OP_I63, /* 0 .. 63 */
5370 OP_I63s, /* -64 .. 63 */
5371 OP_I64, /* 1 .. 64 */
5372 OP_I64z, /* 0 .. 64 */
5373 OP_I255, /* 0 .. 255 */
5374
5375 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
5376 OP_I7b, /* 0 .. 7 */
5377 OP_I15b, /* 0 .. 15 */
5378 OP_I31b, /* 0 .. 31 */
5379
5380 OP_SH, /* shifter operand */
5381 OP_SHG, /* shifter operand with possible group relocation */
5382 OP_ADDR, /* Memory address expression (any mode) */
5383 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
5384 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
5385 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
5386 OP_EXP, /* arbitrary expression */
5387 OP_EXPi, /* same, with optional immediate prefix */
5388 OP_EXPr, /* same, with optional relocation suffix */
5389 OP_HALF, /* 0 .. 65535 or low/high reloc. */
5390
5391 OP_CPSF, /* CPS flags */
5392 OP_ENDI, /* Endianness specifier */
5393 OP_PSR, /* CPSR/SPSR mask for msr */
5394 OP_COND, /* conditional code */
5395 OP_TB, /* Table branch. */
5396
5397 OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */
5398 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
5399
5400 OP_RRnpc_I0, /* ARM register or literal 0 */
5401 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
5402 OP_RR_EXi, /* ARM register or expression with imm prefix */
5403 OP_RF_IF, /* FPA register or immediate */
5404 OP_RIWR_RIWC, /* iWMMXt R or C reg */
5405 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
5406
5407 /* Optional operands. */
5408 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
5409 OP_oI31b, /* 0 .. 31 */
5410 OP_oI32b, /* 1 .. 32 */
5411 OP_oIffffb, /* 0 .. 65535 */
5412 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
5413
5414 OP_oRR, /* ARM register */
5415 OP_oRRnpc, /* ARM register, not the PC */
5416 OP_oRRw, /* ARM register, not r15, optional trailing ! */
5417 OP_oRND, /* Optional Neon double precision register */
5418 OP_oRNQ, /* Optional Neon quad precision register */
5419 OP_oRNDQ, /* Optional Neon double or quad precision register */
5420 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
5421 OP_oSHll, /* LSL immediate */
5422 OP_oSHar, /* ASR immediate */
5423 OP_oSHllar, /* LSL or ASR immediate */
5424 OP_oROR, /* ROR 0/8/16/24 */
5425 OP_oBARRIER, /* Option argument for a barrier instruction. */
5426
5427 OP_FIRST_OPTIONAL = OP_oI7b
5428};
5429
5430/* Generic instruction operand parser. This does no encoding and no
5431 semantic validation; it merely squirrels values away in the inst
5432 structure. Returns SUCCESS or FAIL depending on whether the
5433 specified grammar matched. */
5434static int
5435parse_operands (char *str, const unsigned char *pattern)
5436{
5437 unsigned const char *upat = pattern;
5438 char *backtrack_pos = 0;
5439 const char *backtrack_error = 0;
5440 int i, val, backtrack_index = 0;
5441 enum arm_reg_type rtype;
5442 parse_operand_result result;
5443
5444#define po_char_or_fail(chr) do { \
5445 if (skip_past_char (&str, chr) == FAIL) \
5446 goto bad_args; \
5447} while (0)
5448
5449#define po_reg_or_fail(regtype) do { \
5450 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5451 &inst.operands[i].vectype); \
5452 if (val == FAIL) \
5453 { \
5454 first_error (_(reg_expected_msgs[regtype])); \
5455 goto failure; \
5456 } \
5457 inst.operands[i].reg = val; \
5458 inst.operands[i].isreg = 1; \
5459 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5460 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5461 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5462 || rtype == REG_TYPE_VFD \
5463 || rtype == REG_TYPE_NQ); \
5464} while (0)
5465
5466#define po_reg_or_goto(regtype, label) do { \
5467 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5468 &inst.operands[i].vectype); \
5469 if (val == FAIL) \
5470 goto label; \
5471 \
5472 inst.operands[i].reg = val; \
5473 inst.operands[i].isreg = 1; \
5474 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5475 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5476 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5477 || rtype == REG_TYPE_VFD \
5478 || rtype == REG_TYPE_NQ); \
5479} while (0)
5480
5481#define po_imm_or_fail(min, max, popt) do { \
5482 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5483 goto failure; \
5484 inst.operands[i].imm = val; \
5485} while (0)
5486
5487#define po_scalar_or_goto(elsz, label) do { \
5488 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5489 if (val == FAIL) \
5490 goto label; \
5491 inst.operands[i].reg = val; \
5492 inst.operands[i].isscalar = 1; \
5493} while (0)
5494
5495#define po_misc_or_fail(expr) do { \
5496 if (expr) \
5497 goto failure; \
5498} while (0)
5499
5500#define po_misc_or_fail_no_backtrack(expr) do { \
5501 result = expr; \
5502 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5503 backtrack_pos = 0; \
5504 if (result != PARSE_OPERAND_SUCCESS) \
5505 goto failure; \
5506} while (0)
5507
5508 skip_whitespace (str);
5509
5510 for (i = 0; upat[i] != OP_stop; i++)
5511 {
5512 if (upat[i] >= OP_FIRST_OPTIONAL)
5513 {
5514 /* Remember where we are in case we need to backtrack. */
5515 assert (!backtrack_pos);
5516 backtrack_pos = str;
5517 backtrack_error = inst.error;
5518 backtrack_index = i;
5519 }
5520
5521 if (i > 0 && (i > 1 || inst.operands[0].present))
5522 po_char_or_fail (',');
5523
5524 switch (upat[i])
5525 {
5526 /* Registers */
5527 case OP_oRRnpc:
5528 case OP_RRnpc:
5529 case OP_oRR:
5530 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
5531 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
5532 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
5533 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
5534 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
5535 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
5536 case OP_oRND:
5537 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
5538 case OP_RVC:
5539 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
5540 break;
5541 /* Also accept generic coprocessor regs for unknown registers. */
5542 coproc_reg:
5543 po_reg_or_fail (REG_TYPE_CN);
5544 break;
5545 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
5546 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
5547 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
5548 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
5549 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
5550 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
5551 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
5552 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
5553 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
5554 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
5555 case OP_oRNQ:
5556 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
5557 case OP_oRNDQ:
5558 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
5559 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
5560 case OP_oRNSDQ:
5561 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
5562
5563 /* Neon scalar. Using an element size of 8 means that some invalid
5564 scalars are accepted here, so deal with those in later code. */
5565 case OP_RNSC: po_scalar_or_goto (8, failure); break;
5566
5567 /* WARNING: We can expand to two operands here. This has the potential
5568 to totally confuse the backtracking mechanism! It will be OK at
5569 least as long as we don't try to use optional args as well,
5570 though. */
5571 case OP_NILO:
5572 {
5573 po_reg_or_goto (REG_TYPE_NDQ, try_imm);
5574 inst.operands[i].present = 1;
5575 i++;
5576 skip_past_comma (&str);
5577 po_reg_or_goto (REG_TYPE_NDQ, one_reg_only);
5578 break;
5579 one_reg_only:
5580 /* Optional register operand was omitted. Unfortunately, it's in
5581 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5582 here (this is a bit grotty). */
5583 inst.operands[i] = inst.operands[i-1];
5584 inst.operands[i-1].present = 0;
5585 break;
5586 try_imm:
5587 /* There's a possibility of getting a 64-bit immediate here, so
5588 we need special handling. */
5589 if (parse_big_immediate (&str, i) == FAIL)
5590 {
5591 inst.error = _("immediate value is out of range");
5592 goto failure;
5593 }
5594 }
5595 break;
5596
5597 case OP_RNDQ_I0:
5598 {
5599 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
5600 break;
5601 try_imm0:
5602 po_imm_or_fail (0, 0, TRUE);
5603 }
5604 break;
5605
5606 case OP_RVSD_I0:
5607 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
5608 break;
5609
5610 case OP_RR_RNSC:
5611 {
5612 po_scalar_or_goto (8, try_rr);
5613 break;
5614 try_rr:
5615 po_reg_or_fail (REG_TYPE_RN);
5616 }
5617 break;
5618
5619 case OP_RNSDQ_RNSC:
5620 {
5621 po_scalar_or_goto (8, try_nsdq);
5622 break;
5623 try_nsdq:
5624 po_reg_or_fail (REG_TYPE_NSDQ);
5625 }
5626 break;
5627
5628 case OP_RNDQ_RNSC:
5629 {
5630 po_scalar_or_goto (8, try_ndq);
5631 break;
5632 try_ndq:
5633 po_reg_or_fail (REG_TYPE_NDQ);
5634 }
5635 break;
5636
5637 case OP_RND_RNSC:
5638 {
5639 po_scalar_or_goto (8, try_vfd);
5640 break;
5641 try_vfd:
5642 po_reg_or_fail (REG_TYPE_VFD);
5643 }
5644 break;
5645
5646 case OP_VMOV:
5647 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5648 not careful then bad things might happen. */
5649 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
5650 break;
5651
5652 case OP_RNDQ_IMVNb:
5653 {
5654 po_reg_or_goto (REG_TYPE_NDQ, try_mvnimm);
5655 break;
5656 try_mvnimm:
5657 /* There's a possibility of getting a 64-bit immediate here, so
5658 we need special handling. */
5659 if (parse_big_immediate (&str, i) == FAIL)
5660 {
5661 inst.error = _("immediate value is out of range");
5662 goto failure;
5663 }
5664 }
5665 break;
5666
5667 case OP_RNDQ_I63b:
5668 {
5669 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
5670 break;
5671 try_shimm:
5672 po_imm_or_fail (0, 63, TRUE);
5673 }
5674 break;
5675
5676 case OP_RRnpcb:
5677 po_char_or_fail ('[');
5678 po_reg_or_fail (REG_TYPE_RN);
5679 po_char_or_fail (']');
5680 break;
5681
5682 case OP_RRw:
5683 case OP_oRRw:
5684 po_reg_or_fail (REG_TYPE_RN);
5685 if (skip_past_char (&str, '!') == SUCCESS)
5686 inst.operands[i].writeback = 1;
5687 break;
5688
5689 /* Immediates */
5690 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
5691 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
5692 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
5693 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
5694 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
5695 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
5696 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
5697 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
5698 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
5699 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
5700 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
5701 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
5702
5703 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
5704 case OP_oI7b:
5705 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
5706 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
5707 case OP_oI31b:
5708 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
5709 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
5710 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
5711
5712 /* Immediate variants */
5713 case OP_oI255c:
5714 po_char_or_fail ('{');
5715 po_imm_or_fail (0, 255, TRUE);
5716 po_char_or_fail ('}');
5717 break;
5718
5719 case OP_I31w:
5720 /* The expression parser chokes on a trailing !, so we have
5721 to find it first and zap it. */
5722 {
5723 char *s = str;
5724 while (*s && *s != ',')
5725 s++;
5726 if (s[-1] == '!')
5727 {
5728 s[-1] = '\0';
5729 inst.operands[i].writeback = 1;
5730 }
5731 po_imm_or_fail (0, 31, TRUE);
5732 if (str == s - 1)
5733 str = s;
5734 }
5735 break;
5736
5737 /* Expressions */
5738 case OP_EXPi: EXPi:
5739 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5740 GE_OPT_PREFIX));
5741 break;
5742
5743 case OP_EXP:
5744 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5745 GE_NO_PREFIX));
5746 break;
5747
5748 case OP_EXPr: EXPr:
5749 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5750 GE_NO_PREFIX));
5751 if (inst.reloc.exp.X_op == O_symbol)
5752 {
5753 val = parse_reloc (&str);
5754 if (val == -1)
5755 {
5756 inst.error = _("unrecognized relocation suffix");
5757 goto failure;
5758 }
5759 else if (val != BFD_RELOC_UNUSED)
5760 {
5761 inst.operands[i].imm = val;
5762 inst.operands[i].hasreloc = 1;
5763 }
5764 }
5765 break;
5766
5767 /* Operand for MOVW or MOVT. */
5768 case OP_HALF:
5769 po_misc_or_fail (parse_half (&str));
5770 break;
5771
5772 /* Register or expression */
5773 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
5774 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
5775
5776 /* Register or immediate */
5777 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
5778 I0: po_imm_or_fail (0, 0, FALSE); break;
5779
5780 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
5781 IF:
5782 if (!is_immediate_prefix (*str))
5783 goto bad_args;
5784 str++;
5785 val = parse_fpa_immediate (&str);
5786 if (val == FAIL)
5787 goto failure;
5788 /* FPA immediates are encoded as registers 8-15.
5789 parse_fpa_immediate has already applied the offset. */
5790 inst.operands[i].reg = val;
5791 inst.operands[i].isreg = 1;
5792 break;
5793
5794 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
5795 I32z: po_imm_or_fail (0, 32, FALSE); break;
5796
5797 /* Two kinds of register */
5798 case OP_RIWR_RIWC:
5799 {
5800 struct reg_entry *rege = arm_reg_parse_multi (&str);
5801 if (!rege
5802 || (rege->type != REG_TYPE_MMXWR
5803 && rege->type != REG_TYPE_MMXWC
5804 && rege->type != REG_TYPE_MMXWCG))
5805 {
5806 inst.error = _("iWMMXt data or control register expected");
5807 goto failure;
5808 }
5809 inst.operands[i].reg = rege->number;
5810 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
5811 }
5812 break;
5813
5814 case OP_RIWC_RIWG:
5815 {
5816 struct reg_entry *rege = arm_reg_parse_multi (&str);
5817 if (!rege
5818 || (rege->type != REG_TYPE_MMXWC
5819 && rege->type != REG_TYPE_MMXWCG))
5820 {
5821 inst.error = _("iWMMXt control register expected");
5822 goto failure;
5823 }
5824 inst.operands[i].reg = rege->number;
5825 inst.operands[i].isreg = 1;
5826 }
5827 break;
5828
5829 /* Misc */
5830 case OP_CPSF: val = parse_cps_flags (&str); break;
5831 case OP_ENDI: val = parse_endian_specifier (&str); break;
5832 case OP_oROR: val = parse_ror (&str); break;
5833 case OP_PSR: val = parse_psr (&str); break;
5834 case OP_COND: val = parse_cond (&str); break;
5835 case OP_oBARRIER:val = parse_barrier (&str); break;
5836
5837 case OP_RVC_PSR:
5838 po_reg_or_goto (REG_TYPE_VFC, try_psr);
5839 inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */
5840 break;
5841 try_psr:
5842 val = parse_psr (&str);
5843 break;
5844
5845 case OP_APSR_RR:
5846 po_reg_or_goto (REG_TYPE_RN, try_apsr);
5847 break;
5848 try_apsr:
5849 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5850 instruction). */
5851 if (strncasecmp (str, "APSR_", 5) == 0)
5852 {
5853 unsigned found = 0;
5854 str += 5;
5855 while (found < 15)
5856 switch (*str++)
5857 {
5858 case 'c': found = (found & 1) ? 16 : found | 1; break;
5859 case 'n': found = (found & 2) ? 16 : found | 2; break;
5860 case 'z': found = (found & 4) ? 16 : found | 4; break;
5861 case 'v': found = (found & 8) ? 16 : found | 8; break;
5862 default: found = 16;
5863 }
5864 if (found != 15)
5865 goto failure;
5866 inst.operands[i].isvec = 1;
5867 }
5868 else
5869 goto failure;
5870 break;
5871
5872 case OP_TB:
5873 po_misc_or_fail (parse_tb (&str));
5874 break;
5875
5876 /* Register lists */
5877 case OP_REGLST:
5878 val = parse_reg_list (&str);
5879 if (*str == '^')
5880 {
5881 inst.operands[1].writeback = 1;
5882 str++;
5883 }
5884 break;
5885
5886 case OP_VRSLST:
5887 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
5888 break;
5889
5890 case OP_VRDLST:
5891 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
5892 break;
5893
5894 case OP_VRSDLST:
5895 /* Allow Q registers too. */
5896 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5897 REGLIST_NEON_D);
5898 if (val == FAIL)
5899 {
5900 inst.error = NULL;
5901 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5902 REGLIST_VFP_S);
5903 inst.operands[i].issingle = 1;
5904 }
5905 break;
5906
5907 case OP_NRDLST:
5908 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5909 REGLIST_NEON_D);
5910 break;
5911
5912 case OP_NSTRLST:
5913 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
5914 &inst.operands[i].vectype);
5915 break;
5916
5917 /* Addressing modes */
5918 case OP_ADDR:
5919 po_misc_or_fail (parse_address (&str, i));
5920 break;
5921
5922 case OP_ADDRGLDR:
5923 po_misc_or_fail_no_backtrack (
5924 parse_address_group_reloc (&str, i, GROUP_LDR));
5925 break;
5926
5927 case OP_ADDRGLDRS:
5928 po_misc_or_fail_no_backtrack (
5929 parse_address_group_reloc (&str, i, GROUP_LDRS));
5930 break;
5931
5932 case OP_ADDRGLDC:
5933 po_misc_or_fail_no_backtrack (
5934 parse_address_group_reloc (&str, i, GROUP_LDC));
5935 break;
5936
5937 case OP_SH:
5938 po_misc_or_fail (parse_shifter_operand (&str, i));
5939 break;
5940
5941 case OP_SHG:
5942 po_misc_or_fail_no_backtrack (
5943 parse_shifter_operand_group_reloc (&str, i));
5944 break;
5945
5946 case OP_oSHll:
5947 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
5948 break;
5949
5950 case OP_oSHar:
5951 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
5952 break;
5953
5954 case OP_oSHllar:
5955 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
5956 break;
5957
5958 default:
5959 as_fatal ("unhandled operand code %d", upat[i]);
5960 }
5961
5962 /* Various value-based sanity checks and shared operations. We
5963 do not signal immediate failures for the register constraints;
5964 this allows a syntax error to take precedence. */
5965 switch (upat[i])
5966 {
5967 case OP_oRRnpc:
5968 case OP_RRnpc:
5969 case OP_RRnpcb:
5970 case OP_RRw:
5971 case OP_oRRw:
5972 case OP_RRnpc_I0:
5973 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
5974 inst.error = BAD_PC;
5975 break;
5976
5977 case OP_CPSF:
5978 case OP_ENDI:
5979 case OP_oROR:
5980 case OP_PSR:
5981 case OP_RVC_PSR:
5982 case OP_COND:
5983 case OP_oBARRIER:
5984 case OP_REGLST:
5985 case OP_VRSLST:
5986 case OP_VRDLST:
5987 case OP_VRSDLST:
5988 case OP_NRDLST:
5989 case OP_NSTRLST:
5990 if (val == FAIL)
5991 goto failure;
5992 inst.operands[i].imm = val;
5993 break;
5994
5995 default:
5996 break;
5997 }
5998
5999 /* If we get here, this operand was successfully parsed. */
6000 inst.operands[i].present = 1;
6001 continue;
6002
6003 bad_args:
6004 inst.error = BAD_ARGS;
6005
6006 failure:
6007 if (!backtrack_pos)
6008 {
6009 /* The parse routine should already have set inst.error, but set a
6010 defaut here just in case. */
6011 if (!inst.error)
6012 inst.error = _("syntax error");
6013 return FAIL;
6014 }
6015
6016 /* Do not backtrack over a trailing optional argument that
6017 absorbed some text. We will only fail again, with the
6018 'garbage following instruction' error message, which is
6019 probably less helpful than the current one. */
6020 if (backtrack_index == i && backtrack_pos != str
6021 && upat[i+1] == OP_stop)
6022 {
6023 if (!inst.error)
6024 inst.error = _("syntax error");
6025 return FAIL;
6026 }
6027
6028 /* Try again, skipping the optional argument at backtrack_pos. */
6029 str = backtrack_pos;
6030 inst.error = backtrack_error;
6031 inst.operands[backtrack_index].present = 0;
6032 i = backtrack_index;
6033 backtrack_pos = 0;
6034 }
6035
6036 /* Check that we have parsed all the arguments. */
6037 if (*str != '\0' && !inst.error)
6038 inst.error = _("garbage following instruction");
6039
6040 return inst.error ? FAIL : SUCCESS;
6041}
6042
6043#undef po_char_or_fail
6044#undef po_reg_or_fail
6045#undef po_reg_or_goto
6046#undef po_imm_or_fail
6047#undef po_scalar_or_fail
6048
6049/* Shorthand macro for instruction encoding functions issuing errors. */
6050#define constraint(expr, err) do { \
6051 if (expr) \
6052 { \
6053 inst.error = err; \
6054 return; \
6055 } \
6056} while (0)
6057
6058/* Functions for operand encoding. ARM, then Thumb. */
6059
6060#define rotate_left(v, n) (v << n | v >> (32 - n))
6061
6062/* If VAL can be encoded in the immediate field of an ARM instruction,
6063 return the encoded form. Otherwise, return FAIL. */
6064
6065static unsigned int
6066encode_arm_immediate (unsigned int val)
6067{
6068 unsigned int a, i;
6069
6070 for (i = 0; i < 32; i += 2)
6071 if ((a = rotate_left (val, i)) <= 0xff)
6072 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6073
6074 return FAIL;
6075}
6076
6077/* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6078 return the encoded form. Otherwise, return FAIL. */
6079static unsigned int
6080encode_thumb32_immediate (unsigned int val)
6081{
6082 unsigned int a, i;
6083
6084 if (val <= 0xff)
6085 return val;
6086
6087 for (i = 1; i <= 24; i++)
6088 {
6089 a = val >> i;
6090 if ((val & ~(0xff << i)) == 0)
6091 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6092 }
6093
6094 a = val & 0xff;
6095 if (val == ((a << 16) | a))
6096 return 0x100 | a;
6097 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6098 return 0x300 | a;
6099
6100 a = val & 0xff00;
6101 if (val == ((a << 16) | a))
6102 return 0x200 | (a >> 8);
6103
6104 return FAIL;
6105}
6106/* Encode a VFP SP or DP register number into inst.instruction. */
6107
6108static void
6109encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6110{
6111 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6112 && reg > 15)
6113 {
6114 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
6115 {
6116 if (thumb_mode)
6117 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6118 fpu_vfp_ext_v3);
6119 else
6120 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6121 fpu_vfp_ext_v3);
6122 }
6123 else
6124 {
6125 first_error (_("D register out of range for selected VFP version"));
6126 return;
6127 }
6128 }
6129
6130 switch (pos)
6131 {
6132 case VFP_REG_Sd:
6133 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6134 break;
6135
6136 case VFP_REG_Sn:
6137 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6138 break;
6139
6140 case VFP_REG_Sm:
6141 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6142 break;
6143
6144 case VFP_REG_Dd:
6145 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
6146 break;
6147
6148 case VFP_REG_Dn:
6149 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
6150 break;
6151
6152 case VFP_REG_Dm:
6153 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
6154 break;
6155
6156 default:
6157 abort ();
6158 }
6159}
6160
6161/* Encode a <shift> in an ARM-format instruction. The immediate,
6162 if any, is handled by md_apply_fix. */
6163static void
6164encode_arm_shift (int i)
6165{
6166 if (inst.operands[i].shift_kind == SHIFT_RRX)
6167 inst.instruction |= SHIFT_ROR << 5;
6168 else
6169 {
6170 inst.instruction |= inst.operands[i].shift_kind << 5;
6171 if (inst.operands[i].immisreg)
6172 {
6173 inst.instruction |= SHIFT_BY_REG;
6174 inst.instruction |= inst.operands[i].imm << 8;
6175 }
6176 else
6177 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
6178 }
6179}
6180
6181static void
6182encode_arm_shifter_operand (int i)
6183{
6184 if (inst.operands[i].isreg)
6185 {
6186 inst.instruction |= inst.operands[i].reg;
6187 encode_arm_shift (i);
6188 }
6189 else
6190 inst.instruction |= INST_IMMEDIATE;
6191}
6192
6193/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6194static void
6195encode_arm_addr_mode_common (int i, bfd_boolean is_t)
6196{
6197 assert (inst.operands[i].isreg);
6198 inst.instruction |= inst.operands[i].reg << 16;
6199
6200 if (inst.operands[i].preind)
6201 {
6202 if (is_t)
6203 {
6204 inst.error = _("instruction does not accept preindexed addressing");
6205 return;
6206 }
6207 inst.instruction |= PRE_INDEX;
6208 if (inst.operands[i].writeback)
6209 inst.instruction |= WRITE_BACK;
6210
6211 }
6212 else if (inst.operands[i].postind)
6213 {
6214 assert (inst.operands[i].writeback);
6215 if (is_t)
6216 inst.instruction |= WRITE_BACK;
6217 }
6218 else /* unindexed - only for coprocessor */
6219 {
6220 inst.error = _("instruction does not accept unindexed addressing");
6221 return;
6222 }
6223
6224 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
6225 && (((inst.instruction & 0x000f0000) >> 16)
6226 == ((inst.instruction & 0x0000f000) >> 12)))
6227 as_warn ((inst.instruction & LOAD_BIT)
6228 ? _("destination register same as write-back base")
6229 : _("source register same as write-back base"));
6230}
6231
6232/* inst.operands[i] was set up by parse_address. Encode it into an
6233 ARM-format mode 2 load or store instruction. If is_t is true,
6234 reject forms that cannot be used with a T instruction (i.e. not
6235 post-indexed). */
6236static void
6237encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
6238{
6239 encode_arm_addr_mode_common (i, is_t);
6240
6241 if (inst.operands[i].immisreg)
6242 {
6243 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
6244 inst.instruction |= inst.operands[i].imm;
6245 if (!inst.operands[i].negative)
6246 inst.instruction |= INDEX_UP;
6247 if (inst.operands[i].shifted)
6248 {
6249 if (inst.operands[i].shift_kind == SHIFT_RRX)
6250 inst.instruction |= SHIFT_ROR << 5;
6251 else
6252 {
6253 inst.instruction |= inst.operands[i].shift_kind << 5;
6254 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
6255 }
6256 }
6257 }
6258 else /* immediate offset in inst.reloc */
6259 {
6260 if (inst.reloc.type == BFD_RELOC_UNUSED)
6261 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
6262 }
6263}
6264
6265/* inst.operands[i] was set up by parse_address. Encode it into an
6266 ARM-format mode 3 load or store instruction. Reject forms that
6267 cannot be used with such instructions. If is_t is true, reject
6268 forms that cannot be used with a T instruction (i.e. not
6269 post-indexed). */
6270static void
6271encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
6272{
6273 if (inst.operands[i].immisreg && inst.operands[i].shifted)
6274 {
6275 inst.error = _("instruction does not accept scaled register index");
6276 return;
6277 }
6278
6279 encode_arm_addr_mode_common (i, is_t);
6280
6281 if (inst.operands[i].immisreg)
6282 {
6283 inst.instruction |= inst.operands[i].imm;
6284 if (!inst.operands[i].negative)
6285 inst.instruction |= INDEX_UP;
6286 }
6287 else /* immediate offset in inst.reloc */
6288 {
6289 inst.instruction |= HWOFFSET_IMM;
6290 if (inst.reloc.type == BFD_RELOC_UNUSED)
6291 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
6292 }
6293}
6294
6295/* inst.operands[i] was set up by parse_address. Encode it into an
6296 ARM-format instruction. Reject all forms which cannot be encoded
6297 into a coprocessor load/store instruction. If wb_ok is false,
6298 reject use of writeback; if unind_ok is false, reject use of
6299 unindexed addressing. If reloc_override is not 0, use it instead
6300 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6301 (in which case it is preserved). */
6302
6303static int
6304encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
6305{
6306 inst.instruction |= inst.operands[i].reg << 16;
6307
6308 assert (!(inst.operands[i].preind && inst.operands[i].postind));
6309
6310 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
6311 {
6312 assert (!inst.operands[i].writeback);
6313 if (!unind_ok)
6314 {
6315 inst.error = _("instruction does not support unindexed addressing");
6316 return FAIL;
6317 }
6318 inst.instruction |= inst.operands[i].imm;
6319 inst.instruction |= INDEX_UP;
6320 return SUCCESS;
6321 }
6322
6323 if (inst.operands[i].preind)
6324 inst.instruction |= PRE_INDEX;
6325
6326 if (inst.operands[i].writeback)
6327 {
6328 if (inst.operands[i].reg == REG_PC)
6329 {
6330 inst.error = _("pc may not be used with write-back");
6331 return FAIL;
6332 }
6333 if (!wb_ok)
6334 {
6335 inst.error = _("instruction does not support writeback");
6336 return FAIL;
6337 }
6338 inst.instruction |= WRITE_BACK;
6339 }
6340
6341 if (reloc_override)
6342 inst.reloc.type = reloc_override;
6343 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
6344 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
6345 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
6346 {
6347 if (thumb_mode)
6348 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
6349 else
6350 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
6351 }
6352
6353 return SUCCESS;
6354}
6355
6356/* inst.reloc.exp describes an "=expr" load pseudo-operation.
6357 Determine whether it can be performed with a move instruction; if
6358 it can, convert inst.instruction to that move instruction and
6359 return 1; if it can't, convert inst.instruction to a literal-pool
6360 load and return 0. If this is not a valid thing to do in the
6361 current context, set inst.error and return 1.
6362
6363 inst.operands[i] describes the destination register. */
6364
6365static int
6366move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
6367{
6368 unsigned long tbit;
6369
6370 if (thumb_p)
6371 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
6372 else
6373 tbit = LOAD_BIT;
6374
6375 if ((inst.instruction & tbit) == 0)
6376 {
6377 inst.error = _("invalid pseudo operation");
6378 return 1;
6379 }
6380 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
6381 {
6382 inst.error = _("constant expression expected");
6383 return 1;
6384 }
6385 if (inst.reloc.exp.X_op == O_constant)
6386 {
6387 if (thumb_p)
6388 {
6389 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
6390 {
6391 /* This can be done with a mov(1) instruction. */
6392 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
6393 inst.instruction |= inst.reloc.exp.X_add_number;
6394 return 1;
6395 }
6396 }
6397 else
6398 {
6399 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
6400 if (value != FAIL)
6401 {
6402 /* This can be done with a mov instruction. */
6403 inst.instruction &= LITERAL_MASK;
6404 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
6405 inst.instruction |= value & 0xfff;
6406 return 1;
6407 }
6408
6409 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
6410 if (value != FAIL)
6411 {
6412 /* This can be done with a mvn instruction. */
6413 inst.instruction &= LITERAL_MASK;
6414 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
6415 inst.instruction |= value & 0xfff;
6416 return 1;
6417 }
6418 }
6419 }
6420
6421 if (add_to_lit_pool () == FAIL)
6422 {
6423 inst.error = _("literal pool insertion failed");
6424 return 1;
6425 }
6426 inst.operands[1].reg = REG_PC;
6427 inst.operands[1].isreg = 1;
6428 inst.operands[1].preind = 1;
6429 inst.reloc.pc_rel = 1;
6430 inst.reloc.type = (thumb_p
6431 ? BFD_RELOC_ARM_THUMB_OFFSET
6432 : (mode_3
6433 ? BFD_RELOC_ARM_HWLITERAL
6434 : BFD_RELOC_ARM_LITERAL));
6435 return 0;
6436}
6437
6438/* Functions for instruction encoding, sorted by subarchitecture.
6439 First some generics; their names are taken from the conventional
6440 bit positions for register arguments in ARM format instructions. */
6441
6442static void
6443do_noargs (void)
6444{
6445}
6446
6447static void
6448do_rd (void)
6449{
6450 inst.instruction |= inst.operands[0].reg << 12;
6451}
6452
6453static void
6454do_rd_rm (void)
6455{
6456 inst.instruction |= inst.operands[0].reg << 12;
6457 inst.instruction |= inst.operands[1].reg;
6458}
6459
6460static void
6461do_rd_rn (void)
6462{
6463 inst.instruction |= inst.operands[0].reg << 12;
6464 inst.instruction |= inst.operands[1].reg << 16;
6465}
6466
6467static void
6468do_rn_rd (void)
6469{
6470 inst.instruction |= inst.operands[0].reg << 16;
6471 inst.instruction |= inst.operands[1].reg << 12;
6472}
6473
6474static void
6475do_rd_rm_rn (void)
6476{
6477 unsigned Rn = inst.operands[2].reg;
6478 /* Enforce restrictions on SWP instruction. */
6479 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
6480 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
6481 _("Rn must not overlap other operands"));
6482 inst.instruction |= inst.operands[0].reg << 12;
6483 inst.instruction |= inst.operands[1].reg;
6484 inst.instruction |= Rn << 16;
6485}
6486
6487static void
6488do_rd_rn_rm (void)
6489{
6490 inst.instruction |= inst.operands[0].reg << 12;
6491 inst.instruction |= inst.operands[1].reg << 16;
6492 inst.instruction |= inst.operands[2].reg;
6493}
6494
6495static void
6496do_rm_rd_rn (void)
6497{
6498 inst.instruction |= inst.operands[0].reg;
6499 inst.instruction |= inst.operands[1].reg << 12;
6500 inst.instruction |= inst.operands[2].reg << 16;
6501}
6502
6503static void
6504do_imm0 (void)
6505{
6506 inst.instruction |= inst.operands[0].imm;
6507}
6508
6509static void
6510do_rd_cpaddr (void)
6511{
6512 inst.instruction |= inst.operands[0].reg << 12;
6513 encode_arm_cp_address (1, TRUE, TRUE, 0);
6514}
6515
6516/* ARM instructions, in alphabetical order by function name (except
6517 that wrapper functions appear immediately after the function they
6518 wrap). */
6519
6520/* This is a pseudo-op of the form "adr rd, label" to be converted
6521 into a relative address of the form "add rd, pc, #label-.-8". */
6522
6523static void
6524do_adr (void)
6525{
6526 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
6527
6528 /* Frag hacking will turn this into a sub instruction if the offset turns
6529 out to be negative. */
6530 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
6531 inst.reloc.pc_rel = 1;
6532 inst.reloc.exp.X_add_number -= 8;
6533}
6534
6535/* This is a pseudo-op of the form "adrl rd, label" to be converted
6536 into a relative address of the form:
6537 add rd, pc, #low(label-.-8)"
6538 add rd, rd, #high(label-.-8)" */
6539
6540static void
6541do_adrl (void)
6542{
6543 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
6544
6545 /* Frag hacking will turn this into a sub instruction if the offset turns
6546 out to be negative. */
6547 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
6548 inst.reloc.pc_rel = 1;
6549 inst.size = INSN_SIZE * 2;
6550 inst.reloc.exp.X_add_number -= 8;
6551}
6552
6553static void
6554do_arit (void)
6555{
6556 if (!inst.operands[1].present)
6557 inst.operands[1].reg = inst.operands[0].reg;
6558 inst.instruction |= inst.operands[0].reg << 12;
6559 inst.instruction |= inst.operands[1].reg << 16;
6560 encode_arm_shifter_operand (2);
6561}
6562
6563static void
6564do_barrier (void)
6565{
6566 if (inst.operands[0].present)
6567 {
6568 constraint ((inst.instruction & 0xf0) != 0x40
6569 && inst.operands[0].imm != 0xf,
6570 "bad barrier type");
6571 inst.instruction |= inst.operands[0].imm;
6572 }
6573 else
6574 inst.instruction |= 0xf;
6575}
6576
6577static void
6578do_bfc (void)
6579{
6580 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
6581 constraint (msb > 32, _("bit-field extends past end of register"));
6582 /* The instruction encoding stores the LSB and MSB,
6583 not the LSB and width. */
6584 inst.instruction |= inst.operands[0].reg << 12;
6585 inst.instruction |= inst.operands[1].imm << 7;
6586 inst.instruction |= (msb - 1) << 16;
6587}
6588
6589static void
6590do_bfi (void)
6591{
6592 unsigned int msb;
6593
6594 /* #0 in second position is alternative syntax for bfc, which is
6595 the same instruction but with REG_PC in the Rm field. */
6596 if (!inst.operands[1].isreg)
6597 inst.operands[1].reg = REG_PC;
6598
6599 msb = inst.operands[2].imm + inst.operands[3].imm;
6600 constraint (msb > 32, _("bit-field extends past end of register"));
6601 /* The instruction encoding stores the LSB and MSB,
6602 not the LSB and width. */
6603 inst.instruction |= inst.operands[0].reg << 12;
6604 inst.instruction |= inst.operands[1].reg;
6605 inst.instruction |= inst.operands[2].imm << 7;
6606 inst.instruction |= (msb - 1) << 16;
6607}
6608
6609static void
6610do_bfx (void)
6611{
6612 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
6613 _("bit-field extends past end of register"));
6614 inst.instruction |= inst.operands[0].reg << 12;
6615 inst.instruction |= inst.operands[1].reg;
6616 inst.instruction |= inst.operands[2].imm << 7;
6617 inst.instruction |= (inst.operands[3].imm - 1) << 16;
6618}
6619
6620/* ARM V5 breakpoint instruction (argument parse)
6621 BKPT <16 bit unsigned immediate>
6622 Instruction is not conditional.
6623 The bit pattern given in insns[] has the COND_ALWAYS condition,
6624 and it is an error if the caller tried to override that. */
6625
6626static void
6627do_bkpt (void)
6628{
6629 /* Top 12 of 16 bits to bits 19:8. */
6630 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
6631
6632 /* Bottom 4 of 16 bits to bits 3:0. */
6633 inst.instruction |= inst.operands[0].imm & 0xf;
6634}
6635
6636static void
6637encode_branch (int default_reloc)
6638{
6639 if (inst.operands[0].hasreloc)
6640 {
6641 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
6642 _("the only suffix valid here is '(plt)'"));
6643 inst.reloc.type = BFD_RELOC_ARM_PLT32;
6644 }
6645 else
6646 {
6647 inst.reloc.type = default_reloc;
6648 }
6649 inst.reloc.pc_rel = 1;
6650}
6651
6652static void
6653do_branch (void)
6654{
6655#ifdef OBJ_ELF
6656 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6657 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
6658 else
6659#endif
6660 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
6661}
6662
6663static void
6664do_bl (void)
6665{
6666#ifdef OBJ_ELF
6667 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6668 {
6669 if (inst.cond == COND_ALWAYS)
6670 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
6671 else
6672 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
6673 }
6674 else
6675#endif
6676 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
6677}
6678
6679/* ARM V5 branch-link-exchange instruction (argument parse)
6680 BLX <target_addr> ie BLX(1)
6681 BLX{<condition>} <Rm> ie BLX(2)
6682 Unfortunately, there are two different opcodes for this mnemonic.
6683 So, the insns[].value is not used, and the code here zaps values
6684 into inst.instruction.
6685 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6686
6687static void
6688do_blx (void)
6689{
6690 if (inst.operands[0].isreg)
6691 {
6692 /* Arg is a register; the opcode provided by insns[] is correct.
6693 It is not illegal to do "blx pc", just useless. */
6694 if (inst.operands[0].reg == REG_PC)
6695 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6696
6697 inst.instruction |= inst.operands[0].reg;
6698 }
6699 else
6700 {
6701 /* Arg is an address; this instruction cannot be executed
6702 conditionally, and the opcode must be adjusted. */
6703 constraint (inst.cond != COND_ALWAYS, BAD_COND);
6704 inst.instruction = 0xfa000000;
6705#ifdef OBJ_ELF
6706 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6707 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
6708 else
6709#endif
6710 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
6711 }
6712}
6713
6714static void
6715do_bx (void)
6716{
6717 if (inst.operands[0].reg == REG_PC)
6718 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6719
6720 inst.instruction |= inst.operands[0].reg;
6721}
6722
6723
6724/* ARM v5TEJ. Jump to Jazelle code. */
6725
6726static void
6727do_bxj (void)
6728{
6729 if (inst.operands[0].reg == REG_PC)
6730 as_tsktsk (_("use of r15 in bxj is not really useful"));
6731
6732 inst.instruction |= inst.operands[0].reg;
6733}
6734
6735/* Co-processor data operation:
6736 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6737 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6738static void
6739do_cdp (void)
6740{
6741 inst.instruction |= inst.operands[0].reg << 8;
6742 inst.instruction |= inst.operands[1].imm << 20;
6743 inst.instruction |= inst.operands[2].reg << 12;
6744 inst.instruction |= inst.operands[3].reg << 16;
6745 inst.instruction |= inst.operands[4].reg;
6746 inst.instruction |= inst.operands[5].imm << 5;
6747}
6748
6749static void
6750do_cmp (void)
6751{
6752 inst.instruction |= inst.operands[0].reg << 16;
6753 encode_arm_shifter_operand (1);
6754}
6755
6756/* Transfer between coprocessor and ARM registers.
6757 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6758 MRC2
6759 MCR{cond}
6760 MCR2
6761
6762 No special properties. */
6763
6764static void
6765do_co_reg (void)
6766{
6767 inst.instruction |= inst.operands[0].reg << 8;
6768 inst.instruction |= inst.operands[1].imm << 21;
6769 inst.instruction |= inst.operands[2].reg << 12;
6770 inst.instruction |= inst.operands[3].reg << 16;
6771 inst.instruction |= inst.operands[4].reg;
6772 inst.instruction |= inst.operands[5].imm << 5;
6773}
6774
6775/* Transfer between coprocessor register and pair of ARM registers.
6776 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6777 MCRR2
6778 MRRC{cond}
6779 MRRC2
6780
6781 Two XScale instructions are special cases of these:
6782
6783 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6784 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6785
6786 Result unpredicatable if Rd or Rn is R15. */
6787
6788static void
6789do_co_reg2c (void)
6790{
6791 inst.instruction |= inst.operands[0].reg << 8;
6792 inst.instruction |= inst.operands[1].imm << 4;
6793 inst.instruction |= inst.operands[2].reg << 12;
6794 inst.instruction |= inst.operands[3].reg << 16;
6795 inst.instruction |= inst.operands[4].reg;
6796}
6797
6798static void
6799do_cpsi (void)
6800{
6801 inst.instruction |= inst.operands[0].imm << 6;
6802 if (inst.operands[1].present)
6803 {
6804 inst.instruction |= CPSI_MMOD;
6805 inst.instruction |= inst.operands[1].imm;
6806 }
6807}
6808
6809static void
6810do_dbg (void)
6811{
6812 inst.instruction |= inst.operands[0].imm;
6813}
6814
6815static void
6816do_it (void)
6817{
6818 /* There is no IT instruction in ARM mode. We
6819 process it but do not generate code for it. */
6820 inst.size = 0;
6821}
6822
6823static void
6824do_ldmstm (void)
6825{
6826 int base_reg = inst.operands[0].reg;
6827 int range = inst.operands[1].imm;
6828
6829 inst.instruction |= base_reg << 16;
6830 inst.instruction |= range;
6831
6832 if (inst.operands[1].writeback)
6833 inst.instruction |= LDM_TYPE_2_OR_3;
6834
6835 if (inst.operands[0].writeback)
6836 {
6837 inst.instruction |= WRITE_BACK;
6838 /* Check for unpredictable uses of writeback. */
6839 if (inst.instruction & LOAD_BIT)
6840 {
6841 /* Not allowed in LDM type 2. */
6842 if ((inst.instruction & LDM_TYPE_2_OR_3)
6843 && ((range & (1 << REG_PC)) == 0))
6844 as_warn (_("writeback of base register is UNPREDICTABLE"));
6845 /* Only allowed if base reg not in list for other types. */
6846 else if (range & (1 << base_reg))
6847 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6848 }
6849 else /* STM. */
6850 {
6851 /* Not allowed for type 2. */
6852 if (inst.instruction & LDM_TYPE_2_OR_3)
6853 as_warn (_("writeback of base register is UNPREDICTABLE"));
6854 /* Only allowed if base reg not in list, or first in list. */
6855 else if ((range & (1 << base_reg))
6856 && (range & ((1 << base_reg) - 1)))
6857 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6858 }
6859 }
6860}
6861
6862/* ARMv5TE load-consecutive (argument parse)
6863 Mode is like LDRH.
6864
6865 LDRccD R, mode
6866 STRccD R, mode. */
6867
6868static void
6869do_ldrd (void)
6870{
6871 constraint (inst.operands[0].reg % 2 != 0,
6872 _("first destination register must be even"));
6873 constraint (inst.operands[1].present
6874 && inst.operands[1].reg != inst.operands[0].reg + 1,
6875 _("can only load two consecutive registers"));
6876 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
6877 constraint (!inst.operands[2].isreg, _("'[' expected"));
6878
6879 if (!inst.operands[1].present)
6880 inst.operands[1].reg = inst.operands[0].reg + 1;
6881
6882 if (inst.instruction & LOAD_BIT)
6883 {
6884 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6885 register and the first register written; we have to diagnose
6886 overlap between the base and the second register written here. */
6887
6888 if (inst.operands[2].reg == inst.operands[1].reg
6889 && (inst.operands[2].writeback || inst.operands[2].postind))
6890 as_warn (_("base register written back, and overlaps "
6891 "second destination register"));
6892
6893 /* For an index-register load, the index register must not overlap the
6894 destination (even if not write-back). */
6895 else if (inst.operands[2].immisreg
6896 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
6897 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
6898 as_warn (_("index register overlaps destination register"));
6899 }
6900
6901 inst.instruction |= inst.operands[0].reg << 12;
6902 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
6903}
6904
6905static void
6906do_ldrex (void)
6907{
6908 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
6909 || inst.operands[1].postind || inst.operands[1].writeback
6910 || inst.operands[1].immisreg || inst.operands[1].shifted
6911 || inst.operands[1].negative
6912 /* This can arise if the programmer has written
6913 strex rN, rM, foo
6914 or if they have mistakenly used a register name as the last
6915 operand, eg:
6916 strex rN, rM, rX
6917 It is very difficult to distinguish between these two cases
6918 because "rX" might actually be a label. ie the register
6919 name has been occluded by a symbol of the same name. So we
6920 just generate a general 'bad addressing mode' type error
6921 message and leave it up to the programmer to discover the
6922 true cause and fix their mistake. */
6923 || (inst.operands[1].reg == REG_PC),
6924 BAD_ADDR_MODE);
6925
6926 constraint (inst.reloc.exp.X_op != O_constant
6927 || inst.reloc.exp.X_add_number != 0,
6928 _("offset must be zero in ARM encoding"));
6929
6930 inst.instruction |= inst.operands[0].reg << 12;
6931 inst.instruction |= inst.operands[1].reg << 16;
6932 inst.reloc.type = BFD_RELOC_UNUSED;
6933}
6934
6935static void
6936do_ldrexd (void)
6937{
6938 constraint (inst.operands[0].reg % 2 != 0,
6939 _("even register required"));
6940 constraint (inst.operands[1].present
6941 && inst.operands[1].reg != inst.operands[0].reg + 1,
6942 _("can only load two consecutive registers"));
6943 /* If op 1 were present and equal to PC, this function wouldn't
6944 have been called in the first place. */
6945 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
6946
6947 inst.instruction |= inst.operands[0].reg << 12;
6948 inst.instruction |= inst.operands[2].reg << 16;
6949}
6950
6951static void
6952do_ldst (void)
6953{
6954 inst.instruction |= inst.operands[0].reg << 12;
6955 if (!inst.operands[1].isreg)
6956 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
6957 return;
6958 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
6959}
6960
6961static void
6962do_ldstt (void)
6963{
6964 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6965 reject [Rn,...]. */
6966 if (inst.operands[1].preind)
6967 {
6968 constraint (inst.reloc.exp.X_op != O_constant ||
6969 inst.reloc.exp.X_add_number != 0,
6970 _("this instruction requires a post-indexed address"));
6971
6972 inst.operands[1].preind = 0;
6973 inst.operands[1].postind = 1;
6974 inst.operands[1].writeback = 1;
6975 }
6976 inst.instruction |= inst.operands[0].reg << 12;
6977 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
6978}
6979
6980/* Halfword and signed-byte load/store operations. */
6981
6982static void
6983do_ldstv4 (void)
6984{
6985 inst.instruction |= inst.operands[0].reg << 12;
6986 if (!inst.operands[1].isreg)
6987 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
6988 return;
6989 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
6990}
6991
6992static void
6993do_ldsttv4 (void)
6994{
6995 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6996 reject [Rn,...]. */
6997 if (inst.operands[1].preind)
6998 {
6999 constraint (inst.reloc.exp.X_op != O_constant ||
7000 inst.reloc.exp.X_add_number != 0,
7001 _("this instruction requires a post-indexed address"));
7002
7003 inst.operands[1].preind = 0;
7004 inst.operands[1].postind = 1;
7005 inst.operands[1].writeback = 1;
7006 }
7007 inst.instruction |= inst.operands[0].reg << 12;
7008 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
7009}
7010
7011/* Co-processor register load/store.
7012 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7013static void
7014do_lstc (void)
7015{
7016 inst.instruction |= inst.operands[0].reg << 8;
7017 inst.instruction |= inst.operands[1].reg << 12;
7018 encode_arm_cp_address (2, TRUE, TRUE, 0);
7019}
7020
7021static void
7022do_mlas (void)
7023{
7024 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7025 if (inst.operands[0].reg == inst.operands[1].reg
7026 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
7027 && !(inst.instruction & 0x00400000))
7028 as_tsktsk (_("Rd and Rm should be different in mla"));
7029
7030 inst.instruction |= inst.operands[0].reg << 16;
7031 inst.instruction |= inst.operands[1].reg;
7032 inst.instruction |= inst.operands[2].reg << 8;
7033 inst.instruction |= inst.operands[3].reg << 12;
7034}
7035
7036static void
7037do_mov (void)
7038{
7039 inst.instruction |= inst.operands[0].reg << 12;
7040 encode_arm_shifter_operand (1);
7041}
7042
7043/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7044static void
7045do_mov16 (void)
7046{
7047 bfd_vma imm;
7048 bfd_boolean top;
7049
7050 top = (inst.instruction & 0x00400000) != 0;
7051 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
7052 _(":lower16: not allowed this instruction"));
7053 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
7054 _(":upper16: not allowed instruction"));
7055 inst.instruction |= inst.operands[0].reg << 12;
7056 if (inst.reloc.type == BFD_RELOC_UNUSED)
7057 {
7058 imm = inst.reloc.exp.X_add_number;
7059 /* The value is in two pieces: 0:11, 16:19. */
7060 inst.instruction |= (imm & 0x00000fff);
7061 inst.instruction |= (imm & 0x0000f000) << 4;
7062 }
7063}
7064
7065static void do_vfp_nsyn_opcode (const char *);
7066
7067static int
7068do_vfp_nsyn_mrs (void)
7069{
7070 if (inst.operands[0].isvec)
7071 {
7072 if (inst.operands[1].reg != 1)
7073 first_error (_("operand 1 must be FPSCR"));
7074 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
7075 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
7076 do_vfp_nsyn_opcode ("fmstat");
7077 }
7078 else if (inst.operands[1].isvec)
7079 do_vfp_nsyn_opcode ("fmrx");
7080 else
7081 return FAIL;
7082
7083 return SUCCESS;
7084}
7085
7086static int
7087do_vfp_nsyn_msr (void)
7088{
7089 if (inst.operands[0].isvec)
7090 do_vfp_nsyn_opcode ("fmxr");
7091 else
7092 return FAIL;
7093
7094 return SUCCESS;
7095}
7096
7097static void
7098do_mrs (void)
7099{
7100 if (do_vfp_nsyn_mrs () == SUCCESS)
7101 return;
7102
7103 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7104 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
7105 != (PSR_c|PSR_f),
7106 _("'CPSR' or 'SPSR' expected"));
7107 inst.instruction |= inst.operands[0].reg << 12;
7108 inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
7109}
7110
7111/* Two possible forms:
7112 "{C|S}PSR_<field>, Rm",
7113 "{C|S}PSR_f, #expression". */
7114
7115static void
7116do_msr (void)
7117{
7118 if (do_vfp_nsyn_msr () == SUCCESS)
7119 return;
7120
7121 inst.instruction |= inst.operands[0].imm;
7122 if (inst.operands[1].isreg)
7123 inst.instruction |= inst.operands[1].reg;
7124 else
7125 {
7126 inst.instruction |= INST_IMMEDIATE;
7127 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7128 inst.reloc.pc_rel = 0;
7129 }
7130}
7131
7132static void
7133do_mul (void)
7134{
7135 if (!inst.operands[2].present)
7136 inst.operands[2].reg = inst.operands[0].reg;
7137 inst.instruction |= inst.operands[0].reg << 16;
7138 inst.instruction |= inst.operands[1].reg;
7139 inst.instruction |= inst.operands[2].reg << 8;
7140
7141 if (inst.operands[0].reg == inst.operands[1].reg
7142 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
7143 as_tsktsk (_("Rd and Rm should be different in mul"));
7144}
7145
7146/* Long Multiply Parser
7147 UMULL RdLo, RdHi, Rm, Rs
7148 SMULL RdLo, RdHi, Rm, Rs
7149 UMLAL RdLo, RdHi, Rm, Rs
7150 SMLAL RdLo, RdHi, Rm, Rs. */
7151
7152static void
7153do_mull (void)
7154{
7155 inst.instruction |= inst.operands[0].reg << 12;
7156 inst.instruction |= inst.operands[1].reg << 16;
7157 inst.instruction |= inst.operands[2].reg;
7158 inst.instruction |= inst.operands[3].reg << 8;
7159
7160 /* rdhi, rdlo and rm must all be different. */
7161 if (inst.operands[0].reg == inst.operands[1].reg
7162 || inst.operands[0].reg == inst.operands[2].reg
7163 || inst.operands[1].reg == inst.operands[2].reg)
7164 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7165}
7166
7167static void
7168do_nop (void)
7169{
7170 if (inst.operands[0].present)
7171 {
7172 /* Architectural NOP hints are CPSR sets with no bits selected. */
7173 inst.instruction &= 0xf0000000;
7174 inst.instruction |= 0x0320f000 + inst.operands[0].imm;
7175 }
7176}
7177
7178/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7179 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7180 Condition defaults to COND_ALWAYS.
7181 Error if Rd, Rn or Rm are R15. */
7182
7183static void
7184do_pkhbt (void)
7185{
7186 inst.instruction |= inst.operands[0].reg << 12;
7187 inst.instruction |= inst.operands[1].reg << 16;
7188 inst.instruction |= inst.operands[2].reg;
7189 if (inst.operands[3].present)
7190 encode_arm_shift (3);
7191}
7192
7193/* ARM V6 PKHTB (Argument Parse). */
7194
7195static void
7196do_pkhtb (void)
7197{
7198 if (!inst.operands[3].present)
7199 {
7200 /* If the shift specifier is omitted, turn the instruction
7201 into pkhbt rd, rm, rn. */
7202 inst.instruction &= 0xfff00010;
7203 inst.instruction |= inst.operands[0].reg << 12;
7204 inst.instruction |= inst.operands[1].reg;
7205 inst.instruction |= inst.operands[2].reg << 16;
7206 }
7207 else
7208 {
7209 inst.instruction |= inst.operands[0].reg << 12;
7210 inst.instruction |= inst.operands[1].reg << 16;
7211 inst.instruction |= inst.operands[2].reg;
7212 encode_arm_shift (3);
7213 }
7214}
7215
7216/* ARMv5TE: Preload-Cache
7217
7218 PLD <addr_mode>
7219
7220 Syntactically, like LDR with B=1, W=0, L=1. */
7221
7222static void
7223do_pld (void)
7224{
7225 constraint (!inst.operands[0].isreg,
7226 _("'[' expected after PLD mnemonic"));
7227 constraint (inst.operands[0].postind,
7228 _("post-indexed expression used in preload instruction"));
7229 constraint (inst.operands[0].writeback,
7230 _("writeback used in preload instruction"));
7231 constraint (!inst.operands[0].preind,
7232 _("unindexed addressing used in preload instruction"));
7233 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
7234}
7235
7236/* ARMv7: PLI <addr_mode> */
7237static void
7238do_pli (void)
7239{
7240 constraint (!inst.operands[0].isreg,
7241 _("'[' expected after PLI mnemonic"));
7242 constraint (inst.operands[0].postind,
7243 _("post-indexed expression used in preload instruction"));
7244 constraint (inst.operands[0].writeback,
7245 _("writeback used in preload instruction"));
7246 constraint (!inst.operands[0].preind,
7247 _("unindexed addressing used in preload instruction"));
7248 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
7249 inst.instruction &= ~PRE_INDEX;
7250}
7251
7252static void
7253do_push_pop (void)
7254{
7255 inst.operands[1] = inst.operands[0];
7256 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
7257 inst.operands[0].isreg = 1;
7258 inst.operands[0].writeback = 1;
7259 inst.operands[0].reg = REG_SP;
7260 do_ldmstm ();
7261}
7262
7263/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7264 word at the specified address and the following word
7265 respectively.
7266 Unconditionally executed.
7267 Error if Rn is R15. */
7268
7269static void
7270do_rfe (void)
7271{
7272 inst.instruction |= inst.operands[0].reg << 16;
7273 if (inst.operands[0].writeback)
7274 inst.instruction |= WRITE_BACK;
7275}
7276
7277/* ARM V6 ssat (argument parse). */
7278
7279static void
7280do_ssat (void)
7281{
7282 inst.instruction |= inst.operands[0].reg << 12;
7283 inst.instruction |= (inst.operands[1].imm - 1) << 16;
7284 inst.instruction |= inst.operands[2].reg;
7285
7286 if (inst.operands[3].present)
7287 encode_arm_shift (3);
7288}
7289
7290/* ARM V6 usat (argument parse). */
7291
7292static void
7293do_usat (void)
7294{
7295 inst.instruction |= inst.operands[0].reg << 12;
7296 inst.instruction |= inst.operands[1].imm << 16;
7297 inst.instruction |= inst.operands[2].reg;
7298
7299 if (inst.operands[3].present)
7300 encode_arm_shift (3);
7301}
7302
7303/* ARM V6 ssat16 (argument parse). */
7304
7305static void
7306do_ssat16 (void)
7307{
7308 inst.instruction |= inst.operands[0].reg << 12;
7309 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
7310 inst.instruction |= inst.operands[2].reg;
7311}
7312
7313static void
7314do_usat16 (void)
7315{
7316 inst.instruction |= inst.operands[0].reg << 12;
7317 inst.instruction |= inst.operands[1].imm << 16;
7318 inst.instruction |= inst.operands[2].reg;
7319}
7320
7321/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7322 preserving the other bits.
7323
7324 setend <endian_specifier>, where <endian_specifier> is either
7325 BE or LE. */
7326
7327static void
7328do_setend (void)
7329{
7330 if (inst.operands[0].imm)
7331 inst.instruction |= 0x200;
7332}
7333
7334static void
7335do_shift (void)
7336{
7337 unsigned int Rm = (inst.operands[1].present
7338 ? inst.operands[1].reg
7339 : inst.operands[0].reg);
7340
7341 inst.instruction |= inst.operands[0].reg << 12;
7342 inst.instruction |= Rm;
7343 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
7344 {
7345 inst.instruction |= inst.operands[2].reg << 8;
7346 inst.instruction |= SHIFT_BY_REG;
7347 }
7348 else
7349 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7350}
7351
7352static void
7353do_smc (void)
7354{
7355 inst.reloc.type = BFD_RELOC_ARM_SMC;
7356 inst.reloc.pc_rel = 0;
7357}
7358
7359static void
7360do_swi (void)
7361{
7362 inst.reloc.type = BFD_RELOC_ARM_SWI;
7363 inst.reloc.pc_rel = 0;
7364}
7365
7366/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7367 SMLAxy{cond} Rd,Rm,Rs,Rn
7368 SMLAWy{cond} Rd,Rm,Rs,Rn
7369 Error if any register is R15. */
7370
7371static void
7372do_smla (void)
7373{
7374 inst.instruction |= inst.operands[0].reg << 16;
7375 inst.instruction |= inst.operands[1].reg;
7376 inst.instruction |= inst.operands[2].reg << 8;
7377 inst.instruction |= inst.operands[3].reg << 12;
7378}
7379
7380/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7381 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7382 Error if any register is R15.
7383 Warning if Rdlo == Rdhi. */
7384
7385static void
7386do_smlal (void)
7387{
7388 inst.instruction |= inst.operands[0].reg << 12;
7389 inst.instruction |= inst.operands[1].reg << 16;
7390 inst.instruction |= inst.operands[2].reg;
7391 inst.instruction |= inst.operands[3].reg << 8;
7392
7393 if (inst.operands[0].reg == inst.operands[1].reg)
7394 as_tsktsk (_("rdhi and rdlo must be different"));
7395}
7396
7397/* ARM V5E (El Segundo) signed-multiply (argument parse)
7398 SMULxy{cond} Rd,Rm,Rs
7399 Error if any register is R15. */
7400
7401static void
7402do_smul (void)
7403{
7404 inst.instruction |= inst.operands[0].reg << 16;
7405 inst.instruction |= inst.operands[1].reg;
7406 inst.instruction |= inst.operands[2].reg << 8;
7407}
7408
7409/* ARM V6 srs (argument parse). The variable fields in the encoding are
7410 the same for both ARM and Thumb-2. */
7411
7412static void
7413do_srs (void)
7414{
7415 int reg;
7416
7417 if (inst.operands[0].present)
7418 {
7419 reg = inst.operands[0].reg;
7420 constraint (reg != 13, _("SRS base register must be r13"));
7421 }
7422 else
7423 reg = 13;
7424
7425 inst.instruction |= reg << 16;
7426 inst.instruction |= inst.operands[1].imm;
7427 if (inst.operands[0].writeback || inst.operands[1].writeback)
7428 inst.instruction |= WRITE_BACK;
7429}
7430
7431/* ARM V6 strex (argument parse). */
7432
7433static void
7434do_strex (void)
7435{
7436 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
7437 || inst.operands[2].postind || inst.operands[2].writeback
7438 || inst.operands[2].immisreg || inst.operands[2].shifted
7439 || inst.operands[2].negative
7440 /* See comment in do_ldrex(). */
7441 || (inst.operands[2].reg == REG_PC),
7442 BAD_ADDR_MODE);
7443
7444 constraint (inst.operands[0].reg == inst.operands[1].reg
7445 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
7446
7447 constraint (inst.reloc.exp.X_op != O_constant
7448 || inst.reloc.exp.X_add_number != 0,
7449 _("offset must be zero in ARM encoding"));
7450
7451 inst.instruction |= inst.operands[0].reg << 12;
7452 inst.instruction |= inst.operands[1].reg;
7453 inst.instruction |= inst.operands[2].reg << 16;
7454 inst.reloc.type = BFD_RELOC_UNUSED;
7455}
7456
7457static void
7458do_strexd (void)
7459{
7460 constraint (inst.operands[1].reg % 2 != 0,
7461 _("even register required"));
7462 constraint (inst.operands[2].present
7463 && inst.operands[2].reg != inst.operands[1].reg + 1,
7464 _("can only store two consecutive registers"));
7465 /* If op 2 were present and equal to PC, this function wouldn't
7466 have been called in the first place. */
7467 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
7468
7469 constraint (inst.operands[0].reg == inst.operands[1].reg
7470 || inst.operands[0].reg == inst.operands[1].reg + 1
7471 || inst.operands[0].reg == inst.operands[3].reg,
7472 BAD_OVERLAP);
7473
7474 inst.instruction |= inst.operands[0].reg << 12;
7475 inst.instruction |= inst.operands[1].reg;
7476 inst.instruction |= inst.operands[3].reg << 16;
7477}
7478
7479/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7480 extends it to 32-bits, and adds the result to a value in another
7481 register. You can specify a rotation by 0, 8, 16, or 24 bits
7482 before extracting the 16-bit value.
7483 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7484 Condition defaults to COND_ALWAYS.
7485 Error if any register uses R15. */
7486
7487static void
7488do_sxtah (void)
7489{
7490 inst.instruction |= inst.operands[0].reg << 12;
7491 inst.instruction |= inst.operands[1].reg << 16;
7492 inst.instruction |= inst.operands[2].reg;
7493 inst.instruction |= inst.operands[3].imm << 10;
7494}
7495
7496/* ARM V6 SXTH.
7497
7498 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7499 Condition defaults to COND_ALWAYS.
7500 Error if any register uses R15. */
7501
7502static void
7503do_sxth (void)
7504{
7505 inst.instruction |= inst.operands[0].reg << 12;
7506 inst.instruction |= inst.operands[1].reg;
7507 inst.instruction |= inst.operands[2].imm << 10;
7508}
7509
7510/* VFP instructions. In a logical order: SP variant first, monad
7511 before dyad, arithmetic then move then load/store. */
7512
7513static void
7514do_vfp_sp_monadic (void)
7515{
7516 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7517 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
7518}
7519
7520static void
7521do_vfp_sp_dyadic (void)
7522{
7523 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7524 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
7525 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
7526}
7527
7528static void
7529do_vfp_sp_compare_z (void)
7530{
7531 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7532}
7533
7534static void
7535do_vfp_dp_sp_cvt (void)
7536{
7537 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7538 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
7539}
7540
7541static void
7542do_vfp_sp_dp_cvt (void)
7543{
7544 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7545 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
7546}
7547
7548static void
7549do_vfp_reg_from_sp (void)
7550{
7551 inst.instruction |= inst.operands[0].reg << 12;
7552 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
7553}
7554
7555static void
7556do_vfp_reg2_from_sp2 (void)
7557{
7558 constraint (inst.operands[2].imm != 2,
7559 _("only two consecutive VFP SP registers allowed here"));
7560 inst.instruction |= inst.operands[0].reg << 12;
7561 inst.instruction |= inst.operands[1].reg << 16;
7562 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
7563}
7564
7565static void
7566do_vfp_sp_from_reg (void)
7567{
7568 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
7569 inst.instruction |= inst.operands[1].reg << 12;
7570}
7571
7572static void
7573do_vfp_sp2_from_reg2 (void)
7574{
7575 constraint (inst.operands[0].imm != 2,
7576 _("only two consecutive VFP SP registers allowed here"));
7577 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
7578 inst.instruction |= inst.operands[1].reg << 12;
7579 inst.instruction |= inst.operands[2].reg << 16;
7580}
7581
7582static void
7583do_vfp_sp_ldst (void)
7584{
7585 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7586 encode_arm_cp_address (1, FALSE, TRUE, 0);
7587}
7588
7589static void
7590do_vfp_dp_ldst (void)
7591{
7592 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7593 encode_arm_cp_address (1, FALSE, TRUE, 0);
7594}
7595
7596
7597static void
7598vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
7599{
7600 if (inst.operands[0].writeback)
7601 inst.instruction |= WRITE_BACK;
7602 else
7603 constraint (ldstm_type != VFP_LDSTMIA,
7604 _("this addressing mode requires base-register writeback"));
7605 inst.instruction |= inst.operands[0].reg << 16;
7606 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
7607 inst.instruction |= inst.operands[1].imm;
7608}
7609
7610static void
7611vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
7612{
7613 int count;
7614
7615 if (inst.operands[0].writeback)
7616 inst.instruction |= WRITE_BACK;
7617 else
7618 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
7619 _("this addressing mode requires base-register writeback"));
7620
7621 inst.instruction |= inst.operands[0].reg << 16;
7622 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7623
7624 count = inst.operands[1].imm << 1;
7625 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
7626 count += 1;
7627
7628 inst.instruction |= count;
7629}
7630
7631static void
7632do_vfp_sp_ldstmia (void)
7633{
7634 vfp_sp_ldstm (VFP_LDSTMIA);
7635}
7636
7637static void
7638do_vfp_sp_ldstmdb (void)
7639{
7640 vfp_sp_ldstm (VFP_LDSTMDB);
7641}
7642
7643static void
7644do_vfp_dp_ldstmia (void)
7645{
7646 vfp_dp_ldstm (VFP_LDSTMIA);
7647}
7648
7649static void
7650do_vfp_dp_ldstmdb (void)
7651{
7652 vfp_dp_ldstm (VFP_LDSTMDB);
7653}
7654
7655static void
7656do_vfp_xp_ldstmia (void)
7657{
7658 vfp_dp_ldstm (VFP_LDSTMIAX);
7659}
7660
7661static void
7662do_vfp_xp_ldstmdb (void)
7663{
7664 vfp_dp_ldstm (VFP_LDSTMDBX);
7665}
7666
7667static void
7668do_vfp_dp_rd_rm (void)
7669{
7670 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7671 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
7672}
7673
7674static void
7675do_vfp_dp_rn_rd (void)
7676{
7677 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
7678 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7679}
7680
7681static void
7682do_vfp_dp_rd_rn (void)
7683{
7684 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7685 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
7686}
7687
7688static void
7689do_vfp_dp_rd_rn_rm (void)
7690{
7691 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7692 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
7693 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
7694}
7695
7696static void
7697do_vfp_dp_rd (void)
7698{
7699 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7700}
7701
7702static void
7703do_vfp_dp_rm_rd_rn (void)
7704{
7705 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
7706 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7707 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
7708}
7709
7710/* VFPv3 instructions. */
7711static void
7712do_vfp_sp_const (void)
7713{
7714 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7715 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
7716 inst.instruction |= (inst.operands[1].imm & 0x0f);
7717}
7718
7719static void
7720do_vfp_dp_const (void)
7721{
7722 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7723 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
7724 inst.instruction |= (inst.operands[1].imm & 0x0f);
7725}
7726
7727static void
7728vfp_conv (int srcsize)
7729{
7730 unsigned immbits = srcsize - inst.operands[1].imm;
7731 inst.instruction |= (immbits & 1) << 5;
7732 inst.instruction |= (immbits >> 1);
7733}
7734
7735static void
7736do_vfp_sp_conv_16 (void)
7737{
7738 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7739 vfp_conv (16);
7740}
7741
7742static void
7743do_vfp_dp_conv_16 (void)
7744{
7745 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7746 vfp_conv (16);
7747}
7748
7749static void
7750do_vfp_sp_conv_32 (void)
7751{
7752 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7753 vfp_conv (32);
7754}
7755
7756static void
7757do_vfp_dp_conv_32 (void)
7758{
7759 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7760 vfp_conv (32);
7761}
7762
7763
7764/* FPA instructions. Also in a logical order. */
7765
7766static void
7767do_fpa_cmp (void)
7768{
7769 inst.instruction |= inst.operands[0].reg << 16;
7770 inst.instruction |= inst.operands[1].reg;
7771}
7772
7773static void
7774do_fpa_ldmstm (void)
7775{
7776 inst.instruction |= inst.operands[0].reg << 12;
7777 switch (inst.operands[1].imm)
7778 {
7779 case 1: inst.instruction |= CP_T_X; break;
7780 case 2: inst.instruction |= CP_T_Y; break;
7781 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
7782 case 4: break;
7783 default: abort ();
7784 }
7785
7786 if (inst.instruction & (PRE_INDEX | INDEX_UP))
7787 {
7788 /* The instruction specified "ea" or "fd", so we can only accept
7789 [Rn]{!}. The instruction does not really support stacking or
7790 unstacking, so we have to emulate these by setting appropriate
7791 bits and offsets. */
7792 constraint (inst.reloc.exp.X_op != O_constant
7793 || inst.reloc.exp.X_add_number != 0,
7794 _("this instruction does not support indexing"));
7795
7796 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
7797 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
7798
7799 if (!(inst.instruction & INDEX_UP))
7800 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
7801
7802 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
7803 {
7804 inst.operands[2].preind = 0;
7805 inst.operands[2].postind = 1;
7806 }
7807 }
7808
7809 encode_arm_cp_address (2, TRUE, TRUE, 0);
7810}
7811
7812
7813/* iWMMXt instructions: strictly in alphabetical order. */
7814
7815static void
7816do_iwmmxt_tandorc (void)
7817{
7818 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
7819}
7820
7821static void
7822do_iwmmxt_textrc (void)
7823{
7824 inst.instruction |= inst.operands[0].reg << 12;
7825 inst.instruction |= inst.operands[1].imm;
7826}
7827
7828static void
7829do_iwmmxt_textrm (void)
7830{
7831 inst.instruction |= inst.operands[0].reg << 12;
7832 inst.instruction |= inst.operands[1].reg << 16;
7833 inst.instruction |= inst.operands[2].imm;
7834}
7835
7836static void
7837do_iwmmxt_tinsr (void)
7838{
7839 inst.instruction |= inst.operands[0].reg << 16;
7840 inst.instruction |= inst.operands[1].reg << 12;
7841 inst.instruction |= inst.operands[2].imm;
7842}
7843
7844static void
7845do_iwmmxt_tmia (void)
7846{
7847 inst.instruction |= inst.operands[0].reg << 5;
7848 inst.instruction |= inst.operands[1].reg;
7849 inst.instruction |= inst.operands[2].reg << 12;
7850}
7851
7852static void
7853do_iwmmxt_waligni (void)
7854{
7855 inst.instruction |= inst.operands[0].reg << 12;
7856 inst.instruction |= inst.operands[1].reg << 16;
7857 inst.instruction |= inst.operands[2].reg;
7858 inst.instruction |= inst.operands[3].imm << 20;
7859}
7860
7861static void
7862do_iwmmxt_wmerge (void)
7863{
7864 inst.instruction |= inst.operands[0].reg << 12;
7865 inst.instruction |= inst.operands[1].reg << 16;
7866 inst.instruction |= inst.operands[2].reg;
7867 inst.instruction |= inst.operands[3].imm << 21;
7868}
7869
7870static void
7871do_iwmmxt_wmov (void)
7872{
7873 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7874 inst.instruction |= inst.operands[0].reg << 12;
7875 inst.instruction |= inst.operands[1].reg << 16;
7876 inst.instruction |= inst.operands[1].reg;
7877}
7878
7879static void
7880do_iwmmxt_wldstbh (void)
7881{
7882 int reloc;
7883 inst.instruction |= inst.operands[0].reg << 12;
7884 if (thumb_mode)
7885 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
7886 else
7887 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
7888 encode_arm_cp_address (1, TRUE, FALSE, reloc);
7889}
7890
7891static void
7892do_iwmmxt_wldstw (void)
7893{
7894 /* RIWR_RIWC clears .isreg for a control register. */
7895 if (!inst.operands[0].isreg)
7896 {
7897 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7898 inst.instruction |= 0xf0000000;
7899 }
7900
7901 inst.instruction |= inst.operands[0].reg << 12;
7902 encode_arm_cp_address (1, TRUE, TRUE, 0);
7903}
7904
7905static void
7906do_iwmmxt_wldstd (void)
7907{
7908 inst.instruction |= inst.operands[0].reg << 12;
7909 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
7910 && inst.operands[1].immisreg)
7911 {
7912 inst.instruction &= ~0x1a000ff;
7913 inst.instruction |= (0xf << 28);
7914 if (inst.operands[1].preind)
7915 inst.instruction |= PRE_INDEX;
7916 if (!inst.operands[1].negative)
7917 inst.instruction |= INDEX_UP;
7918 if (inst.operands[1].writeback)
7919 inst.instruction |= WRITE_BACK;
7920 inst.instruction |= inst.operands[1].reg << 16;
7921 inst.instruction |= inst.reloc.exp.X_add_number << 4;
7922 inst.instruction |= inst.operands[1].imm;
7923 }
7924 else
7925 encode_arm_cp_address (1, TRUE, FALSE, 0);
7926}
7927
7928static void
7929do_iwmmxt_wshufh (void)
7930{
7931 inst.instruction |= inst.operands[0].reg << 12;
7932 inst.instruction |= inst.operands[1].reg << 16;
7933 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
7934 inst.instruction |= (inst.operands[2].imm & 0x0f);
7935}
7936
7937static void
7938do_iwmmxt_wzero (void)
7939{
7940 /* WZERO reg is an alias for WANDN reg, reg, reg. */
7941 inst.instruction |= inst.operands[0].reg;
7942 inst.instruction |= inst.operands[0].reg << 12;
7943 inst.instruction |= inst.operands[0].reg << 16;
7944}
7945
7946static void
7947do_iwmmxt_wrwrwr_or_imm5 (void)
7948{
7949 if (inst.operands[2].isreg)
7950 do_rd_rn_rm ();
7951 else {
7952 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
7953 _("immediate operand requires iWMMXt2"));
7954 do_rd_rn ();
7955 if (inst.operands[2].imm == 0)
7956 {
7957 switch ((inst.instruction >> 20) & 0xf)
7958 {
7959 case 4:
7960 case 5:
7961 case 6:
7962 case 7:
7963 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
7964 inst.operands[2].imm = 16;
7965 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
7966 break;
7967 case 8:
7968 case 9:
7969 case 10:
7970 case 11:
7971 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
7972 inst.operands[2].imm = 32;
7973 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
7974 break;
7975 case 12:
7976 case 13:
7977 case 14:
7978 case 15:
7979 {
7980 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
7981 unsigned long wrn;
7982 wrn = (inst.instruction >> 16) & 0xf;
7983 inst.instruction &= 0xff0fff0f;
7984 inst.instruction |= wrn;
7985 /* Bail out here; the instruction is now assembled. */
7986 return;
7987 }
7988 }
7989 }
7990 /* Map 32 -> 0, etc. */
7991 inst.operands[2].imm &= 0x1f;
7992 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
7993 }
7994}
7995
7996/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
7997 operations first, then control, shift, and load/store. */
7998
7999/* Insns like "foo X,Y,Z". */
8000
8001static void
8002do_mav_triple (void)
8003{
8004 inst.instruction |= inst.operands[0].reg << 16;
8005 inst.instruction |= inst.operands[1].reg;
8006 inst.instruction |= inst.operands[2].reg << 12;
8007}
8008
8009/* Insns like "foo W,X,Y,Z".
8010 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8011
8012static void
8013do_mav_quad (void)
8014{
8015 inst.instruction |= inst.operands[0].reg << 5;
8016 inst.instruction |= inst.operands[1].reg << 12;
8017 inst.instruction |= inst.operands[2].reg << 16;
8018 inst.instruction |= inst.operands[3].reg;
8019}
8020
8021/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8022static void
8023do_mav_dspsc (void)
8024{
8025 inst.instruction |= inst.operands[1].reg << 12;
8026}
8027
8028/* Maverick shift immediate instructions.
8029 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8030 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8031
8032static void
8033do_mav_shift (void)
8034{
8035 int imm = inst.operands[2].imm;
8036
8037 inst.instruction |= inst.operands[0].reg << 12;
8038 inst.instruction |= inst.operands[1].reg << 16;
8039
8040 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8041 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8042 Bit 4 should be 0. */
8043 imm = (imm & 0xf) | ((imm & 0x70) << 1);
8044
8045 inst.instruction |= imm;
8046}
8047
8048/* XScale instructions. Also sorted arithmetic before move. */
8049
8050/* Xscale multiply-accumulate (argument parse)
8051 MIAcc acc0,Rm,Rs
8052 MIAPHcc acc0,Rm,Rs
8053 MIAxycc acc0,Rm,Rs. */
8054
8055static void
8056do_xsc_mia (void)
8057{
8058 inst.instruction |= inst.operands[1].reg;
8059 inst.instruction |= inst.operands[2].reg << 12;
8060}
8061
8062/* Xscale move-accumulator-register (argument parse)
8063
8064 MARcc acc0,RdLo,RdHi. */
8065
8066static void
8067do_xsc_mar (void)
8068{
8069 inst.instruction |= inst.operands[1].reg << 12;
8070 inst.instruction |= inst.operands[2].reg << 16;
8071}
8072
8073/* Xscale move-register-accumulator (argument parse)
8074
8075 MRAcc RdLo,RdHi,acc0. */
8076
8077static void
8078do_xsc_mra (void)
8079{
8080 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
8081 inst.instruction |= inst.operands[0].reg << 12;
8082 inst.instruction |= inst.operands[1].reg << 16;
8083}
8084
8085/* Encoding functions relevant only to Thumb. */
8086
8087/* inst.operands[i] is a shifted-register operand; encode
8088 it into inst.instruction in the format used by Thumb32. */
8089
8090static void
8091encode_thumb32_shifted_operand (int i)
8092{
8093 unsigned int value = inst.reloc.exp.X_add_number;
8094 unsigned int shift = inst.operands[i].shift_kind;
8095
8096 constraint (inst.operands[i].immisreg,
8097 _("shift by register not allowed in thumb mode"));
8098 inst.instruction |= inst.operands[i].reg;
8099 if (shift == SHIFT_RRX)
8100 inst.instruction |= SHIFT_ROR << 4;
8101 else
8102 {
8103 constraint (inst.reloc.exp.X_op != O_constant,
8104 _("expression too complex"));
8105
8106 constraint (value > 32
8107 || (value == 32 && (shift == SHIFT_LSL
8108 || shift == SHIFT_ROR)),
8109 _("shift expression is too large"));
8110
8111 if (value == 0)
8112 shift = SHIFT_LSL;
8113 else if (value == 32)
8114 value = 0;
8115
8116 inst.instruction |= shift << 4;
8117 inst.instruction |= (value & 0x1c) << 10;
8118 inst.instruction |= (value & 0x03) << 6;
8119 }
8120}
8121
8122
8123/* inst.operands[i] was set up by parse_address. Encode it into a
8124 Thumb32 format load or store instruction. Reject forms that cannot
8125 be used with such instructions. If is_t is true, reject forms that
8126 cannot be used with a T instruction; if is_d is true, reject forms
8127 that cannot be used with a D instruction. */
8128
8129static void
8130encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
8131{
8132 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
8133
8134 constraint (!inst.operands[i].isreg,
8135 _("Instruction does not support =N addresses"));
8136
8137 inst.instruction |= inst.operands[i].reg << 16;
8138 if (inst.operands[i].immisreg)
8139 {
8140 constraint (is_pc, _("cannot use register index with PC-relative addressing"));
8141 constraint (is_t || is_d, _("cannot use register index with this instruction"));
8142 constraint (inst.operands[i].negative,
8143 _("Thumb does not support negative register indexing"));
8144 constraint (inst.operands[i].postind,
8145 _("Thumb does not support register post-indexing"));
8146 constraint (inst.operands[i].writeback,
8147 _("Thumb does not support register indexing with writeback"));
8148 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
8149 _("Thumb supports only LSL in shifted register indexing"));
8150
8151 inst.instruction |= inst.operands[i].imm;
8152 if (inst.operands[i].shifted)
8153 {
8154 constraint (inst.reloc.exp.X_op != O_constant,
8155 _("expression too complex"));
8156 constraint (inst.reloc.exp.X_add_number < 0
8157 || inst.reloc.exp.X_add_number > 3,
8158 _("shift out of range"));
8159 inst.instruction |= inst.reloc.exp.X_add_number << 4;
8160 }
8161 inst.reloc.type = BFD_RELOC_UNUSED;
8162 }
8163 else if (inst.operands[i].preind)
8164 {
8165 constraint (is_pc && inst.operands[i].writeback,
8166 _("cannot use writeback with PC-relative addressing"));
8167 constraint (is_t && inst.operands[i].writeback,
8168 _("cannot use writeback with this instruction"));
8169
8170 if (is_d)
8171 {
8172 inst.instruction |= 0x01000000;
8173 if (inst.operands[i].writeback)
8174 inst.instruction |= 0x00200000;
8175 }
8176 else
8177 {
8178 inst.instruction |= 0x00000c00;
8179 if (inst.operands[i].writeback)
8180 inst.instruction |= 0x00000100;
8181 }
8182 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
8183 }
8184 else if (inst.operands[i].postind)
8185 {
8186 assert (inst.operands[i].writeback);
8187 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
8188 constraint (is_t, _("cannot use post-indexing with this instruction"));
8189
8190 if (is_d)
8191 inst.instruction |= 0x00200000;
8192 else
8193 inst.instruction |= 0x00000900;
8194 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
8195 }
8196 else /* unindexed - only for coprocessor */
8197 inst.error = _("instruction does not accept unindexed addressing");
8198}
8199
8200/* Table of Thumb instructions which exist in both 16- and 32-bit
8201 encodings (the latter only in post-V6T2 cores). The index is the
8202 value used in the insns table below. When there is more than one
8203 possible 16-bit encoding for the instruction, this table always
8204 holds variant (1).
8205 Also contains several pseudo-instructions used during relaxation. */
8206#define T16_32_TAB \
8207 X(adc, 4140, eb400000), \
8208 X(adcs, 4140, eb500000), \
8209 X(add, 1c00, eb000000), \
8210 X(adds, 1c00, eb100000), \
8211 X(addi, 0000, f1000000), \
8212 X(addis, 0000, f1100000), \
8213 X(add_pc,000f, f20f0000), \
8214 X(add_sp,000d, f10d0000), \
8215 X(adr, 000f, f20f0000), \
8216 X(and, 4000, ea000000), \
8217 X(ands, 4000, ea100000), \
8218 X(asr, 1000, fa40f000), \
8219 X(asrs, 1000, fa50f000), \
8220 X(b, e000, f000b000), \
8221 X(bcond, d000, f0008000), \
8222 X(bic, 4380, ea200000), \
8223 X(bics, 4380, ea300000), \
8224 X(cmn, 42c0, eb100f00), \
8225 X(cmp, 2800, ebb00f00), \
8226 X(cpsie, b660, f3af8400), \
8227 X(cpsid, b670, f3af8600), \
8228 X(cpy, 4600, ea4f0000), \
8229 X(dec_sp,80dd, f1ad0d00), \
8230 X(eor, 4040, ea800000), \
8231 X(eors, 4040, ea900000), \
8232 X(inc_sp,00dd, f10d0d00), \
8233 X(ldmia, c800, e8900000), \
8234 X(ldr, 6800, f8500000), \
8235 X(ldrb, 7800, f8100000), \
8236 X(ldrh, 8800, f8300000), \
8237 X(ldrsb, 5600, f9100000), \
8238 X(ldrsh, 5e00, f9300000), \
8239 X(ldr_pc,4800, f85f0000), \
8240 X(ldr_pc2,4800, f85f0000), \
8241 X(ldr_sp,9800, f85d0000), \
8242 X(lsl, 0000, fa00f000), \
8243 X(lsls, 0000, fa10f000), \
8244 X(lsr, 0800, fa20f000), \
8245 X(lsrs, 0800, fa30f000), \
8246 X(mov, 2000, ea4f0000), \
8247 X(movs, 2000, ea5f0000), \
8248 X(mul, 4340, fb00f000), \
8249 X(muls, 4340, ffffffff), /* no 32b muls */ \
8250 X(mvn, 43c0, ea6f0000), \
8251 X(mvns, 43c0, ea7f0000), \
8252 X(neg, 4240, f1c00000), /* rsb #0 */ \
8253 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8254 X(orr, 4300, ea400000), \
8255 X(orrs, 4300, ea500000), \
8256 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8257 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8258 X(rev, ba00, fa90f080), \
8259 X(rev16, ba40, fa90f090), \
8260 X(revsh, bac0, fa90f0b0), \
8261 X(ror, 41c0, fa60f000), \
8262 X(rors, 41c0, fa70f000), \
8263 X(sbc, 4180, eb600000), \
8264 X(sbcs, 4180, eb700000), \
8265 X(stmia, c000, e8800000), \
8266 X(str, 6000, f8400000), \
8267 X(strb, 7000, f8000000), \
8268 X(strh, 8000, f8200000), \
8269 X(str_sp,9000, f84d0000), \
8270 X(sub, 1e00, eba00000), \
8271 X(subs, 1e00, ebb00000), \
8272 X(subi, 8000, f1a00000), \
8273 X(subis, 8000, f1b00000), \
8274 X(sxtb, b240, fa4ff080), \
8275 X(sxth, b200, fa0ff080), \
8276 X(tst, 4200, ea100f00), \
8277 X(uxtb, b2c0, fa5ff080), \
8278 X(uxth, b280, fa1ff080), \
8279 X(nop, bf00, f3af8000), \
8280 X(yield, bf10, f3af8001), \
8281 X(wfe, bf20, f3af8002), \
8282 X(wfi, bf30, f3af8003), \
8283 X(sev, bf40, f3af9004), /* typo, 8004? */
8284
8285/* To catch errors in encoding functions, the codes are all offset by
8286 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8287 as 16-bit instructions. */
8288#define X(a,b,c) T_MNEM_##a
8289enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
8290#undef X
8291
8292#define X(a,b,c) 0x##b
8293static const unsigned short thumb_op16[] = { T16_32_TAB };
8294#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8295#undef X
8296
8297#define X(a,b,c) 0x##c
8298static const unsigned int thumb_op32[] = { T16_32_TAB };
8299#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8300#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8301#undef X
8302#undef T16_32_TAB
8303
8304/* Thumb instruction encoders, in alphabetical order. */
8305
8306/* ADDW or SUBW. */
8307static void
8308do_t_add_sub_w (void)
8309{
8310 int Rd, Rn;
8311
8312 Rd = inst.operands[0].reg;
8313 Rn = inst.operands[1].reg;
8314
8315 constraint (Rd == 15, _("PC not allowed as destination"));
8316 inst.instruction |= (Rn << 16) | (Rd << 8);
8317 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
8318}
8319
8320/* Parse an add or subtract instruction. We get here with inst.instruction
8321 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8322
8323static void
8324do_t_add_sub (void)
8325{
8326 int Rd, Rs, Rn;
8327
8328 Rd = inst.operands[0].reg;
8329 Rs = (inst.operands[1].present
8330 ? inst.operands[1].reg /* Rd, Rs, foo */
8331 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
8332
8333 if (unified_syntax)
8334 {
8335 bfd_boolean flags;
8336 bfd_boolean narrow;
8337 int opcode;
8338
8339 flags = (inst.instruction == T_MNEM_adds
8340 || inst.instruction == T_MNEM_subs);
8341 if (flags)
8342 narrow = (current_it_mask == 0);
8343 else
8344 narrow = (current_it_mask != 0);
8345 if (!inst.operands[2].isreg)
8346 {
8347 int add;
8348
8349 add = (inst.instruction == T_MNEM_add
8350 || inst.instruction == T_MNEM_adds);
8351 opcode = 0;
8352 if (inst.size_req != 4)
8353 {
8354 /* Attempt to use a narrow opcode, with relaxation if
8355 appropriate. */
8356 if (Rd == REG_SP && Rs == REG_SP && !flags)
8357 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
8358 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
8359 opcode = T_MNEM_add_sp;
8360 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
8361 opcode = T_MNEM_add_pc;
8362 else if (Rd <= 7 && Rs <= 7 && narrow)
8363 {
8364 if (flags)
8365 opcode = add ? T_MNEM_addis : T_MNEM_subis;
8366 else
8367 opcode = add ? T_MNEM_addi : T_MNEM_subi;
8368 }
8369 if (opcode)
8370 {
8371 inst.instruction = THUMB_OP16(opcode);
8372 inst.instruction |= (Rd << 4) | Rs;
8373 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
8374 if (inst.size_req != 2)
8375 inst.relax = opcode;
8376 }
8377 else
8378 constraint (inst.size_req == 2, BAD_HIREG);
8379 }
8380 if (inst.size_req == 4
8381 || (inst.size_req != 2 && !opcode))
8382 {
8383 if (Rd == REG_PC)
8384 {
8385 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
8386 _("only SUBS PC, LR, #const allowed"));
8387 constraint (inst.reloc.exp.X_op != O_constant,
8388 _("expression too complex"));
8389 constraint (inst.reloc.exp.X_add_number < 0
8390 || inst.reloc.exp.X_add_number > 0xff,
8391 _("immediate value out of range"));
8392 inst.instruction = T2_SUBS_PC_LR
8393 | inst.reloc.exp.X_add_number;
8394 inst.reloc.type = BFD_RELOC_UNUSED;
8395 return;
8396 }
8397 else if (Rs == REG_PC)
8398 {
8399 /* Always use addw/subw. */
8400 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
8401 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
8402 }
8403 else
8404 {
8405 inst.instruction = THUMB_OP32 (inst.instruction);
8406 inst.instruction = (inst.instruction & 0xe1ffffff)
8407 | 0x10000000;
8408 if (flags)
8409 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
8410 else
8411 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
8412 }
8413 inst.instruction |= Rd << 8;
8414 inst.instruction |= Rs << 16;
8415 }
8416 }
8417 else
8418 {
8419 Rn = inst.operands[2].reg;
8420 /* See if we can do this with a 16-bit instruction. */
8421 if (!inst.operands[2].shifted && inst.size_req != 4)
8422 {
8423 if (Rd > 7 || Rs > 7 || Rn > 7)
8424 narrow = FALSE;
8425
8426 if (narrow)
8427 {
8428 inst.instruction = ((inst.instruction == T_MNEM_adds
8429 || inst.instruction == T_MNEM_add)
8430 ? T_OPCODE_ADD_R3
8431 : T_OPCODE_SUB_R3);
8432 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
8433 return;
8434 }
8435
8436 if (inst.instruction == T_MNEM_add)
8437 {
8438 if (Rd == Rs)
8439 {
8440 inst.instruction = T_OPCODE_ADD_HI;
8441 inst.instruction |= (Rd & 8) << 4;
8442 inst.instruction |= (Rd & 7);
8443 inst.instruction |= Rn << 3;
8444 return;
8445 }
8446 /* ... because addition is commutative! */
8447 else if (Rd == Rn)
8448 {
8449 inst.instruction = T_OPCODE_ADD_HI;
8450 inst.instruction |= (Rd & 8) << 4;
8451 inst.instruction |= (Rd & 7);
8452 inst.instruction |= Rs << 3;
8453 return;
8454 }
8455 }
8456 }
8457 /* If we get here, it can't be done in 16 bits. */
8458 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
8459 _("shift must be constant"));
8460 inst.instruction = THUMB_OP32 (inst.instruction);
8461 inst.instruction |= Rd << 8;
8462 inst.instruction |= Rs << 16;
8463 encode_thumb32_shifted_operand (2);
8464 }
8465 }
8466 else
8467 {
8468 constraint (inst.instruction == T_MNEM_adds
8469 || inst.instruction == T_MNEM_subs,
8470 BAD_THUMB32);
8471
8472 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
8473 {
8474 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
8475 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
8476 BAD_HIREG);
8477
8478 inst.instruction = (inst.instruction == T_MNEM_add
8479 ? 0x0000 : 0x8000);
8480 inst.instruction |= (Rd << 4) | Rs;
8481 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
8482 return;
8483 }
8484
8485 Rn = inst.operands[2].reg;
8486 constraint (inst.operands[2].shifted, _("unshifted register required"));
8487
8488 /* We now have Rd, Rs, and Rn set to registers. */
8489 if (Rd > 7 || Rs > 7 || Rn > 7)
8490 {
8491 /* Can't do this for SUB. */
8492 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
8493 inst.instruction = T_OPCODE_ADD_HI;
8494 inst.instruction |= (Rd & 8) << 4;
8495 inst.instruction |= (Rd & 7);
8496 if (Rs == Rd)
8497 inst.instruction |= Rn << 3;
8498 else if (Rn == Rd)
8499 inst.instruction |= Rs << 3;
8500 else
8501 constraint (1, _("dest must overlap one source register"));
8502 }
8503 else
8504 {
8505 inst.instruction = (inst.instruction == T_MNEM_add
8506 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
8507 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
8508 }
8509 }
8510}
8511
8512static void
8513do_t_adr (void)
8514{
8515 if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7)
8516 {
8517 /* Defer to section relaxation. */
8518 inst.relax = inst.instruction;
8519 inst.instruction = THUMB_OP16 (inst.instruction);
8520 inst.instruction |= inst.operands[0].reg << 4;
8521 }
8522 else if (unified_syntax && inst.size_req != 2)
8523 {
8524 /* Generate a 32-bit opcode. */
8525 inst.instruction = THUMB_OP32 (inst.instruction);
8526 inst.instruction |= inst.operands[0].reg << 8;
8527 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
8528 inst.reloc.pc_rel = 1;
8529 }
8530 else
8531 {
8532 /* Generate a 16-bit opcode. */
8533 inst.instruction = THUMB_OP16 (inst.instruction);
8534 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
8535 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
8536 inst.reloc.pc_rel = 1;
8537
8538 inst.instruction |= inst.operands[0].reg << 4;
8539 }
8540}
8541
8542/* Arithmetic instructions for which there is just one 16-bit
8543 instruction encoding, and it allows only two low registers.
8544 For maximal compatibility with ARM syntax, we allow three register
8545 operands even when Thumb-32 instructions are not available, as long
8546 as the first two are identical. For instance, both "sbc r0,r1" and
8547 "sbc r0,r0,r1" are allowed. */
8548static void
8549do_t_arit3 (void)
8550{
8551 int Rd, Rs, Rn;
8552
8553 Rd = inst.operands[0].reg;
8554 Rs = (inst.operands[1].present
8555 ? inst.operands[1].reg /* Rd, Rs, foo */
8556 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
8557 Rn = inst.operands[2].reg;
8558
8559 if (unified_syntax)
8560 {
8561 if (!inst.operands[2].isreg)
8562 {
8563 /* For an immediate, we always generate a 32-bit opcode;
8564 section relaxation will shrink it later if possible. */
8565 inst.instruction = THUMB_OP32 (inst.instruction);
8566 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
8567 inst.instruction |= Rd << 8;
8568 inst.instruction |= Rs << 16;
8569 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
8570 }
8571 else
8572 {
8573 bfd_boolean narrow;
8574
8575 /* See if we can do this with a 16-bit instruction. */
8576 if (THUMB_SETS_FLAGS (inst.instruction))
8577 narrow = current_it_mask == 0;
8578 else
8579 narrow = current_it_mask != 0;
8580
8581 if (Rd > 7 || Rn > 7 || Rs > 7)
8582 narrow = FALSE;
8583 if (inst.operands[2].shifted)
8584 narrow = FALSE;
8585 if (inst.size_req == 4)
8586 narrow = FALSE;
8587
8588 if (narrow
8589 && Rd == Rs)
8590 {
8591 inst.instruction = THUMB_OP16 (inst.instruction);
8592 inst.instruction |= Rd;
8593 inst.instruction |= Rn << 3;
8594 return;
8595 }
8596
8597 /* If we get here, it can't be done in 16 bits. */
8598 constraint (inst.operands[2].shifted
8599 && inst.operands[2].immisreg,
8600 _("shift must be constant"));
8601 inst.instruction = THUMB_OP32 (inst.instruction);
8602 inst.instruction |= Rd << 8;
8603 inst.instruction |= Rs << 16;
8604 encode_thumb32_shifted_operand (2);
8605 }
8606 }
8607 else
8608 {
8609 /* On its face this is a lie - the instruction does set the
8610 flags. However, the only supported mnemonic in this mode
8611 says it doesn't. */
8612 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
8613
8614 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
8615 _("unshifted register required"));
8616 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
8617 constraint (Rd != Rs,
8618 _("dest and source1 must be the same register"));
8619
8620 inst.instruction = THUMB_OP16 (inst.instruction);
8621 inst.instruction |= Rd;
8622 inst.instruction |= Rn << 3;
8623 }
8624}
8625
8626/* Similarly, but for instructions where the arithmetic operation is
8627 commutative, so we can allow either of them to be different from
8628 the destination operand in a 16-bit instruction. For instance, all
8629 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8630 accepted. */
8631static void
8632do_t_arit3c (void)
8633{
8634 int Rd, Rs, Rn;
8635
8636 Rd = inst.operands[0].reg;
8637 Rs = (inst.operands[1].present
8638 ? inst.operands[1].reg /* Rd, Rs, foo */
8639 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
8640 Rn = inst.operands[2].reg;
8641
8642 if (unified_syntax)
8643 {
8644 if (!inst.operands[2].isreg)
8645 {
8646 /* For an immediate, we always generate a 32-bit opcode;
8647 section relaxation will shrink it later if possible. */
8648 inst.instruction = THUMB_OP32 (inst.instruction);
8649 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
8650 inst.instruction |= Rd << 8;
8651 inst.instruction |= Rs << 16;
8652 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
8653 }
8654 else
8655 {
8656 bfd_boolean narrow;
8657
8658 /* See if we can do this with a 16-bit instruction. */
8659 if (THUMB_SETS_FLAGS (inst.instruction))
8660 narrow = current_it_mask == 0;
8661 else
8662 narrow = current_it_mask != 0;
8663
8664 if (Rd > 7 || Rn > 7 || Rs > 7)
8665 narrow = FALSE;
8666 if (inst.operands[2].shifted)
8667 narrow = FALSE;
8668 if (inst.size_req == 4)
8669 narrow = FALSE;
8670
8671 if (narrow)
8672 {
8673 if (Rd == Rs)
8674 {
8675 inst.instruction = THUMB_OP16 (inst.instruction);
8676 inst.instruction |= Rd;
8677 inst.instruction |= Rn << 3;
8678 return;
8679 }
8680 if (Rd == Rn)
8681 {
8682 inst.instruction = THUMB_OP16 (inst.instruction);
8683 inst.instruction |= Rd;
8684 inst.instruction |= Rs << 3;
8685 return;
8686 }
8687 }
8688
8689 /* If we get here, it can't be done in 16 bits. */
8690 constraint (inst.operands[2].shifted
8691 && inst.operands[2].immisreg,
8692 _("shift must be constant"));
8693 inst.instruction = THUMB_OP32 (inst.instruction);
8694 inst.instruction |= Rd << 8;
8695 inst.instruction |= Rs << 16;
8696 encode_thumb32_shifted_operand (2);
8697 }
8698 }
8699 else
8700 {
8701 /* On its face this is a lie - the instruction does set the
8702 flags. However, the only supported mnemonic in this mode
8703 says it doesn't. */
8704 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
8705
8706 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
8707 _("unshifted register required"));
8708 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
8709
8710 inst.instruction = THUMB_OP16 (inst.instruction);
8711 inst.instruction |= Rd;
8712
8713 if (Rd == Rs)
8714 inst.instruction |= Rn << 3;
8715 else if (Rd == Rn)
8716 inst.instruction |= Rs << 3;
8717 else
8718 constraint (1, _("dest must overlap one source register"));
8719 }
8720}
8721
8722static void
8723do_t_barrier (void)
8724{
8725 if (inst.operands[0].present)
8726 {
8727 constraint ((inst.instruction & 0xf0) != 0x40
8728 && inst.operands[0].imm != 0xf,
8729 "bad barrier type");
8730 inst.instruction |= inst.operands[0].imm;
8731 }
8732 else
8733 inst.instruction |= 0xf;
8734}
8735
8736static void
8737do_t_bfc (void)
8738{
8739 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
8740 constraint (msb > 32, _("bit-field extends past end of register"));
8741 /* The instruction encoding stores the LSB and MSB,
8742 not the LSB and width. */
8743 inst.instruction |= inst.operands[0].reg << 8;
8744 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
8745 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
8746 inst.instruction |= msb - 1;
8747}
8748
8749static void
8750do_t_bfi (void)
8751{
8752 unsigned int msb;
8753
8754 /* #0 in second position is alternative syntax for bfc, which is
8755 the same instruction but with REG_PC in the Rm field. */
8756 if (!inst.operands[1].isreg)
8757 inst.operands[1].reg = REG_PC;
8758
8759 msb = inst.operands[2].imm + inst.operands[3].imm;
8760 constraint (msb > 32, _("bit-field extends past end of register"));
8761 /* The instruction encoding stores the LSB and MSB,
8762 not the LSB and width. */
8763 inst.instruction |= inst.operands[0].reg << 8;
8764 inst.instruction |= inst.operands[1].reg << 16;
8765 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
8766 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
8767 inst.instruction |= msb - 1;
8768}
8769
8770static void
8771do_t_bfx (void)
8772{
8773 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
8774 _("bit-field extends past end of register"));
8775 inst.instruction |= inst.operands[0].reg << 8;
8776 inst.instruction |= inst.operands[1].reg << 16;
8777 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
8778 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
8779 inst.instruction |= inst.operands[3].imm - 1;
8780}
8781
8782/* ARM V5 Thumb BLX (argument parse)
8783 BLX <target_addr> which is BLX(1)
8784 BLX <Rm> which is BLX(2)
8785 Unfortunately, there are two different opcodes for this mnemonic.
8786 So, the insns[].value is not used, and the code here zaps values
8787 into inst.instruction.
8788
8789 ??? How to take advantage of the additional two bits of displacement
8790 available in Thumb32 mode? Need new relocation? */
8791
8792static void
8793do_t_blx (void)
8794{
8795 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8796 if (inst.operands[0].isreg)
8797 /* We have a register, so this is BLX(2). */
8798 inst.instruction |= inst.operands[0].reg << 3;
8799 else
8800 {
8801 /* No register. This must be BLX(1). */
8802 inst.instruction = 0xf000e800;
8803#ifdef OBJ_ELF
8804 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
8805 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
8806 else
8807#endif
8808 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
8809 inst.reloc.pc_rel = 1;
8810 }
8811}
8812
8813static void
8814do_t_branch (void)
8815{
8816 int opcode;
8817 int cond;
8818
8819 if (current_it_mask)
8820 {
8821 /* Conditional branches inside IT blocks are encoded as unconditional
8822 branches. */
8823 cond = COND_ALWAYS;
8824 /* A branch must be the last instruction in an IT block. */
8825 constraint (current_it_mask != 0x10, BAD_BRANCH);
8826 }
8827 else
8828 cond = inst.cond;
8829
8830 if (cond != COND_ALWAYS)
8831 opcode = T_MNEM_bcond;
8832 else
8833 opcode = inst.instruction;
8834
8835 if (unified_syntax && inst.size_req == 4)
8836 {
8837 inst.instruction = THUMB_OP32(opcode);
8838 if (cond == COND_ALWAYS)
8839 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
8840 else
8841 {
8842 assert (cond != 0xF);
8843 inst.instruction |= cond << 22;
8844 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
8845 }
8846 }
8847 else
8848 {
8849 inst.instruction = THUMB_OP16(opcode);
8850 if (cond == COND_ALWAYS)
8851 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
8852 else
8853 {
8854 inst.instruction |= cond << 8;
8855 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
8856 }
8857 /* Allow section relaxation. */
8858 if (unified_syntax && inst.size_req != 2)
8859 inst.relax = opcode;
8860 }
8861
8862 inst.reloc.pc_rel = 1;
8863}
8864
8865static void
8866do_t_bkpt (void)
8867{
8868 constraint (inst.cond != COND_ALWAYS,
8869 _("instruction is always unconditional"));
8870 if (inst.operands[0].present)
8871 {
8872 constraint (inst.operands[0].imm > 255,
8873 _("immediate value out of range"));
8874 inst.instruction |= inst.operands[0].imm;
8875 }
8876}
8877
8878static void
8879do_t_branch23 (void)
8880{
8881 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8882 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
8883 inst.reloc.pc_rel = 1;
8884
8885 /* If the destination of the branch is a defined symbol which does not have
8886 the THUMB_FUNC attribute, then we must be calling a function which has
8887 the (interfacearm) attribute. We look for the Thumb entry point to that
8888 function and change the branch to refer to that function instead. */
8889 if ( inst.reloc.exp.X_op == O_symbol
8890 && inst.reloc.exp.X_add_symbol != NULL
8891 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
8892 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
8893 inst.reloc.exp.X_add_symbol =
8894 find_real_start (inst.reloc.exp.X_add_symbol);
8895}
8896
8897static void
8898do_t_bx (void)
8899{
8900 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8901 inst.instruction |= inst.operands[0].reg << 3;
8902 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8903 should cause the alignment to be checked once it is known. This is
8904 because BX PC only works if the instruction is word aligned. */
8905}
8906
8907static void
8908do_t_bxj (void)
8909{
8910 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8911 if (inst.operands[0].reg == REG_PC)
8912 as_tsktsk (_("use of r15 in bxj is not really useful"));
8913
8914 inst.instruction |= inst.operands[0].reg << 16;
8915}
8916
8917static void
8918do_t_clz (void)
8919{
8920 inst.instruction |= inst.operands[0].reg << 8;
8921 inst.instruction |= inst.operands[1].reg << 16;
8922 inst.instruction |= inst.operands[1].reg;
8923}
8924
8925static void
8926do_t_cps (void)
8927{
8928 constraint (current_it_mask, BAD_NOT_IT);
8929 inst.instruction |= inst.operands[0].imm;
8930}
8931
8932static void
8933do_t_cpsi (void)
8934{
8935 constraint (current_it_mask, BAD_NOT_IT);
8936 if (unified_syntax
8937 && (inst.operands[1].present || inst.size_req == 4)
8938 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
8939 {
8940 unsigned int imod = (inst.instruction & 0x0030) >> 4;
8941 inst.instruction = 0xf3af8000;
8942 inst.instruction |= imod << 9;
8943 inst.instruction |= inst.operands[0].imm << 5;
8944 if (inst.operands[1].present)
8945 inst.instruction |= 0x100 | inst.operands[1].imm;
8946 }
8947 else
8948 {
8949 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
8950 && (inst.operands[0].imm & 4),
8951 _("selected processor does not support 'A' form "
8952 "of this instruction"));
8953 constraint (inst.operands[1].present || inst.size_req == 4,
8954 _("Thumb does not support the 2-argument "
8955 "form of this instruction"));
8956 inst.instruction |= inst.operands[0].imm;
8957 }
8958}
8959
8960/* THUMB CPY instruction (argument parse). */
8961
8962static void
8963do_t_cpy (void)
8964{
8965 if (inst.size_req == 4)
8966 {
8967 inst.instruction = THUMB_OP32 (T_MNEM_mov);
8968 inst.instruction |= inst.operands[0].reg << 8;
8969 inst.instruction |= inst.operands[1].reg;
8970 }
8971 else
8972 {
8973 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
8974 inst.instruction |= (inst.operands[0].reg & 0x7);
8975 inst.instruction |= inst.operands[1].reg << 3;
8976 }
8977}
8978
8979static void
8980do_t_cbz (void)
8981{
8982 constraint (current_it_mask, BAD_NOT_IT);
8983 constraint (inst.operands[0].reg > 7, BAD_HIREG);
8984 inst.instruction |= inst.operands[0].reg;
8985 inst.reloc.pc_rel = 1;
8986 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
8987}
8988
8989static void
8990do_t_dbg (void)
8991{
8992 inst.instruction |= inst.operands[0].imm;
8993}
8994
8995static void
8996do_t_div (void)
8997{
8998 if (!inst.operands[1].present)
8999 inst.operands[1].reg = inst.operands[0].reg;
9000 inst.instruction |= inst.operands[0].reg << 8;
9001 inst.instruction |= inst.operands[1].reg << 16;
9002 inst.instruction |= inst.operands[2].reg;
9003}
9004
9005static void
9006do_t_hint (void)
9007{
9008 if (unified_syntax && inst.size_req == 4)
9009 inst.instruction = THUMB_OP32 (inst.instruction);
9010 else
9011 inst.instruction = THUMB_OP16 (inst.instruction);
9012}
9013
9014static void
9015do_t_it (void)
9016{
9017 unsigned int cond = inst.operands[0].imm;
9018
9019 constraint (current_it_mask, BAD_NOT_IT);
9020 current_it_mask = (inst.instruction & 0xf) | 0x10;
9021 current_cc = cond;
9022
9023 /* If the condition is a negative condition, invert the mask. */
9024 if ((cond & 0x1) == 0x0)
9025 {
9026 unsigned int mask = inst.instruction & 0x000f;
9027
9028 if ((mask & 0x7) == 0)
9029 /* no conversion needed */;
9030 else if ((mask & 0x3) == 0)
9031 mask ^= 0x8;
9032 else if ((mask & 0x1) == 0)
9033 mask ^= 0xC;
9034 else
9035 mask ^= 0xE;
9036
9037 inst.instruction &= 0xfff0;
9038 inst.instruction |= mask;
9039 }
9040
9041 inst.instruction |= cond << 4;
9042}
9043
9044/* Helper function used for both push/pop and ldm/stm. */
9045static void
9046encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
9047{
9048 bfd_boolean load;
9049
9050 load = (inst.instruction & (1 << 20)) != 0;
9051
9052 if (mask & (1 << 13))
9053 inst.error = _("SP not allowed in register list");
9054 if (load)
9055 {
9056 if (mask & (1 << 14)
9057 && mask & (1 << 15))
9058 inst.error = _("LR and PC should not both be in register list");
9059
9060 if ((mask & (1 << base)) != 0
9061 && writeback)
9062 as_warn (_("base register should not be in register list "
9063 "when written back"));
9064 }
9065 else
9066 {
9067 if (mask & (1 << 15))
9068 inst.error = _("PC not allowed in register list");
9069
9070 if (mask & (1 << base))
9071 as_warn (_("value stored for r%d is UNPREDICTABLE"), base);
9072 }
9073
9074 if ((mask & (mask - 1)) == 0)
9075 {
9076 /* Single register transfers implemented as str/ldr. */
9077 if (writeback)
9078 {
9079 if (inst.instruction & (1 << 23))
9080 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
9081 else
9082 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
9083 }
9084 else
9085 {
9086 if (inst.instruction & (1 << 23))
9087 inst.instruction = 0x00800000; /* ia -> [base] */
9088 else
9089 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
9090 }
9091
9092 inst.instruction |= 0xf8400000;
9093 if (load)
9094 inst.instruction |= 0x00100000;
9095
9096 mask = ffs(mask) - 1;
9097 mask <<= 12;
9098 }
9099 else if (writeback)
9100 inst.instruction |= WRITE_BACK;
9101
9102 inst.instruction |= mask;
9103 inst.instruction |= base << 16;
9104}
9105
9106static void
9107do_t_ldmstm (void)
9108{
9109 /* This really doesn't seem worth it. */
9110 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
9111 _("expression too complex"));
9112 constraint (inst.operands[1].writeback,
9113 _("Thumb load/store multiple does not support {reglist}^"));
9114
9115 if (unified_syntax)
9116 {
9117 bfd_boolean narrow;
9118 unsigned mask;
9119
9120 narrow = FALSE;
9121 /* See if we can use a 16-bit instruction. */
9122 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
9123 && inst.size_req != 4
9124 && !(inst.operands[1].imm & ~0xff))
9125 {
9126 mask = 1 << inst.operands[0].reg;
9127
9128 if (inst.operands[0].reg <= 7
9129 && (inst.instruction == T_MNEM_stmia
9130 ? inst.operands[0].writeback
9131 : (inst.operands[0].writeback
9132 == !(inst.operands[1].imm & mask))))
9133 {
9134 if (inst.instruction == T_MNEM_stmia
9135 && (inst.operands[1].imm & mask)
9136 && (inst.operands[1].imm & (mask - 1)))
9137 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9138 inst.operands[0].reg);
9139
9140 inst.instruction = THUMB_OP16 (inst.instruction);
9141 inst.instruction |= inst.operands[0].reg << 8;
9142 inst.instruction |= inst.operands[1].imm;
9143 narrow = TRUE;
9144 }
9145 else if (inst.operands[0] .reg == REG_SP
9146 && inst.operands[0].writeback)
9147 {
9148 inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia
9149 ? T_MNEM_push : T_MNEM_pop);
9150 inst.instruction |= inst.operands[1].imm;
9151 narrow = TRUE;
9152 }
9153 }
9154
9155 if (!narrow)
9156 {
9157 if (inst.instruction < 0xffff)
9158 inst.instruction = THUMB_OP32 (inst.instruction);
9159
9160 encode_thumb2_ldmstm(inst.operands[0].reg, inst.operands[1].imm,
9161 inst.operands[0].writeback);
9162 }
9163 }
9164 else
9165 {
9166 constraint (inst.operands[0].reg > 7
9167 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
9168 constraint (inst.instruction != T_MNEM_ldmia
9169 && inst.instruction != T_MNEM_stmia,
9170 _("Thumb-2 instruction only valid in unified syntax"));
9171 if (inst.instruction == T_MNEM_stmia)
9172 {
9173 if (!inst.operands[0].writeback)
9174 as_warn (_("this instruction will write back the base register"));
9175 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
9176 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
9177 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9178 inst.operands[0].reg);
9179 }
9180 else
9181 {
9182 if (!inst.operands[0].writeback
9183 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
9184 as_warn (_("this instruction will write back the base register"));
9185 else if (inst.operands[0].writeback
9186 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
9187 as_warn (_("this instruction will not write back the base register"));
9188 }
9189
9190 inst.instruction = THUMB_OP16 (inst.instruction);
9191 inst.instruction |= inst.operands[0].reg << 8;
9192 inst.instruction |= inst.operands[1].imm;
9193 }
9194}
9195
9196static void
9197do_t_ldrex (void)
9198{
9199 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
9200 || inst.operands[1].postind || inst.operands[1].writeback
9201 || inst.operands[1].immisreg || inst.operands[1].shifted
9202 || inst.operands[1].negative,
9203 BAD_ADDR_MODE);
9204
9205 inst.instruction |= inst.operands[0].reg << 12;
9206 inst.instruction |= inst.operands[1].reg << 16;
9207 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
9208}
9209
9210static void
9211do_t_ldrexd (void)
9212{
9213 if (!inst.operands[1].present)
9214 {
9215 constraint (inst.operands[0].reg == REG_LR,
9216 _("r14 not allowed as first register "
9217 "when second register is omitted"));
9218 inst.operands[1].reg = inst.operands[0].reg + 1;
9219 }
9220 constraint (inst.operands[0].reg == inst.operands[1].reg,
9221 BAD_OVERLAP);
9222
9223 inst.instruction |= inst.operands[0].reg << 12;
9224 inst.instruction |= inst.operands[1].reg << 8;
9225 inst.instruction |= inst.operands[2].reg << 16;
9226}
9227
9228static void
9229do_t_ldst (void)
9230{
9231 unsigned long opcode;
9232 int Rn;
9233
9234 opcode = inst.instruction;
9235 if (unified_syntax)
9236 {
9237 if (!inst.operands[1].isreg)
9238 {
9239 if (opcode <= 0xffff)
9240 inst.instruction = THUMB_OP32 (opcode);
9241 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
9242 return;
9243 }
9244 if (inst.operands[1].isreg
9245 && !inst.operands[1].writeback
9246 && !inst.operands[1].shifted && !inst.operands[1].postind
9247 && !inst.operands[1].negative && inst.operands[0].reg <= 7
9248 && opcode <= 0xffff
9249 && inst.size_req != 4)
9250 {
9251 /* Insn may have a 16-bit form. */
9252 Rn = inst.operands[1].reg;
9253 if (inst.operands[1].immisreg)
9254 {
9255 inst.instruction = THUMB_OP16 (opcode);
9256 /* [Rn, Ri] */
9257 if (Rn <= 7 && inst.operands[1].imm <= 7)
9258 goto op16;
9259 }
9260 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
9261 && opcode != T_MNEM_ldrsb)
9262 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
9263 || (Rn == REG_SP && opcode == T_MNEM_str))
9264 {
9265 /* [Rn, #const] */
9266 if (Rn > 7)
9267 {
9268 if (Rn == REG_PC)
9269 {
9270 if (inst.reloc.pc_rel)
9271 opcode = T_MNEM_ldr_pc2;
9272 else
9273 opcode = T_MNEM_ldr_pc;
9274 }
9275 else
9276 {
9277 if (opcode == T_MNEM_ldr)
9278 opcode = T_MNEM_ldr_sp;
9279 else
9280 opcode = T_MNEM_str_sp;
9281 }
9282 inst.instruction = inst.operands[0].reg << 8;
9283 }
9284 else
9285 {
9286 inst.instruction = inst.operands[0].reg;
9287 inst.instruction |= inst.operands[1].reg << 3;
9288 }
9289 inst.instruction |= THUMB_OP16 (opcode);
9290 if (inst.size_req == 2)
9291 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
9292 else
9293 inst.relax = opcode;
9294 return;
9295 }
9296 }
9297 /* Definitely a 32-bit variant. */
9298 inst.instruction = THUMB_OP32 (opcode);
9299 inst.instruction |= inst.operands[0].reg << 12;
9300 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
9301 return;
9302 }
9303
9304 constraint (inst.operands[0].reg > 7, BAD_HIREG);
9305
9306 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
9307 {
9308 /* Only [Rn,Rm] is acceptable. */
9309 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
9310 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
9311 || inst.operands[1].postind || inst.operands[1].shifted
9312 || inst.operands[1].negative,
9313 _("Thumb does not support this addressing mode"));
9314 inst.instruction = THUMB_OP16 (inst.instruction);
9315 goto op16;
9316 }
9317
9318 inst.instruction = THUMB_OP16 (inst.instruction);
9319 if (!inst.operands[1].isreg)
9320 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
9321 return;
9322
9323 constraint (!inst.operands[1].preind
9324 || inst.operands[1].shifted
9325 || inst.operands[1].writeback,
9326 _("Thumb does not support this addressing mode"));
9327 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
9328 {
9329 constraint (inst.instruction & 0x0600,
9330 _("byte or halfword not valid for base register"));
9331 constraint (inst.operands[1].reg == REG_PC
9332 && !(inst.instruction & THUMB_LOAD_BIT),
9333 _("r15 based store not allowed"));
9334 constraint (inst.operands[1].immisreg,
9335 _("invalid base register for register offset"));
9336
9337 if (inst.operands[1].reg == REG_PC)
9338 inst.instruction = T_OPCODE_LDR_PC;
9339 else if (inst.instruction & THUMB_LOAD_BIT)
9340 inst.instruction = T_OPCODE_LDR_SP;
9341 else
9342 inst.instruction = T_OPCODE_STR_SP;
9343
9344 inst.instruction |= inst.operands[0].reg << 8;
9345 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
9346 return;
9347 }
9348
9349 constraint (inst.operands[1].reg > 7, BAD_HIREG);
9350 if (!inst.operands[1].immisreg)
9351 {
9352 /* Immediate offset. */
9353 inst.instruction |= inst.operands[0].reg;
9354 inst.instruction |= inst.operands[1].reg << 3;
9355 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
9356 return;
9357 }
9358
9359 /* Register offset. */
9360 constraint (inst.operands[1].imm > 7, BAD_HIREG);
9361 constraint (inst.operands[1].negative,
9362 _("Thumb does not support this addressing mode"));
9363
9364 op16:
9365 switch (inst.instruction)
9366 {
9367 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
9368 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
9369 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
9370 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
9371 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
9372 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
9373 case 0x5600 /* ldrsb */:
9374 case 0x5e00 /* ldrsh */: break;
9375 default: abort ();
9376 }
9377
9378 inst.instruction |= inst.operands[0].reg;
9379 inst.instruction |= inst.operands[1].reg << 3;
9380 inst.instruction |= inst.operands[1].imm << 6;
9381}
9382
9383static void
9384do_t_ldstd (void)
9385{
9386 if (!inst.operands[1].present)
9387 {
9388 inst.operands[1].reg = inst.operands[0].reg + 1;
9389 constraint (inst.operands[0].reg == REG_LR,
9390 _("r14 not allowed here"));
9391 }
9392 inst.instruction |= inst.operands[0].reg << 12;
9393 inst.instruction |= inst.operands[1].reg << 8;
9394 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
9395
9396}
9397
9398static void
9399do_t_ldstt (void)
9400{
9401 inst.instruction |= inst.operands[0].reg << 12;
9402 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
9403}
9404
9405static void
9406do_t_mla (void)
9407{
9408 inst.instruction |= inst.operands[0].reg << 8;
9409 inst.instruction |= inst.operands[1].reg << 16;
9410 inst.instruction |= inst.operands[2].reg;
9411 inst.instruction |= inst.operands[3].reg << 12;
9412}
9413
9414static void
9415do_t_mlal (void)
9416{
9417 inst.instruction |= inst.operands[0].reg << 12;
9418 inst.instruction |= inst.operands[1].reg << 8;
9419 inst.instruction |= inst.operands[2].reg << 16;
9420 inst.instruction |= inst.operands[3].reg;
9421}
9422
9423static void
9424do_t_mov_cmp (void)
9425{
9426 if (unified_syntax)
9427 {
9428 int r0off = (inst.instruction == T_MNEM_mov
9429 || inst.instruction == T_MNEM_movs) ? 8 : 16;
9430 unsigned long opcode;
9431 bfd_boolean narrow;
9432 bfd_boolean low_regs;
9433
9434 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7);
9435 opcode = inst.instruction;
9436 if (current_it_mask)
9437 narrow = opcode != T_MNEM_movs;
9438 else
9439 narrow = opcode != T_MNEM_movs || low_regs;
9440 if (inst.size_req == 4
9441 || inst.operands[1].shifted)
9442 narrow = FALSE;
9443
9444 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
9445 if (opcode == T_MNEM_movs && inst.operands[1].isreg
9446 && !inst.operands[1].shifted
9447 && inst.operands[0].reg == REG_PC
9448 && inst.operands[1].reg == REG_LR)
9449 {
9450 inst.instruction = T2_SUBS_PC_LR;
9451 return;
9452 }
9453
9454 if (!inst.operands[1].isreg)
9455 {
9456 /* Immediate operand. */
9457 if (current_it_mask == 0 && opcode == T_MNEM_mov)
9458 narrow = 0;
9459 if (low_regs && narrow)
9460 {
9461 inst.instruction = THUMB_OP16 (opcode);
9462 inst.instruction |= inst.operands[0].reg << 8;
9463 if (inst.size_req == 2)
9464 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
9465 else
9466 inst.relax = opcode;
9467 }
9468 else
9469 {
9470 inst.instruction = THUMB_OP32 (inst.instruction);
9471 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9472 inst.instruction |= inst.operands[0].reg << r0off;
9473 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9474 }
9475 }
9476 else if (inst.operands[1].shifted && inst.operands[1].immisreg
9477 && (inst.instruction == T_MNEM_mov
9478 || inst.instruction == T_MNEM_movs))
9479 {
9480 /* Register shifts are encoded as separate shift instructions. */
9481 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
9482
9483 if (current_it_mask)
9484 narrow = !flags;
9485 else
9486 narrow = flags;
9487
9488 if (inst.size_req == 4)
9489 narrow = FALSE;
9490
9491 if (!low_regs || inst.operands[1].imm > 7)
9492 narrow = FALSE;
9493
9494 if (inst.operands[0].reg != inst.operands[1].reg)
9495 narrow = FALSE;
9496
9497 switch (inst.operands[1].shift_kind)
9498 {
9499 case SHIFT_LSL:
9500 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
9501 break;
9502 case SHIFT_ASR:
9503 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
9504 break;
9505 case SHIFT_LSR:
9506 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
9507 break;
9508 case SHIFT_ROR:
9509 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
9510 break;
9511 default:
9512 abort();
9513 }
9514
9515 inst.instruction = opcode;
9516 if (narrow)
9517 {
9518 inst.instruction |= inst.operands[0].reg;
9519 inst.instruction |= inst.operands[1].imm << 3;
9520 }
9521 else
9522 {
9523 if (flags)
9524 inst.instruction |= CONDS_BIT;
9525
9526 inst.instruction |= inst.operands[0].reg << 8;
9527 inst.instruction |= inst.operands[1].reg << 16;
9528 inst.instruction |= inst.operands[1].imm;
9529 }
9530 }
9531 else if (!narrow)
9532 {
9533 /* Some mov with immediate shift have narrow variants.
9534 Register shifts are handled above. */
9535 if (low_regs && inst.operands[1].shifted
9536 && (inst.instruction == T_MNEM_mov
9537 || inst.instruction == T_MNEM_movs))
9538 {
9539 if (current_it_mask)
9540 narrow = (inst.instruction == T_MNEM_mov);
9541 else
9542 narrow = (inst.instruction == T_MNEM_movs);
9543 }
9544
9545 if (narrow)
9546 {
9547 switch (inst.operands[1].shift_kind)
9548 {
9549 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
9550 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
9551 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
9552 default: narrow = FALSE; break;
9553 }
9554 }
9555
9556 if (narrow)
9557 {
9558 inst.instruction |= inst.operands[0].reg;
9559 inst.instruction |= inst.operands[1].reg << 3;
9560 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
9561 }
9562 else
9563 {
9564 inst.instruction = THUMB_OP32 (inst.instruction);
9565 inst.instruction |= inst.operands[0].reg << r0off;
9566 encode_thumb32_shifted_operand (1);
9567 }
9568 }
9569 else
9570 switch (inst.instruction)
9571 {
9572 case T_MNEM_mov:
9573 inst.instruction = T_OPCODE_MOV_HR;
9574 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9575 inst.instruction |= (inst.operands[0].reg & 0x7);
9576 inst.instruction |= inst.operands[1].reg << 3;
9577 break;
9578
9579 case T_MNEM_movs:
9580 /* We know we have low registers at this point.
9581 Generate ADD Rd, Rs, #0. */
9582 inst.instruction = T_OPCODE_ADD_I3;
9583 inst.instruction |= inst.operands[0].reg;
9584 inst.instruction |= inst.operands[1].reg << 3;
9585 break;
9586
9587 case T_MNEM_cmp:
9588 if (low_regs)
9589 {
9590 inst.instruction = T_OPCODE_CMP_LR;
9591 inst.instruction |= inst.operands[0].reg;
9592 inst.instruction |= inst.operands[1].reg << 3;
9593 }
9594 else
9595 {
9596 inst.instruction = T_OPCODE_CMP_HR;
9597 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9598 inst.instruction |= (inst.operands[0].reg & 0x7);
9599 inst.instruction |= inst.operands[1].reg << 3;
9600 }
9601 break;
9602 }
9603 return;
9604 }
9605
9606 inst.instruction = THUMB_OP16 (inst.instruction);
9607 if (inst.operands[1].isreg)
9608 {
9609 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
9610 {
9611 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9612 since a MOV instruction produces unpredictable results. */
9613 if (inst.instruction == T_OPCODE_MOV_I8)
9614 inst.instruction = T_OPCODE_ADD_I3;
9615 else
9616 inst.instruction = T_OPCODE_CMP_LR;
9617
9618 inst.instruction |= inst.operands[0].reg;
9619 inst.instruction |= inst.operands[1].reg << 3;
9620 }
9621 else
9622 {
9623 if (inst.instruction == T_OPCODE_MOV_I8)
9624 inst.instruction = T_OPCODE_MOV_HR;
9625 else
9626 inst.instruction = T_OPCODE_CMP_HR;
9627 do_t_cpy ();
9628 }
9629 }
9630 else
9631 {
9632 constraint (inst.operands[0].reg > 7,
9633 _("only lo regs allowed with immediate"));
9634 inst.instruction |= inst.operands[0].reg << 8;
9635 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
9636 }
9637}
9638
9639static void
9640do_t_mov16 (void)
9641{
9642 bfd_vma imm;
9643 bfd_boolean top;
9644
9645 top = (inst.instruction & 0x00800000) != 0;
9646 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
9647 {
9648 constraint (top, _(":lower16: not allowed this instruction"));
9649 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
9650 }
9651 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
9652 {
9653 constraint (!top, _(":upper16: not allowed this instruction"));
9654 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
9655 }
9656
9657 inst.instruction |= inst.operands[0].reg << 8;
9658 if (inst.reloc.type == BFD_RELOC_UNUSED)
9659 {
9660 imm = inst.reloc.exp.X_add_number;
9661 inst.instruction |= (imm & 0xf000) << 4;
9662 inst.instruction |= (imm & 0x0800) << 15;
9663 inst.instruction |= (imm & 0x0700) << 4;
9664 inst.instruction |= (imm & 0x00ff);
9665 }
9666}
9667
9668static void
9669do_t_mvn_tst (void)
9670{
9671 if (unified_syntax)
9672 {
9673 int r0off = (inst.instruction == T_MNEM_mvn
9674 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
9675 bfd_boolean narrow;
9676
9677 if (inst.size_req == 4
9678 || inst.instruction > 0xffff
9679 || inst.operands[1].shifted
9680 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
9681 narrow = FALSE;
9682 else if (inst.instruction == T_MNEM_cmn)
9683 narrow = TRUE;
9684 else if (THUMB_SETS_FLAGS (inst.instruction))
9685 narrow = (current_it_mask == 0);
9686 else
9687 narrow = (current_it_mask != 0);
9688
9689 if (!inst.operands[1].isreg)
9690 {
9691 /* For an immediate, we always generate a 32-bit opcode;
9692 section relaxation will shrink it later if possible. */
9693 if (inst.instruction < 0xffff)
9694 inst.instruction = THUMB_OP32 (inst.instruction);
9695 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9696 inst.instruction |= inst.operands[0].reg << r0off;
9697 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9698 }
9699 else
9700 {
9701 /* See if we can do this with a 16-bit instruction. */
9702 if (narrow)
9703 {
9704 inst.instruction = THUMB_OP16 (inst.instruction);
9705 inst.instruction |= inst.operands[0].reg;
9706 inst.instruction |= inst.operands[1].reg << 3;
9707 }
9708 else
9709 {
9710 constraint (inst.operands[1].shifted
9711 && inst.operands[1].immisreg,
9712 _("shift must be constant"));
9713 if (inst.instruction < 0xffff)
9714 inst.instruction = THUMB_OP32 (inst.instruction);
9715 inst.instruction |= inst.operands[0].reg << r0off;
9716 encode_thumb32_shifted_operand (1);
9717 }
9718 }
9719 }
9720 else
9721 {
9722 constraint (inst.instruction > 0xffff
9723 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
9724 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
9725 _("unshifted register required"));
9726 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9727 BAD_HIREG);
9728
9729 inst.instruction = THUMB_OP16 (inst.instruction);
9730 inst.instruction |= inst.operands[0].reg;
9731 inst.instruction |= inst.operands[1].reg << 3;
9732 }
9733}
9734
9735static void
9736do_t_mrs (void)
9737{
9738 int flags;
9739
9740 if (do_vfp_nsyn_mrs () == SUCCESS)
9741 return;
9742
9743 flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
9744 if (flags == 0)
9745 {
9746 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m),
9747 _("selected processor does not support "
9748 "requested special purpose register"));
9749 }
9750 else
9751 {
9752 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
9753 _("selected processor does not support "
9754 "requested special purpose register %x"));
9755 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9756 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
9757 _("'CPSR' or 'SPSR' expected"));
9758 }
9759
9760 inst.instruction |= inst.operands[0].reg << 8;
9761 inst.instruction |= (flags & SPSR_BIT) >> 2;
9762 inst.instruction |= inst.operands[1].imm & 0xff;
9763}
9764
9765static void
9766do_t_msr (void)
9767{
9768 int flags;
9769
9770 if (do_vfp_nsyn_msr () == SUCCESS)
9771 return;
9772
9773 constraint (!inst.operands[1].isreg,
9774 _("Thumb encoding does not support an immediate here"));
9775 flags = inst.operands[0].imm;
9776 if (flags & ~0xff)
9777 {
9778 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
9779 _("selected processor does not support "
9780 "requested special purpose register"));
9781 }
9782 else
9783 {
9784 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m),
9785 _("selected processor does not support "
9786 "requested special purpose register"));
9787 flags |= PSR_f;
9788 }
9789 inst.instruction |= (flags & SPSR_BIT) >> 2;
9790 inst.instruction |= (flags & ~SPSR_BIT) >> 8;
9791 inst.instruction |= (flags & 0xff);
9792 inst.instruction |= inst.operands[1].reg << 16;
9793}
9794
9795static void
9796do_t_mul (void)
9797{
9798 if (!inst.operands[2].present)
9799 inst.operands[2].reg = inst.operands[0].reg;
9800
9801 /* There is no 32-bit MULS and no 16-bit MUL. */
9802 if (unified_syntax && inst.instruction == T_MNEM_mul)
9803 {
9804 inst.instruction = THUMB_OP32 (inst.instruction);
9805 inst.instruction |= inst.operands[0].reg << 8;
9806 inst.instruction |= inst.operands[1].reg << 16;
9807 inst.instruction |= inst.operands[2].reg << 0;
9808 }
9809 else
9810 {
9811 constraint (!unified_syntax
9812 && inst.instruction == T_MNEM_muls, BAD_THUMB32);
9813 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9814 BAD_HIREG);
9815
9816 inst.instruction = THUMB_OP16 (inst.instruction);
9817 inst.instruction |= inst.operands[0].reg;
9818
9819 if (inst.operands[0].reg == inst.operands[1].reg)
9820 inst.instruction |= inst.operands[2].reg << 3;
9821 else if (inst.operands[0].reg == inst.operands[2].reg)
9822 inst.instruction |= inst.operands[1].reg << 3;
9823 else
9824 constraint (1, _("dest must overlap one source register"));
9825 }
9826}
9827
9828static void
9829do_t_mull (void)
9830{
9831 inst.instruction |= inst.operands[0].reg << 12;
9832 inst.instruction |= inst.operands[1].reg << 8;
9833 inst.instruction |= inst.operands[2].reg << 16;
9834 inst.instruction |= inst.operands[3].reg;
9835
9836 if (inst.operands[0].reg == inst.operands[1].reg)
9837 as_tsktsk (_("rdhi and rdlo must be different"));
9838}
9839
9840static void
9841do_t_nop (void)
9842{
9843 if (unified_syntax)
9844 {
9845 if (inst.size_req == 4 || inst.operands[0].imm > 15)
9846 {
9847 inst.instruction = THUMB_OP32 (inst.instruction);
9848 inst.instruction |= inst.operands[0].imm;
9849 }
9850 else
9851 {
9852 inst.instruction = THUMB_OP16 (inst.instruction);
9853 inst.instruction |= inst.operands[0].imm << 4;
9854 }
9855 }
9856 else
9857 {
9858 constraint (inst.operands[0].present,
9859 _("Thumb does not support NOP with hints"));
9860 inst.instruction = 0x46c0;
9861 }
9862}
9863
9864static void
9865do_t_neg (void)
9866{
9867 if (unified_syntax)
9868 {
9869 bfd_boolean narrow;
9870
9871 if (THUMB_SETS_FLAGS (inst.instruction))
9872 narrow = (current_it_mask == 0);
9873 else
9874 narrow = (current_it_mask != 0);
9875 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
9876 narrow = FALSE;
9877 if (inst.size_req == 4)
9878 narrow = FALSE;
9879
9880 if (!narrow)
9881 {
9882 inst.instruction = THUMB_OP32 (inst.instruction);
9883 inst.instruction |= inst.operands[0].reg << 8;
9884 inst.instruction |= inst.operands[1].reg << 16;
9885 }
9886 else
9887 {
9888 inst.instruction = THUMB_OP16 (inst.instruction);
9889 inst.instruction |= inst.operands[0].reg;
9890 inst.instruction |= inst.operands[1].reg << 3;
9891 }
9892 }
9893 else
9894 {
9895 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9896 BAD_HIREG);
9897 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9898
9899 inst.instruction = THUMB_OP16 (inst.instruction);
9900 inst.instruction |= inst.operands[0].reg;
9901 inst.instruction |= inst.operands[1].reg << 3;
9902 }
9903}
9904
9905static void
9906do_t_pkhbt (void)
9907{
9908 inst.instruction |= inst.operands[0].reg << 8;
9909 inst.instruction |= inst.operands[1].reg << 16;
9910 inst.instruction |= inst.operands[2].reg;
9911 if (inst.operands[3].present)
9912 {
9913 unsigned int val = inst.reloc.exp.X_add_number;
9914 constraint (inst.reloc.exp.X_op != O_constant,
9915 _("expression too complex"));
9916 inst.instruction |= (val & 0x1c) << 10;
9917 inst.instruction |= (val & 0x03) << 6;
9918 }
9919}
9920
9921static void
9922do_t_pkhtb (void)
9923{
9924 if (!inst.operands[3].present)
9925 inst.instruction &= ~0x00000020;
9926 do_t_pkhbt ();
9927}
9928
9929static void
9930do_t_pld (void)
9931{
9932 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
9933}
9934
9935static void
9936do_t_push_pop (void)
9937{
9938 unsigned mask;
9939
9940 constraint (inst.operands[0].writeback,
9941 _("push/pop do not support {reglist}^"));
9942 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
9943 _("expression too complex"));
9944
9945 mask = inst.operands[0].imm;
9946 if ((mask & ~0xff) == 0)
9947 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
9948 else if ((inst.instruction == T_MNEM_push
9949 && (mask & ~0xff) == 1 << REG_LR)
9950 || (inst.instruction == T_MNEM_pop
9951 && (mask & ~0xff) == 1 << REG_PC))
9952 {
9953 inst.instruction = THUMB_OP16 (inst.instruction);
9954 inst.instruction |= THUMB_PP_PC_LR;
9955 inst.instruction |= mask & 0xff;
9956 }
9957 else if (unified_syntax)
9958 {
9959 inst.instruction = THUMB_OP32 (inst.instruction);
9960 encode_thumb2_ldmstm(13, mask, TRUE);
9961 }
9962 else
9963 {
9964 inst.error = _("invalid register list to push/pop instruction");
9965 return;
9966 }
9967}
9968
9969static void
9970do_t_rbit (void)
9971{
9972 inst.instruction |= inst.operands[0].reg << 8;
9973 inst.instruction |= inst.operands[1].reg << 16;
9974}
9975
9976static void
9977do_t_rd_rm (void)
9978{
9979 inst.instruction |= inst.operands[0].reg << 8;
9980 inst.instruction |= inst.operands[1].reg;
9981}
9982
9983static void
9984do_t_rev (void)
9985{
9986 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
9987 && inst.size_req != 4)
9988 {
9989 inst.instruction = THUMB_OP16 (inst.instruction);
9990 inst.instruction |= inst.operands[0].reg;
9991 inst.instruction |= inst.operands[1].reg << 3;
9992 }
9993 else if (unified_syntax)
9994 {
9995 inst.instruction = THUMB_OP32 (inst.instruction);
9996 inst.instruction |= inst.operands[0].reg << 8;
9997 inst.instruction |= inst.operands[1].reg << 16;
9998 inst.instruction |= inst.operands[1].reg;
9999 }
10000 else
10001 inst.error = BAD_HIREG;
10002}
10003
10004static void
10005do_t_rsb (void)
10006{
10007 int Rd, Rs;
10008
10009 Rd = inst.operands[0].reg;
10010 Rs = (inst.operands[1].present
10011 ? inst.operands[1].reg /* Rd, Rs, foo */
10012 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10013
10014 inst.instruction |= Rd << 8;
10015 inst.instruction |= Rs << 16;
10016 if (!inst.operands[2].isreg)
10017 {
10018 bfd_boolean narrow;
10019
10020 if ((inst.instruction & 0x00100000) != 0)
10021 narrow = (current_it_mask == 0);
10022 else
10023 narrow = (current_it_mask != 0);
10024
10025 if (Rd > 7 || Rs > 7)
10026 narrow = FALSE;
10027
10028 if (inst.size_req == 4 || !unified_syntax)
10029 narrow = FALSE;
10030
10031 if (inst.reloc.exp.X_op != O_constant
10032 || inst.reloc.exp.X_add_number != 0)
10033 narrow = FALSE;
10034
10035 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10036 relaxation, but it doesn't seem worth the hassle. */
10037 if (narrow)
10038 {
10039 inst.reloc.type = BFD_RELOC_UNUSED;
10040 inst.instruction = THUMB_OP16 (T_MNEM_negs);
10041 inst.instruction |= Rs << 3;
10042 inst.instruction |= Rd;
10043 }
10044 else
10045 {
10046 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10047 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10048 }
10049 }
10050 else
10051 encode_thumb32_shifted_operand (2);
10052}
10053
10054static void
10055do_t_setend (void)
10056{
10057 constraint (current_it_mask, BAD_NOT_IT);
10058 if (inst.operands[0].imm)
10059 inst.instruction |= 0x8;
10060}
10061
10062static void
10063do_t_shift (void)
10064{
10065 if (!inst.operands[1].present)
10066 inst.operands[1].reg = inst.operands[0].reg;
10067
10068 if (unified_syntax)
10069 {
10070 bfd_boolean narrow;
10071 int shift_kind;
10072
10073 switch (inst.instruction)
10074 {
10075 case T_MNEM_asr:
10076 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
10077 case T_MNEM_lsl:
10078 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
10079 case T_MNEM_lsr:
10080 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
10081 case T_MNEM_ror:
10082 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
10083 default: abort ();
10084 }
10085
10086 if (THUMB_SETS_FLAGS (inst.instruction))
10087 narrow = (current_it_mask == 0);
10088 else
10089 narrow = (current_it_mask != 0);
10090 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
10091 narrow = FALSE;
10092 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
10093 narrow = FALSE;
10094 if (inst.operands[2].isreg
10095 && (inst.operands[1].reg != inst.operands[0].reg
10096 || inst.operands[2].reg > 7))
10097 narrow = FALSE;
10098 if (inst.size_req == 4)
10099 narrow = FALSE;
10100
10101 if (!narrow)
10102 {
10103 if (inst.operands[2].isreg)
10104 {
10105 inst.instruction = THUMB_OP32 (inst.instruction);
10106 inst.instruction |= inst.operands[0].reg << 8;
10107 inst.instruction |= inst.operands[1].reg << 16;
10108 inst.instruction |= inst.operands[2].reg;
10109 }
10110 else
10111 {
10112 inst.operands[1].shifted = 1;
10113 inst.operands[1].shift_kind = shift_kind;
10114 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
10115 ? T_MNEM_movs : T_MNEM_mov);
10116 inst.instruction |= inst.operands[0].reg << 8;
10117 encode_thumb32_shifted_operand (1);
10118 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10119 inst.reloc.type = BFD_RELOC_UNUSED;
10120 }
10121 }
10122 else
10123 {
10124 if (inst.operands[2].isreg)
10125 {
10126 switch (shift_kind)
10127 {
10128 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
10129 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
10130 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
10131 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
10132 default: abort ();
10133 }
10134
10135 inst.instruction |= inst.operands[0].reg;
10136 inst.instruction |= inst.operands[2].reg << 3;
10137 }
10138 else
10139 {
10140 switch (shift_kind)
10141 {
10142 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
10143 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
10144 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
10145 default: abort ();
10146 }
10147 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10148 inst.instruction |= inst.operands[0].reg;
10149 inst.instruction |= inst.operands[1].reg << 3;
10150 }
10151 }
10152 }
10153 else
10154 {
10155 constraint (inst.operands[0].reg > 7
10156 || inst.operands[1].reg > 7, BAD_HIREG);
10157 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10158
10159 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
10160 {
10161 constraint (inst.operands[2].reg > 7, BAD_HIREG);
10162 constraint (inst.operands[0].reg != inst.operands[1].reg,
10163 _("source1 and dest must be same register"));
10164
10165 switch (inst.instruction)
10166 {
10167 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
10168 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
10169 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
10170 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
10171 default: abort ();
10172 }
10173
10174 inst.instruction |= inst.operands[0].reg;
10175 inst.instruction |= inst.operands[2].reg << 3;
10176 }
10177 else
10178 {
10179 switch (inst.instruction)
10180 {
10181 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
10182 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
10183 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
10184 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
10185 default: abort ();
10186 }
10187 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10188 inst.instruction |= inst.operands[0].reg;
10189 inst.instruction |= inst.operands[1].reg << 3;
10190 }
10191 }
10192}
10193
10194static void
10195do_t_simd (void)
10196{
10197 inst.instruction |= inst.operands[0].reg << 8;
10198 inst.instruction |= inst.operands[1].reg << 16;
10199 inst.instruction |= inst.operands[2].reg;
10200}
10201
10202static void
10203do_t_smc (void)
10204{
10205 unsigned int value = inst.reloc.exp.X_add_number;
10206 constraint (inst.reloc.exp.X_op != O_constant,
10207 _("expression too complex"));
10208 inst.reloc.type = BFD_RELOC_UNUSED;
10209 inst.instruction |= (value & 0xf000) >> 12;
10210 inst.instruction |= (value & 0x0ff0);
10211 inst.instruction |= (value & 0x000f) << 16;
10212}
10213
10214static void
10215do_t_ssat (void)
10216{
10217 inst.instruction |= inst.operands[0].reg << 8;
10218 inst.instruction |= inst.operands[1].imm - 1;
10219 inst.instruction |= inst.operands[2].reg << 16;
10220
10221 if (inst.operands[3].present)
10222 {
10223 constraint (inst.reloc.exp.X_op != O_constant,
10224 _("expression too complex"));
10225
10226 if (inst.reloc.exp.X_add_number != 0)
10227 {
10228 if (inst.operands[3].shift_kind == SHIFT_ASR)
10229 inst.instruction |= 0x00200000; /* sh bit */
10230 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
10231 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
10232 }
10233 inst.reloc.type = BFD_RELOC_UNUSED;
10234 }
10235}
10236
10237static void
10238do_t_ssat16 (void)
10239{
10240 inst.instruction |= inst.operands[0].reg << 8;
10241 inst.instruction |= inst.operands[1].imm - 1;
10242 inst.instruction |= inst.operands[2].reg << 16;
10243}
10244
10245static void
10246do_t_strex (void)
10247{
10248 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10249 || inst.operands[2].postind || inst.operands[2].writeback
10250 || inst.operands[2].immisreg || inst.operands[2].shifted
10251 || inst.operands[2].negative,
10252 BAD_ADDR_MODE);
10253
10254 inst.instruction |= inst.operands[0].reg << 8;
10255 inst.instruction |= inst.operands[1].reg << 12;
10256 inst.instruction |= inst.operands[2].reg << 16;
10257 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10258}
10259
10260static void
10261do_t_strexd (void)
10262{
10263 if (!inst.operands[2].present)
10264 inst.operands[2].reg = inst.operands[1].reg + 1;
10265
10266 constraint (inst.operands[0].reg == inst.operands[1].reg
10267 || inst.operands[0].reg == inst.operands[2].reg
10268 || inst.operands[0].reg == inst.operands[3].reg
10269 || inst.operands[1].reg == inst.operands[2].reg,
10270 BAD_OVERLAP);
10271
10272 inst.instruction |= inst.operands[0].reg;
10273 inst.instruction |= inst.operands[1].reg << 12;
10274 inst.instruction |= inst.operands[2].reg << 8;
10275 inst.instruction |= inst.operands[3].reg << 16;
10276}
10277
10278static void
10279do_t_sxtah (void)
10280{
10281 inst.instruction |= inst.operands[0].reg << 8;
10282 inst.instruction |= inst.operands[1].reg << 16;
10283 inst.instruction |= inst.operands[2].reg;
10284 inst.instruction |= inst.operands[3].imm << 4;
10285}
10286
10287static void
10288do_t_sxth (void)
10289{
10290 if (inst.instruction <= 0xffff && inst.size_req != 4
10291 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
10292 && (!inst.operands[2].present || inst.operands[2].imm == 0))
10293 {
10294 inst.instruction = THUMB_OP16 (inst.instruction);
10295 inst.instruction |= inst.operands[0].reg;
10296 inst.instruction |= inst.operands[1].reg << 3;
10297 }
10298 else if (unified_syntax)
10299 {
10300 if (inst.instruction <= 0xffff)
10301 inst.instruction = THUMB_OP32 (inst.instruction);
10302 inst.instruction |= inst.operands[0].reg << 8;
10303 inst.instruction |= inst.operands[1].reg;
10304 inst.instruction |= inst.operands[2].imm << 4;
10305 }
10306 else
10307 {
10308 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
10309 _("Thumb encoding does not support rotation"));
10310 constraint (1, BAD_HIREG);
10311 }
10312}
10313
10314static void
10315do_t_swi (void)
10316{
10317 inst.reloc.type = BFD_RELOC_ARM_SWI;
10318}
10319
10320static void
10321do_t_tb (void)
10322{
10323 int half;
10324
10325 half = (inst.instruction & 0x10) != 0;
10326 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
10327 constraint (inst.operands[0].immisreg,
10328 _("instruction requires register index"));
10329 constraint (inst.operands[0].imm == 15,
10330 _("PC is not a valid index register"));
10331 constraint (!half && inst.operands[0].shifted,
10332 _("instruction does not allow shifted index"));
10333 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm;
10334}
10335
10336static void
10337do_t_usat (void)
10338{
10339 inst.instruction |= inst.operands[0].reg << 8;
10340 inst.instruction |= inst.operands[1].imm;
10341 inst.instruction |= inst.operands[2].reg << 16;
10342
10343 if (inst.operands[3].present)
10344 {
10345 constraint (inst.reloc.exp.X_op != O_constant,
10346 _("expression too complex"));
10347 if (inst.reloc.exp.X_add_number != 0)
10348 {
10349 if (inst.operands[3].shift_kind == SHIFT_ASR)
10350 inst.instruction |= 0x00200000; /* sh bit */
10351
10352 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
10353 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
10354 }
10355 inst.reloc.type = BFD_RELOC_UNUSED;
10356 }
10357}
10358
10359static void
10360do_t_usat16 (void)
10361{
10362 inst.instruction |= inst.operands[0].reg << 8;
10363 inst.instruction |= inst.operands[1].imm;
10364 inst.instruction |= inst.operands[2].reg << 16;
10365}
10366
10367/* Neon instruction encoder helpers. */
10368
10369/* Encodings for the different types for various Neon opcodes. */
10370
10371/* An "invalid" code for the following tables. */
10372#define N_INV -1u
10373
10374struct neon_tab_entry
10375{
10376 unsigned integer;
10377 unsigned float_or_poly;
10378 unsigned scalar_or_imm;
10379};
10380
10381/* Map overloaded Neon opcodes to their respective encodings. */
10382#define NEON_ENC_TAB \
10383 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10384 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10385 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10386 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10387 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10388 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10389 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10390 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10391 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10392 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10393 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10394 /* Register variants of the following two instructions are encoded as
10395 vcge / vcgt with the operands reversed. */ \
10396 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10397 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
10398 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10399 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10400 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10401 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10402 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10403 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10404 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10405 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10406 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10407 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10408 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10409 X(vshl, 0x0000400, N_INV, 0x0800510), \
10410 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10411 X(vand, 0x0000110, N_INV, 0x0800030), \
10412 X(vbic, 0x0100110, N_INV, 0x0800030), \
10413 X(veor, 0x1000110, N_INV, N_INV), \
10414 X(vorn, 0x0300110, N_INV, 0x0800010), \
10415 X(vorr, 0x0200110, N_INV, 0x0800010), \
10416 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10417 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10418 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10419 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10420 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10421 X(vst1, 0x0000000, 0x0800000, N_INV), \
10422 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10423 X(vst2, 0x0000100, 0x0800100, N_INV), \
10424 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10425 X(vst3, 0x0000200, 0x0800200, N_INV), \
10426 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10427 X(vst4, 0x0000300, 0x0800300, N_INV), \
10428 X(vmovn, 0x1b20200, N_INV, N_INV), \
10429 X(vtrn, 0x1b20080, N_INV, N_INV), \
10430 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10431 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10432 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10433 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10434 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10435 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10436 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10437 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10438 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10439
10440enum neon_opc
10441{
10442#define X(OPC,I,F,S) N_MNEM_##OPC
10443NEON_ENC_TAB
10444#undef X
10445};
10446
10447static const struct neon_tab_entry neon_enc_tab[] =
10448{
10449#define X(OPC,I,F,S) { (I), (F), (S) }
10450NEON_ENC_TAB
10451#undef X
10452};
10453
10454#define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10455#define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10456#define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10457#define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10458#define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10459#define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10460#define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10461#define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10462#define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10463#define NEON_ENC_SINGLE(X) \
10464 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10465#define NEON_ENC_DOUBLE(X) \
10466 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10467
10468/* Define shapes for instruction operands. The following mnemonic characters
10469 are used in this table:
10470
10471 F - VFP S<n> register
10472 D - Neon D<n> register
10473 Q - Neon Q<n> register
10474 I - Immediate
10475 S - Scalar
10476 R - ARM register
10477 L - D<n> register list
10478
10479 This table is used to generate various data:
10480 - enumerations of the form NS_DDR to be used as arguments to
10481 neon_select_shape.
10482 - a table classifying shapes into single, double, quad, mixed.
10483 - a table used to drive neon_select_shape.
10484*/
10485
10486#define NEON_SHAPE_DEF \
10487 X(3, (D, D, D), DOUBLE), \
10488 X(3, (Q, Q, Q), QUAD), \
10489 X(3, (D, D, I), DOUBLE), \
10490 X(3, (Q, Q, I), QUAD), \
10491 X(3, (D, D, S), DOUBLE), \
10492 X(3, (Q, Q, S), QUAD), \
10493 X(2, (D, D), DOUBLE), \
10494 X(2, (Q, Q), QUAD), \
10495 X(2, (D, S), DOUBLE), \
10496 X(2, (Q, S), QUAD), \
10497 X(2, (D, R), DOUBLE), \
10498 X(2, (Q, R), QUAD), \
10499 X(2, (D, I), DOUBLE), \
10500 X(2, (Q, I), QUAD), \
10501 X(3, (D, L, D), DOUBLE), \
10502 X(2, (D, Q), MIXED), \
10503 X(2, (Q, D), MIXED), \
10504 X(3, (D, Q, I), MIXED), \
10505 X(3, (Q, D, I), MIXED), \
10506 X(3, (Q, D, D), MIXED), \
10507 X(3, (D, Q, Q), MIXED), \
10508 X(3, (Q, Q, D), MIXED), \
10509 X(3, (Q, D, S), MIXED), \
10510 X(3, (D, Q, S), MIXED), \
10511 X(4, (D, D, D, I), DOUBLE), \
10512 X(4, (Q, Q, Q, I), QUAD), \
10513 X(2, (F, F), SINGLE), \
10514 X(3, (F, F, F), SINGLE), \
10515 X(2, (F, I), SINGLE), \
10516 X(2, (F, D), MIXED), \
10517 X(2, (D, F), MIXED), \
10518 X(3, (F, F, I), MIXED), \
10519 X(4, (R, R, F, F), SINGLE), \
10520 X(4, (F, F, R, R), SINGLE), \
10521 X(3, (D, R, R), DOUBLE), \
10522 X(3, (R, R, D), DOUBLE), \
10523 X(2, (S, R), SINGLE), \
10524 X(2, (R, S), SINGLE), \
10525 X(2, (F, R), SINGLE), \
10526 X(2, (R, F), SINGLE)
10527
10528#define S2(A,B) NS_##A##B
10529#define S3(A,B,C) NS_##A##B##C
10530#define S4(A,B,C,D) NS_##A##B##C##D
10531
10532#define X(N, L, C) S##N L
10533
10534enum neon_shape
10535{
10536 NEON_SHAPE_DEF,
10537 NS_NULL
10538};
10539
10540#undef X
10541#undef S2
10542#undef S3
10543#undef S4
10544
10545enum neon_shape_class
10546{
10547 SC_SINGLE,
10548 SC_DOUBLE,
10549 SC_QUAD,
10550 SC_MIXED
10551};
10552
10553#define X(N, L, C) SC_##C
10554
10555static enum neon_shape_class neon_shape_class[] =
10556{
10557 NEON_SHAPE_DEF
10558};
10559
10560#undef X
10561
10562enum neon_shape_el
10563{
10564 SE_F,
10565 SE_D,
10566 SE_Q,
10567 SE_I,
10568 SE_S,
10569 SE_R,
10570 SE_L
10571};
10572
10573/* Register widths of above. */
10574static unsigned neon_shape_el_size[] =
10575{
10576 32,
10577 64,
10578 128,
10579 0,
10580 32,
10581 32,
10582 0
10583};
10584
10585struct neon_shape_info
10586{
10587 unsigned els;
10588 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
10589};
10590
10591#define S2(A,B) { SE_##A, SE_##B }
10592#define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10593#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10594
10595#define X(N, L, C) { N, S##N L }
10596
10597static struct neon_shape_info neon_shape_tab[] =
10598{
10599 NEON_SHAPE_DEF
10600};
10601
10602#undef X
10603#undef S2
10604#undef S3
10605#undef S4
10606
10607/* Bit masks used in type checking given instructions.
10608 'N_EQK' means the type must be the same as (or based on in some way) the key
10609 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10610 set, various other bits can be set as well in order to modify the meaning of
10611 the type constraint. */
10612
10613enum neon_type_mask
10614{
10615 N_S8 = 0x000001,
10616 N_S16 = 0x000002,
10617 N_S32 = 0x000004,
10618 N_S64 = 0x000008,
10619 N_U8 = 0x000010,
10620 N_U16 = 0x000020,
10621 N_U32 = 0x000040,
10622 N_U64 = 0x000080,
10623 N_I8 = 0x000100,
10624 N_I16 = 0x000200,
10625 N_I32 = 0x000400,
10626 N_I64 = 0x000800,
10627 N_8 = 0x001000,
10628 N_16 = 0x002000,
10629 N_32 = 0x004000,
10630 N_64 = 0x008000,
10631 N_P8 = 0x010000,
10632 N_P16 = 0x020000,
10633 N_F32 = 0x040000,
10634 N_F64 = 0x080000,
10635 N_KEY = 0x100000, /* key element (main type specifier). */
10636 N_EQK = 0x200000, /* given operand has the same type & size as the key. */
10637 N_VFP = 0x400000, /* VFP mode: operand size must match register width. */
10638 N_DBL = 0x000001, /* if N_EQK, this operand is twice the size. */
10639 N_HLF = 0x000002, /* if N_EQK, this operand is half the size. */
10640 N_SGN = 0x000004, /* if N_EQK, this operand is forced to be signed. */
10641 N_UNS = 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10642 N_INT = 0x000010, /* if N_EQK, this operand is forced to be integer. */
10643 N_FLT = 0x000020, /* if N_EQK, this operand is forced to be float. */
10644 N_SIZ = 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10645 N_UTYP = 0,
10646 N_MAX_NONSPECIAL = N_F64
10647};
10648
10649#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10650
10651#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10652#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10653#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10654#define N_SUF_32 (N_SU_32 | N_F32)
10655#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10656#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10657
10658/* Pass this as the first type argument to neon_check_type to ignore types
10659 altogether. */
10660#define N_IGNORE_TYPE (N_KEY | N_EQK)
10661
10662/* Select a "shape" for the current instruction (describing register types or
10663 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10664 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10665 function of operand parsing, so this function doesn't need to be called.
10666 Shapes should be listed in order of decreasing length. */
10667
10668static enum neon_shape
10669neon_select_shape (enum neon_shape shape, ...)
10670{
10671 va_list ap;
10672 enum neon_shape first_shape = shape;
10673
10674 /* Fix missing optional operands. FIXME: we don't know at this point how
10675 many arguments we should have, so this makes the assumption that we have
10676 > 1. This is true of all current Neon opcodes, I think, but may not be
10677 true in the future. */
10678 if (!inst.operands[1].present)
10679 inst.operands[1] = inst.operands[0];
10680
10681 va_start (ap, shape);
10682
10683 for (; shape != NS_NULL; shape = va_arg (ap, int))
10684 {
10685 unsigned j;
10686 int matches = 1;
10687
10688 for (j = 0; j < neon_shape_tab[shape].els; j++)
10689 {
10690 if (!inst.operands[j].present)
10691 {
10692 matches = 0;
10693 break;
10694 }
10695
10696 switch (neon_shape_tab[shape].el[j])
10697 {
10698 case SE_F:
10699 if (!(inst.operands[j].isreg
10700 && inst.operands[j].isvec
10701 && inst.operands[j].issingle
10702 && !inst.operands[j].isquad))
10703 matches = 0;
10704 break;
10705
10706 case SE_D:
10707 if (!(inst.operands[j].isreg
10708 && inst.operands[j].isvec
10709 && !inst.operands[j].isquad
10710 && !inst.operands[j].issingle))
10711 matches = 0;
10712 break;
10713
10714 case SE_R:
10715 if (!(inst.operands[j].isreg
10716 && !inst.operands[j].isvec))
10717 matches = 0;
10718 break;
10719
10720 case SE_Q:
10721 if (!(inst.operands[j].isreg
10722 && inst.operands[j].isvec
10723 && inst.operands[j].isquad
10724 && !inst.operands[j].issingle))
10725 matches = 0;
10726 break;
10727
10728 case SE_I:
10729 if (!(!inst.operands[j].isreg
10730 && !inst.operands[j].isscalar))
10731 matches = 0;
10732 break;
10733
10734 case SE_S:
10735 if (!(!inst.operands[j].isreg
10736 && inst.operands[j].isscalar))
10737 matches = 0;
10738 break;
10739
10740 case SE_L:
10741 break;
10742 }
10743 }
10744 if (matches)
10745 break;
10746 }
10747
10748 va_end (ap);
10749
10750 if (shape == NS_NULL && first_shape != NS_NULL)
10751 first_error (_("invalid instruction shape"));
10752
10753 return shape;
10754}
10755
10756/* True if SHAPE is predominantly a quadword operation (most of the time, this
10757 means the Q bit should be set). */
10758
10759static int
10760neon_quad (enum neon_shape shape)
10761{
10762 return neon_shape_class[shape] == SC_QUAD;
10763}
10764
10765static void
10766neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
10767 unsigned *g_size)
10768{
10769 /* Allow modification to be made to types which are constrained to be
10770 based on the key element, based on bits set alongside N_EQK. */
10771 if ((typebits & N_EQK) != 0)
10772 {
10773 if ((typebits & N_HLF) != 0)
10774 *g_size /= 2;
10775 else if ((typebits & N_DBL) != 0)
10776 *g_size *= 2;
10777 if ((typebits & N_SGN) != 0)
10778 *g_type = NT_signed;
10779 else if ((typebits & N_UNS) != 0)
10780 *g_type = NT_unsigned;
10781 else if ((typebits & N_INT) != 0)
10782 *g_type = NT_integer;
10783 else if ((typebits & N_FLT) != 0)
10784 *g_type = NT_float;
10785 else if ((typebits & N_SIZ) != 0)
10786 *g_type = NT_untyped;
10787 }
10788}
10789
10790/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10791 operand type, i.e. the single type specified in a Neon instruction when it
10792 is the only one given. */
10793
10794static struct neon_type_el
10795neon_type_promote (struct neon_type_el *key, unsigned thisarg)
10796{
10797 struct neon_type_el dest = *key;
10798
10799 assert ((thisarg & N_EQK) != 0);
10800
10801 neon_modify_type_size (thisarg, &dest.type, &dest.size);
10802
10803 return dest;
10804}
10805
10806/* Convert Neon type and size into compact bitmask representation. */
10807
10808static enum neon_type_mask
10809type_chk_of_el_type (enum neon_el_type type, unsigned size)
10810{
10811 switch (type)
10812 {
10813 case NT_untyped:
10814 switch (size)
10815 {
10816 case 8: return N_8;
10817 case 16: return N_16;
10818 case 32: return N_32;
10819 case 64: return N_64;
10820 default: ;
10821 }
10822 break;
10823
10824 case NT_integer:
10825 switch (size)
10826 {
10827 case 8: return N_I8;
10828 case 16: return N_I16;
10829 case 32: return N_I32;
10830 case 64: return N_I64;
10831 default: ;
10832 }
10833 break;
10834
10835 case NT_float:
10836 switch (size)
10837 {
10838 case 32: return N_F32;
10839 case 64: return N_F64;
10840 default: ;
10841 }
10842 break;
10843
10844 case NT_poly:
10845 switch (size)
10846 {
10847 case 8: return N_P8;
10848 case 16: return N_P16;
10849 default: ;
10850 }
10851 break;
10852
10853 case NT_signed:
10854 switch (size)
10855 {
10856 case 8: return N_S8;
10857 case 16: return N_S16;
10858 case 32: return N_S32;
10859 case 64: return N_S64;
10860 default: ;
10861 }
10862 break;
10863
10864 case NT_unsigned:
10865 switch (size)
10866 {
10867 case 8: return N_U8;
10868 case 16: return N_U16;
10869 case 32: return N_U32;
10870 case 64: return N_U64;
10871 default: ;
10872 }
10873 break;
10874
10875 default: ;
10876 }
10877
10878 return N_UTYP;
10879}
10880
10881/* Convert compact Neon bitmask type representation to a type and size. Only
10882 handles the case where a single bit is set in the mask. */
10883
10884static int
10885el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
10886 enum neon_type_mask mask)
10887{
10888 if ((mask & N_EQK) != 0)
10889 return FAIL;
10890
10891 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
10892 *size = 8;
10893 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
10894 *size = 16;
10895 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
10896 *size = 32;
10897 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
10898 *size = 64;
10899 else
10900 return FAIL;
10901
10902 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
10903 *type = NT_signed;
10904 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
10905 *type = NT_unsigned;
10906 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
10907 *type = NT_integer;
10908 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
10909 *type = NT_untyped;
10910 else if ((mask & (N_P8 | N_P16)) != 0)
10911 *type = NT_poly;
10912 else if ((mask & (N_F32 | N_F64)) != 0)
10913 *type = NT_float;
10914 else
10915 return FAIL;
10916
10917 return SUCCESS;
10918}
10919
10920/* Modify a bitmask of allowed types. This is only needed for type
10921 relaxation. */
10922
10923static unsigned
10924modify_types_allowed (unsigned allowed, unsigned mods)
10925{
10926 unsigned size;
10927 enum neon_el_type type;
10928 unsigned destmask;
10929 int i;
10930
10931 destmask = 0;
10932
10933 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
10934 {
10935 if (el_type_of_type_chk (&type, &size, allowed & i) == SUCCESS)
10936 {
10937 neon_modify_type_size (mods, &type, &size);
10938 destmask |= type_chk_of_el_type (type, size);
10939 }
10940 }
10941
10942 return destmask;
10943}
10944
10945/* Check type and return type classification.
10946 The manual states (paraphrase): If one datatype is given, it indicates the
10947 type given in:
10948 - the second operand, if there is one
10949 - the operand, if there is no second operand
10950 - the result, if there are no operands.
10951 This isn't quite good enough though, so we use a concept of a "key" datatype
10952 which is set on a per-instruction basis, which is the one which matters when
10953 only one data type is written.
10954 Note: this function has side-effects (e.g. filling in missing operands). All
10955 Neon instructions should call it before performing bit encoding. */
10956
10957static struct neon_type_el
10958neon_check_type (unsigned els, enum neon_shape ns, ...)
10959{
10960 va_list ap;
10961 unsigned i, pass, key_el = 0;
10962 unsigned types[NEON_MAX_TYPE_ELS];
10963 enum neon_el_type k_type = NT_invtype;
10964 unsigned k_size = -1u;
10965 struct neon_type_el badtype = {NT_invtype, -1};
10966 unsigned key_allowed = 0;
10967
10968 /* Optional registers in Neon instructions are always (not) in operand 1.
10969 Fill in the missing operand here, if it was omitted. */
10970 if (els > 1 && !inst.operands[1].present)
10971 inst.operands[1] = inst.operands[0];
10972
10973 /* Suck up all the varargs. */
10974 va_start (ap, ns);
10975 for (i = 0; i < els; i++)
10976 {
10977 unsigned thisarg = va_arg (ap, unsigned);
10978 if (thisarg == N_IGNORE_TYPE)
10979 {
10980 va_end (ap);
10981 return badtype;
10982 }
10983 types[i] = thisarg;
10984 if ((thisarg & N_KEY) != 0)
10985 key_el = i;
10986 }
10987 va_end (ap);
10988
10989 if (inst.vectype.elems > 0)
10990 for (i = 0; i < els; i++)
10991 if (inst.operands[i].vectype.type != NT_invtype)
10992 {
10993 first_error (_("types specified in both the mnemonic and operands"));
10994 return badtype;
10995 }
10996
10997 /* Duplicate inst.vectype elements here as necessary.
10998 FIXME: No idea if this is exactly the same as the ARM assembler,
10999 particularly when an insn takes one register and one non-register
11000 operand. */
11001 if (inst.vectype.elems == 1 && els > 1)
11002 {
11003 unsigned j;
11004 inst.vectype.elems = els;
11005 inst.vectype.el[key_el] = inst.vectype.el[0];
11006 for (j = 0; j < els; j++)
11007 if (j != key_el)
11008 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
11009 types[j]);
11010 }
11011 else if (inst.vectype.elems == 0 && els > 0)
11012 {
11013 unsigned j;
11014 /* No types were given after the mnemonic, so look for types specified
11015 after each operand. We allow some flexibility here; as long as the
11016 "key" operand has a type, we can infer the others. */
11017 for (j = 0; j < els; j++)
11018 if (inst.operands[j].vectype.type != NT_invtype)
11019 inst.vectype.el[j] = inst.operands[j].vectype;
11020
11021 if (inst.operands[key_el].vectype.type != NT_invtype)
11022 {
11023 for (j = 0; j < els; j++)
11024 if (inst.operands[j].vectype.type == NT_invtype)
11025 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
11026 types[j]);
11027 }
11028 else
11029 {
11030 first_error (_("operand types can't be inferred"));
11031 return badtype;
11032 }
11033 }
11034 else if (inst.vectype.elems != els)
11035 {
11036 first_error (_("type specifier has the wrong number of parts"));
11037 return badtype;
11038 }
11039
11040 for (pass = 0; pass < 2; pass++)
11041 {
11042 for (i = 0; i < els; i++)
11043 {
11044 unsigned thisarg = types[i];
11045 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
11046 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
11047 enum neon_el_type g_type = inst.vectype.el[i].type;
11048 unsigned g_size = inst.vectype.el[i].size;
11049
11050 /* Decay more-specific signed & unsigned types to sign-insensitive
11051 integer types if sign-specific variants are unavailable. */
11052 if ((g_type == NT_signed || g_type == NT_unsigned)
11053 && (types_allowed & N_SU_ALL) == 0)
11054 g_type = NT_integer;
11055
11056 /* If only untyped args are allowed, decay any more specific types to
11057 them. Some instructions only care about signs for some element
11058 sizes, so handle that properly. */
11059 if ((g_size == 8 && (types_allowed & N_8) != 0)
11060 || (g_size == 16 && (types_allowed & N_16) != 0)
11061 || (g_size == 32 && (types_allowed & N_32) != 0)
11062 || (g_size == 64 && (types_allowed & N_64) != 0))
11063 g_type = NT_untyped;
11064
11065 if (pass == 0)
11066 {
11067 if ((thisarg & N_KEY) != 0)
11068 {
11069 k_type = g_type;
11070 k_size = g_size;
11071 key_allowed = thisarg & ~N_KEY;
11072 }
11073 }
11074 else
11075 {
11076 if ((thisarg & N_VFP) != 0)
11077 {
11078 enum neon_shape_el regshape = neon_shape_tab[ns].el[i];
11079 unsigned regwidth = neon_shape_el_size[regshape], match;
11080
11081 /* In VFP mode, operands must match register widths. If we
11082 have a key operand, use its width, else use the width of
11083 the current operand. */
11084 if (k_size != -1u)
11085 match = k_size;
11086 else
11087 match = g_size;
11088
11089 if (regwidth != match)
11090 {
11091 first_error (_("operand size must match register width"));
11092 return badtype;
11093 }
11094 }
11095
11096 if ((thisarg & N_EQK) == 0)
11097 {
11098 unsigned given_type = type_chk_of_el_type (g_type, g_size);
11099
11100 if ((given_type & types_allowed) == 0)
11101 {
11102 first_error (_("bad type in Neon instruction"));
11103 return badtype;
11104 }
11105 }
11106 else
11107 {
11108 enum neon_el_type mod_k_type = k_type;
11109 unsigned mod_k_size = k_size;
11110 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
11111 if (g_type != mod_k_type || g_size != mod_k_size)
11112 {
11113 first_error (_("inconsistent types in Neon instruction"));
11114 return badtype;
11115 }
11116 }
11117 }
11118 }
11119 }
11120
11121 return inst.vectype.el[key_el];
11122}
11123
11124/* Neon-style VFP instruction forwarding. */
11125
11126/* Thumb VFP instructions have 0xE in the condition field. */
11127
11128static void
11129do_vfp_cond_or_thumb (void)
11130{
11131 if (thumb_mode)
11132 inst.instruction |= 0xe0000000;
11133 else
11134 inst.instruction |= inst.cond << 28;
11135}
11136
11137/* Look up and encode a simple mnemonic, for use as a helper function for the
11138 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11139 etc. It is assumed that operand parsing has already been done, and that the
11140 operands are in the form expected by the given opcode (this isn't necessarily
11141 the same as the form in which they were parsed, hence some massaging must
11142 take place before this function is called).
11143 Checks current arch version against that in the looked-up opcode. */
11144
11145static void
11146do_vfp_nsyn_opcode (const char *opname)
11147{
11148 const struct asm_opcode *opcode;
11149
11150 opcode = hash_find (arm_ops_hsh, opname);
11151
11152 if (!opcode)
11153 abort ();
11154
11155 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
11156 thumb_mode ? *opcode->tvariant : *opcode->avariant),
11157 _(BAD_FPU));
11158
11159 if (thumb_mode)
11160 {
11161 inst.instruction = opcode->tvalue;
11162 opcode->tencode ();
11163 }
11164 else
11165 {
11166 inst.instruction = (inst.cond << 28) | opcode->avalue;
11167 opcode->aencode ();
11168 }
11169}
11170
11171static void
11172do_vfp_nsyn_add_sub (enum neon_shape rs)
11173{
11174 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
11175
11176 if (rs == NS_FFF)
11177 {
11178 if (is_add)
11179 do_vfp_nsyn_opcode ("fadds");
11180 else
11181 do_vfp_nsyn_opcode ("fsubs");
11182 }
11183 else
11184 {
11185 if (is_add)
11186 do_vfp_nsyn_opcode ("faddd");
11187 else
11188 do_vfp_nsyn_opcode ("fsubd");
11189 }
11190}
11191
11192/* Check operand types to see if this is a VFP instruction, and if so call
11193 PFN (). */
11194
11195static int
11196try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
11197{
11198 enum neon_shape rs;
11199 struct neon_type_el et;
11200
11201 switch (args)
11202 {
11203 case 2:
11204 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
11205 et = neon_check_type (2, rs,
11206 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11207 break;
11208
11209 case 3:
11210 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
11211 et = neon_check_type (3, rs,
11212 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11213 break;
11214
11215 default:
11216 abort ();
11217 }
11218
11219 if (et.type != NT_invtype)
11220 {
11221 pfn (rs);
11222 return SUCCESS;
11223 }
11224 else
11225 inst.error = NULL;
11226
11227 return FAIL;
11228}
11229
11230static void
11231do_vfp_nsyn_mla_mls (enum neon_shape rs)
11232{
11233 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
11234
11235 if (rs == NS_FFF)
11236 {
11237 if (is_mla)
11238 do_vfp_nsyn_opcode ("fmacs");
11239 else
11240 do_vfp_nsyn_opcode ("fmscs");
11241 }
11242 else
11243 {
11244 if (is_mla)
11245 do_vfp_nsyn_opcode ("fmacd");
11246 else
11247 do_vfp_nsyn_opcode ("fmscd");
11248 }
11249}
11250
11251static void
11252do_vfp_nsyn_mul (enum neon_shape rs)
11253{
11254 if (rs == NS_FFF)
11255 do_vfp_nsyn_opcode ("fmuls");
11256 else
11257 do_vfp_nsyn_opcode ("fmuld");
11258}
11259
11260static void
11261do_vfp_nsyn_abs_neg (enum neon_shape rs)
11262{
11263 int is_neg = (inst.instruction & 0x80) != 0;
11264 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
11265
11266 if (rs == NS_FF)
11267 {
11268 if (is_neg)
11269 do_vfp_nsyn_opcode ("fnegs");
11270 else
11271 do_vfp_nsyn_opcode ("fabss");
11272 }
11273 else
11274 {
11275 if (is_neg)
11276 do_vfp_nsyn_opcode ("fnegd");
11277 else
11278 do_vfp_nsyn_opcode ("fabsd");
11279 }
11280}
11281
11282/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11283 insns belong to Neon, and are handled elsewhere. */
11284
11285static void
11286do_vfp_nsyn_ldm_stm (int is_dbmode)
11287{
11288 int is_ldm = (inst.instruction & (1 << 20)) != 0;
11289 if (is_ldm)
11290 {
11291 if (is_dbmode)
11292 do_vfp_nsyn_opcode ("fldmdbs");
11293 else
11294 do_vfp_nsyn_opcode ("fldmias");
11295 }
11296 else
11297 {
11298 if (is_dbmode)
11299 do_vfp_nsyn_opcode ("fstmdbs");
11300 else
11301 do_vfp_nsyn_opcode ("fstmias");
11302 }
11303}
11304
11305static void
11306do_vfp_nsyn_sqrt (void)
11307{
11308 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
11309 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11310
11311 if (rs == NS_FF)
11312 do_vfp_nsyn_opcode ("fsqrts");
11313 else
11314 do_vfp_nsyn_opcode ("fsqrtd");
11315}
11316
11317static void
11318do_vfp_nsyn_div (void)
11319{
11320 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
11321 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
11322 N_F32 | N_F64 | N_KEY | N_VFP);
11323
11324 if (rs == NS_FFF)
11325 do_vfp_nsyn_opcode ("fdivs");
11326 else
11327 do_vfp_nsyn_opcode ("fdivd");
11328}
11329
11330static void
11331do_vfp_nsyn_nmul (void)
11332{
11333 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
11334 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
11335 N_F32 | N_F64 | N_KEY | N_VFP);
11336
11337 if (rs == NS_FFF)
11338 {
11339 inst.instruction = NEON_ENC_SINGLE (inst.instruction);
11340 do_vfp_sp_dyadic ();
11341 }
11342 else
11343 {
11344 inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
11345 do_vfp_dp_rd_rn_rm ();
11346 }
11347 do_vfp_cond_or_thumb ();
11348}
11349
11350static void
11351do_vfp_nsyn_cmp (void)
11352{
11353 if (inst.operands[1].isreg)
11354 {
11355 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
11356 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11357
11358 if (rs == NS_FF)
11359 {
11360 inst.instruction = NEON_ENC_SINGLE (inst.instruction);
11361 do_vfp_sp_monadic ();
11362 }
11363 else
11364 {
11365 inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
11366 do_vfp_dp_rd_rm ();
11367 }
11368 }
11369 else
11370 {
11371 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
11372 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
11373
11374 switch (inst.instruction & 0x0fffffff)
11375 {
11376 case N_MNEM_vcmp:
11377 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
11378 break;
11379 case N_MNEM_vcmpe:
11380 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
11381 break;
11382 default:
11383 abort ();
11384 }
11385
11386 if (rs == NS_FI)
11387 {
11388 inst.instruction = NEON_ENC_SINGLE (inst.instruction);
11389 do_vfp_sp_compare_z ();
11390 }
11391 else
11392 {
11393 inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
11394 do_vfp_dp_rd ();
11395 }
11396 }
11397 do_vfp_cond_or_thumb ();
11398}
11399
11400static void
11401nsyn_insert_sp (void)
11402{
11403 inst.operands[1] = inst.operands[0];
11404 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
11405 inst.operands[0].reg = 13;
11406 inst.operands[0].isreg = 1;
11407 inst.operands[0].writeback = 1;
11408 inst.operands[0].present = 1;
11409}
11410
11411static void
11412do_vfp_nsyn_push (void)
11413{
11414 nsyn_insert_sp ();
11415 if (inst.operands[1].issingle)
11416 do_vfp_nsyn_opcode ("fstmdbs");
11417 else
11418 do_vfp_nsyn_opcode ("fstmdbd");
11419}
11420
11421static void
11422do_vfp_nsyn_pop (void)
11423{
11424 nsyn_insert_sp ();
11425 if (inst.operands[1].issingle)
11426 do_vfp_nsyn_opcode ("fldmias");
11427 else
11428 do_vfp_nsyn_opcode ("fldmiad");
11429}
11430
11431/* Fix up Neon data-processing instructions, ORing in the correct bits for
11432 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11433
11434static unsigned
11435neon_dp_fixup (unsigned i)
11436{
11437 if (thumb_mode)
11438 {
11439 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11440 if (i & (1 << 24))
11441 i |= 1 << 28;
11442
11443 i &= ~(1 << 24);
11444
11445 i |= 0xef000000;
11446 }
11447 else
11448 i |= 0xf2000000;
11449
11450 return i;
11451}
11452
11453/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11454 (0, 1, 2, 3). */
11455
11456static unsigned
11457neon_logbits (unsigned x)
11458{
11459 return ffs (x) - 4;
11460}
11461
11462#define LOW4(R) ((R) & 0xf)
11463#define HI1(R) (((R) >> 4) & 1)
11464
11465/* Encode insns with bit pattern:
11466
11467 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11468 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11469
11470 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11471 different meaning for some instruction. */
11472
11473static void
11474neon_three_same (int isquad, int ubit, int size)
11475{
11476 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11477 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11478 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
11479 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
11480 inst.instruction |= LOW4 (inst.operands[2].reg);
11481 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
11482 inst.instruction |= (isquad != 0) << 6;
11483 inst.instruction |= (ubit != 0) << 24;
11484 if (size != -1)
11485 inst.instruction |= neon_logbits (size) << 20;
11486
11487 inst.instruction = neon_dp_fixup (inst.instruction);
11488}
11489
11490/* Encode instructions of the form:
11491
11492 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11493 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11494
11495 Don't write size if SIZE == -1. */
11496
11497static void
11498neon_two_same (int qbit, int ubit, int size)
11499{
11500 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11501 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11502 inst.instruction |= LOW4 (inst.operands[1].reg);
11503 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
11504 inst.instruction |= (qbit != 0) << 6;
11505 inst.instruction |= (ubit != 0) << 24;
11506
11507 if (size != -1)
11508 inst.instruction |= neon_logbits (size) << 18;
11509
11510 inst.instruction = neon_dp_fixup (inst.instruction);
11511}
11512
11513/* Neon instruction encoders, in approximate order of appearance. */
11514
11515static void
11516do_neon_dyadic_i_su (void)
11517{
11518 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11519 struct neon_type_el et = neon_check_type (3, rs,
11520 N_EQK, N_EQK, N_SU_32 | N_KEY);
11521 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11522}
11523
11524static void
11525do_neon_dyadic_i64_su (void)
11526{
11527 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11528 struct neon_type_el et = neon_check_type (3, rs,
11529 N_EQK, N_EQK, N_SU_ALL | N_KEY);
11530 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11531}
11532
11533static void
11534neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
11535 unsigned immbits)
11536{
11537 unsigned size = et.size >> 3;
11538 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11539 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11540 inst.instruction |= LOW4 (inst.operands[1].reg);
11541 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
11542 inst.instruction |= (isquad != 0) << 6;
11543 inst.instruction |= immbits << 16;
11544 inst.instruction |= (size >> 3) << 7;
11545 inst.instruction |= (size & 0x7) << 19;
11546 if (write_ubit)
11547 inst.instruction |= (uval != 0) << 24;
11548
11549 inst.instruction = neon_dp_fixup (inst.instruction);
11550}
11551
11552static void
11553do_neon_shl_imm (void)
11554{
11555 if (!inst.operands[2].isreg)
11556 {
11557 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
11558 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
11559 inst.instruction = NEON_ENC_IMMED (inst.instruction);
11560 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
11561 }
11562 else
11563 {
11564 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11565 struct neon_type_el et = neon_check_type (3, rs,
11566 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
11567 unsigned int tmp;
11568
11569 /* VSHL/VQSHL 3-register variants have syntax such as:
11570 vshl.xx Dd, Dm, Dn
11571 whereas other 3-register operations encoded by neon_three_same have
11572 syntax like:
11573 vadd.xx Dd, Dn, Dm
11574 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
11575 here. */
11576 tmp = inst.operands[2].reg;
11577 inst.operands[2].reg = inst.operands[1].reg;
11578 inst.operands[1].reg = tmp;
11579 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
11580 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11581 }
11582}
11583
11584static void
11585do_neon_qshl_imm (void)
11586{
11587 if (!inst.operands[2].isreg)
11588 {
11589 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
11590 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
11591
11592 inst.instruction = NEON_ENC_IMMED (inst.instruction);
11593 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
11594 inst.operands[2].imm);
11595 }
11596 else
11597 {
11598 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11599 struct neon_type_el et = neon_check_type (3, rs,
11600 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
11601 unsigned int tmp;
11602
11603 /* See note in do_neon_shl_imm. */
11604 tmp = inst.operands[2].reg;
11605 inst.operands[2].reg = inst.operands[1].reg;
11606 inst.operands[1].reg = tmp;
11607 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
11608 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11609 }
11610}
11611
11612static void
11613do_neon_rshl (void)
11614{
11615 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11616 struct neon_type_el et = neon_check_type (3, rs,
11617 N_EQK, N_EQK, N_SU_ALL | N_KEY);
11618 unsigned int tmp;
11619
11620 tmp = inst.operands[2].reg;
11621 inst.operands[2].reg = inst.operands[1].reg;
11622 inst.operands[1].reg = tmp;
11623 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11624}
11625
11626static int
11627neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
11628{
11629 /* Handle .I8 pseudo-instructions. */
11630 if (size == 8)
11631 {
11632 /* Unfortunately, this will make everything apart from zero out-of-range.
11633 FIXME is this the intended semantics? There doesn't seem much point in
11634 accepting .I8 if so. */
11635 immediate |= immediate << 8;
11636 size = 16;
11637 }
11638
11639 if (size >= 32)
11640 {
11641 if (immediate == (immediate & 0x000000ff))
11642 {
11643 *immbits = immediate;
11644 return 0x1;
11645 }
11646 else if (immediate == (immediate & 0x0000ff00))
11647 {
11648 *immbits = immediate >> 8;
11649 return 0x3;
11650 }
11651 else if (immediate == (immediate & 0x00ff0000))
11652 {
11653 *immbits = immediate >> 16;
11654 return 0x5;
11655 }
11656 else if (immediate == (immediate & 0xff000000))
11657 {
11658 *immbits = immediate >> 24;
11659 return 0x7;
11660 }
11661 if ((immediate & 0xffff) != (immediate >> 16))
11662 goto bad_immediate;
11663 immediate &= 0xffff;
11664 }
11665
11666 if (immediate == (immediate & 0x000000ff))
11667 {
11668 *immbits = immediate;
11669 return 0x9;
11670 }
11671 else if (immediate == (immediate & 0x0000ff00))
11672 {
11673 *immbits = immediate >> 8;
11674 return 0xb;
11675 }
11676
11677 bad_immediate:
11678 first_error (_("immediate value out of range"));
11679 return FAIL;
11680}
11681
11682/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11683 A, B, C, D. */
11684
11685static int
11686neon_bits_same_in_bytes (unsigned imm)
11687{
11688 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
11689 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
11690 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
11691 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
11692}
11693
11694/* For immediate of above form, return 0bABCD. */
11695
11696static unsigned
11697neon_squash_bits (unsigned imm)
11698{
11699 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
11700 | ((imm & 0x01000000) >> 21);
11701}
11702
11703/* Compress quarter-float representation to 0b...000 abcdefgh. */
11704
11705static unsigned
11706neon_qfloat_bits (unsigned imm)
11707{
11708 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
11709}
11710
11711/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11712 the instruction. *OP is passed as the initial value of the op field, and
11713 may be set to a different value depending on the constant (i.e.
11714 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11715 MVN). If the immediate looks like a repeated parttern then also
11716 try smaller element sizes. */
11717
11718static int
11719neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
11720 unsigned *immbits, int *op, int size,
11721 enum neon_el_type type)
11722{
11723 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
11724 float. */
11725 if (type == NT_float && !float_p)
11726 return FAIL;
11727
11728 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
11729 {
11730 if (size != 32 || *op == 1)
11731 return FAIL;
11732 *immbits = neon_qfloat_bits (immlo);
11733 return 0xf;
11734 }
11735
11736 if (size == 64)
11737 {
11738 if (neon_bits_same_in_bytes (immhi)
11739 && neon_bits_same_in_bytes (immlo))
11740 {
11741 if (*op == 1)
11742 return FAIL;
11743 *immbits = (neon_squash_bits (immhi) << 4)
11744 | neon_squash_bits (immlo);
11745 *op = 1;
11746 return 0xe;
11747 }
11748
11749 if (immhi != immlo)
11750 return FAIL;
11751 }
11752
11753 if (size >= 32)
11754 {
11755 if (immlo == (immlo & 0x000000ff))
11756 {
11757 *immbits = immlo;
11758 return 0x0;
11759 }
11760 else if (immlo == (immlo & 0x0000ff00))
11761 {
11762 *immbits = immlo >> 8;
11763 return 0x2;
11764 }
11765 else if (immlo == (immlo & 0x00ff0000))
11766 {
11767 *immbits = immlo >> 16;
11768 return 0x4;
11769 }
11770 else if (immlo == (immlo & 0xff000000))
11771 {
11772 *immbits = immlo >> 24;
11773 return 0x6;
11774 }
11775 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
11776 {
11777 *immbits = (immlo >> 8) & 0xff;
11778 return 0xc;
11779 }
11780 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
11781 {
11782 *immbits = (immlo >> 16) & 0xff;
11783 return 0xd;
11784 }
11785
11786 if ((immlo & 0xffff) != (immlo >> 16))
11787 return FAIL;
11788 immlo &= 0xffff;
11789 }
11790
11791 if (size >= 16)
11792 {
11793 if (immlo == (immlo & 0x000000ff))
11794 {
11795 *immbits = immlo;
11796 return 0x8;
11797 }
11798 else if (immlo == (immlo & 0x0000ff00))
11799 {
11800 *immbits = immlo >> 8;
11801 return 0xa;
11802 }
11803
11804 if ((immlo & 0xff) != (immlo >> 8))
11805 return FAIL;
11806 immlo &= 0xff;
11807 }
11808
11809 if (immlo == (immlo & 0x000000ff))
11810 {
11811 /* Don't allow MVN with 8-bit immediate. */
11812 if (*op == 1)
11813 return FAIL;
11814 *immbits = immlo;
11815 return 0xe;
11816 }
11817
11818 return FAIL;
11819}
11820
11821/* Write immediate bits [7:0] to the following locations:
11822
11823 |28/24|23 19|18 16|15 4|3 0|
11824 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11825
11826 This function is used by VMOV/VMVN/VORR/VBIC. */
11827
11828static void
11829neon_write_immbits (unsigned immbits)
11830{
11831 inst.instruction |= immbits & 0xf;
11832 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
11833 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
11834}
11835
11836/* Invert low-order SIZE bits of XHI:XLO. */
11837
11838static void
11839neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
11840{
11841 unsigned immlo = xlo ? *xlo : 0;
11842 unsigned immhi = xhi ? *xhi : 0;
11843
11844 switch (size)
11845 {
11846 case 8:
11847 immlo = (~immlo) & 0xff;
11848 break;
11849
11850 case 16:
11851 immlo = (~immlo) & 0xffff;
11852 break;
11853
11854 case 64:
11855 immhi = (~immhi) & 0xffffffff;
11856 /* fall through. */
11857
11858 case 32:
11859 immlo = (~immlo) & 0xffffffff;
11860 break;
11861
11862 default:
11863 abort ();
11864 }
11865
11866 if (xlo)
11867 *xlo = immlo;
11868
11869 if (xhi)
11870 *xhi = immhi;
11871}
11872
11873static void
11874do_neon_logic (void)
11875{
11876 if (inst.operands[2].present && inst.operands[2].isreg)
11877 {
11878 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11879 neon_check_type (3, rs, N_IGNORE_TYPE);
11880 /* U bit and size field were set as part of the bitmask. */
11881 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
11882 neon_three_same (neon_quad (rs), 0, -1);
11883 }
11884 else
11885 {
11886 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
11887 struct neon_type_el et = neon_check_type (2, rs,
11888 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
11889 enum neon_opc opcode = inst.instruction & 0x0fffffff;
11890 unsigned immbits;
11891 int cmode;
11892
11893 if (et.type == NT_invtype)
11894 return;
11895
11896 inst.instruction = NEON_ENC_IMMED (inst.instruction);
11897
11898 immbits = inst.operands[1].imm;
11899 if (et.size == 64)
11900 {
11901 /* .i64 is a pseudo-op, so the immediate must be a repeating
11902 pattern. */
11903 if (immbits != (inst.operands[1].regisimm ?
11904 inst.operands[1].reg : 0))
11905 {
11906 /* Set immbits to an invalid constant. */
11907 immbits = 0xdeadbeef;
11908 }
11909 }
11910
11911 switch (opcode)
11912 {
11913 case N_MNEM_vbic:
11914 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
11915 break;
11916
11917 case N_MNEM_vorr:
11918 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
11919 break;
11920
11921 case N_MNEM_vand:
11922 /* Pseudo-instruction for VBIC. */
11923 neon_invert_size (&immbits, 0, et.size);
11924 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
11925 break;
11926
11927 case N_MNEM_vorn:
11928 /* Pseudo-instruction for VORR. */
11929 neon_invert_size (&immbits, 0, et.size);
11930 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
11931 break;
11932
11933 default:
11934 abort ();
11935 }
11936
11937 if (cmode == FAIL)
11938 return;
11939
11940 inst.instruction |= neon_quad (rs) << 6;
11941 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11942 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11943 inst.instruction |= cmode << 8;
11944 neon_write_immbits (immbits);
11945
11946 inst.instruction = neon_dp_fixup (inst.instruction);
11947 }
11948}
11949
11950static void
11951do_neon_bitfield (void)
11952{
11953 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11954 neon_check_type (3, rs, N_IGNORE_TYPE);
11955 neon_three_same (neon_quad (rs), 0, -1);
11956}
11957
11958static void
11959neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
11960 unsigned destbits)
11961{
11962 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11963 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
11964 types | N_KEY);
11965 if (et.type == NT_float)
11966 {
11967 inst.instruction = NEON_ENC_FLOAT (inst.instruction);
11968 neon_three_same (neon_quad (rs), 0, -1);
11969 }
11970 else
11971 {
11972 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
11973 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
11974 }
11975}
11976
11977static void
11978do_neon_dyadic_if_su (void)
11979{
11980 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
11981}
11982
11983static void
11984do_neon_dyadic_if_su_d (void)
11985{
11986 /* This version only allow D registers, but that constraint is enforced during
11987 operand parsing so we don't need to do anything extra here. */
11988 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
11989}
11990
11991static void
11992do_neon_dyadic_if_i_d (void)
11993{
11994 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11995 affected if we specify unsigned args. */
11996 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
11997}
11998
11999enum vfp_or_neon_is_neon_bits
12000{
12001 NEON_CHECK_CC = 1,
12002 NEON_CHECK_ARCH = 2
12003};
12004
12005/* Call this function if an instruction which may have belonged to the VFP or
12006 Neon instruction sets, but turned out to be a Neon instruction (due to the
12007 operand types involved, etc.). We have to check and/or fix-up a couple of
12008 things:
12009
12010 - Make sure the user hasn't attempted to make a Neon instruction
12011 conditional.
12012 - Alter the value in the condition code field if necessary.
12013 - Make sure that the arch supports Neon instructions.
12014
12015 Which of these operations take place depends on bits from enum
12016 vfp_or_neon_is_neon_bits.
12017
12018 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12019 current instruction's condition is COND_ALWAYS, the condition field is
12020 changed to inst.uncond_value. This is necessary because instructions shared
12021 between VFP and Neon may be conditional for the VFP variants only, and the
12022 unconditional Neon version must have, e.g., 0xF in the condition field. */
12023
12024static int
12025vfp_or_neon_is_neon (unsigned check)
12026{
12027 /* Conditions are always legal in Thumb mode (IT blocks). */
12028 if (!thumb_mode && (check & NEON_CHECK_CC))
12029 {
12030 if (inst.cond != COND_ALWAYS)
12031 {
12032 first_error (_(BAD_COND));
12033 return FAIL;
12034 }
12035 if (inst.uncond_value != -1)
12036 inst.instruction |= inst.uncond_value << 28;
12037 }
12038
12039 if ((check & NEON_CHECK_ARCH)
12040 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
12041 {
12042 first_error (_(BAD_FPU));
12043 return FAIL;
12044 }
12045
12046 return SUCCESS;
12047}
12048
12049static void
12050do_neon_addsub_if_i (void)
12051{
12052 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
12053 return;
12054
12055 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12056 return;
12057
12058 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12059 affected if we specify unsigned args. */
12060 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
12061}
12062
12063/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12064 result to be:
12065 V<op> A,B (A is operand 0, B is operand 2)
12066 to mean:
12067 V<op> A,B,A
12068 not:
12069 V<op> A,B,B
12070 so handle that case specially. */
12071
12072static void
12073neon_exchange_operands (void)
12074{
12075 void *scratch = alloca (sizeof (inst.operands[0]));
12076 if (inst.operands[1].present)
12077 {
12078 /* Swap operands[1] and operands[2]. */
12079 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
12080 inst.operands[1] = inst.operands[2];
12081 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
12082 }
12083 else
12084 {
12085 inst.operands[1] = inst.operands[2];
12086 inst.operands[2] = inst.operands[0];
12087 }
12088}
12089
12090static void
12091neon_compare (unsigned regtypes, unsigned immtypes, int invert)
12092{
12093 if (inst.operands[2].isreg)
12094 {
12095 if (invert)
12096 neon_exchange_operands ();
12097 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
12098 }
12099 else
12100 {
12101 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12102 struct neon_type_el et = neon_check_type (2, rs,
12103 N_EQK | N_SIZ, immtypes | N_KEY);
12104
12105 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12106 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12107 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12108 inst.instruction |= LOW4 (inst.operands[1].reg);
12109 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12110 inst.instruction |= neon_quad (rs) << 6;
12111 inst.instruction |= (et.type == NT_float) << 10;
12112 inst.instruction |= neon_logbits (et.size) << 18;
12113
12114 inst.instruction = neon_dp_fixup (inst.instruction);
12115 }
12116}
12117
12118static void
12119do_neon_cmp (void)
12120{
12121 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
12122}
12123
12124static void
12125do_neon_cmp_inv (void)
12126{
12127 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
12128}
12129
12130static void
12131do_neon_ceq (void)
12132{
12133 neon_compare (N_IF_32, N_IF_32, FALSE);
12134}
12135
12136/* For multiply instructions, we have the possibility of 16-bit or 32-bit
12137 scalars, which are encoded in 5 bits, M : Rm.
12138 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12139 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12140 index in M. */
12141
12142static unsigned
12143neon_scalar_for_mul (unsigned scalar, unsigned elsize)
12144{
12145 unsigned regno = NEON_SCALAR_REG (scalar);
12146 unsigned elno = NEON_SCALAR_INDEX (scalar);
12147
12148 switch (elsize)
12149 {
12150 case 16:
12151 if (regno > 7 || elno > 3)
12152 goto bad_scalar;
12153 return regno | (elno << 3);
12154
12155 case 32:
12156 if (regno > 15 || elno > 1)
12157 goto bad_scalar;
12158 return regno | (elno << 4);
12159
12160 default:
12161 bad_scalar:
12162 first_error (_("scalar out of range for multiply instruction"));
12163 }
12164
12165 return 0;
12166}
12167
12168/* Encode multiply / multiply-accumulate scalar instructions. */
12169
12170static void
12171neon_mul_mac (struct neon_type_el et, int ubit)
12172{
12173 unsigned scalar;
12174
12175 /* Give a more helpful error message if we have an invalid type. */
12176 if (et.type == NT_invtype)
12177 return;
12178
12179 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
12180 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12181 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12182 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12183 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12184 inst.instruction |= LOW4 (scalar);
12185 inst.instruction |= HI1 (scalar) << 5;
12186 inst.instruction |= (et.type == NT_float) << 8;
12187 inst.instruction |= neon_logbits (et.size) << 20;
12188 inst.instruction |= (ubit != 0) << 24;
12189
12190 inst.instruction = neon_dp_fixup (inst.instruction);
12191}
12192
12193static void
12194do_neon_mac_maybe_scalar (void)
12195{
12196 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
12197 return;
12198
12199 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12200 return;
12201
12202 if (inst.operands[2].isscalar)
12203 {
12204 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
12205 struct neon_type_el et = neon_check_type (3, rs,
12206 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
12207 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
12208 neon_mul_mac (et, neon_quad (rs));
12209 }
12210 else
12211 {
12212 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12213 affected if we specify unsigned args. */
12214 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
12215 }
12216}
12217
12218static void
12219do_neon_tst (void)
12220{
12221 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12222 struct neon_type_el et = neon_check_type (3, rs,
12223 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
12224 neon_three_same (neon_quad (rs), 0, et.size);
12225}
12226
12227/* VMUL with 3 registers allows the P8 type. The scalar version supports the
12228 same types as the MAC equivalents. The polynomial type for this instruction
12229 is encoded the same as the integer type. */
12230
12231static void
12232do_neon_mul (void)
12233{
12234 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
12235 return;
12236
12237 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12238 return;
12239
12240 if (inst.operands[2].isscalar)
12241 do_neon_mac_maybe_scalar ();
12242 else
12243 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
12244}
12245
12246static void
12247do_neon_qdmulh (void)
12248{
12249 if (inst.operands[2].isscalar)
12250 {
12251 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
12252 struct neon_type_el et = neon_check_type (3, rs,
12253 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
12254 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
12255 neon_mul_mac (et, neon_quad (rs));
12256 }
12257 else
12258 {
12259 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12260 struct neon_type_el et = neon_check_type (3, rs,
12261 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
12262 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12263 /* The U bit (rounding) comes from bit mask. */
12264 neon_three_same (neon_quad (rs), 0, et.size);
12265 }
12266}
12267
12268static void
12269do_neon_fcmp_absolute (void)
12270{
12271 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12272 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
12273 /* Size field comes from bit mask. */
12274 neon_three_same (neon_quad (rs), 1, -1);
12275}
12276
12277static void
12278do_neon_fcmp_absolute_inv (void)
12279{
12280 neon_exchange_operands ();
12281 do_neon_fcmp_absolute ();
12282}
12283
12284static void
12285do_neon_step (void)
12286{
12287 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12288 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
12289 neon_three_same (neon_quad (rs), 0, -1);
12290}
12291
12292static void
12293do_neon_abs_neg (void)
12294{
12295 enum neon_shape rs;
12296 struct neon_type_el et;
12297
12298 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
12299 return;
12300
12301 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12302 return;
12303
12304 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
12305 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
12306
12307 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12308 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12309 inst.instruction |= LOW4 (inst.operands[1].reg);
12310 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12311 inst.instruction |= neon_quad (rs) << 6;
12312 inst.instruction |= (et.type == NT_float) << 10;
12313 inst.instruction |= neon_logbits (et.size) << 18;
12314
12315 inst.instruction = neon_dp_fixup (inst.instruction);
12316}
12317
12318static void
12319do_neon_sli (void)
12320{
12321 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12322 struct neon_type_el et = neon_check_type (2, rs,
12323 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
12324 int imm = inst.operands[2].imm;
12325 constraint (imm < 0 || (unsigned)imm >= et.size,
12326 _("immediate out of range for insert"));
12327 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
12328}
12329
12330static void
12331do_neon_sri (void)
12332{
12333 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12334 struct neon_type_el et = neon_check_type (2, rs,
12335 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
12336 int imm = inst.operands[2].imm;
12337 constraint (imm < 1 || (unsigned)imm > et.size,
12338 _("immediate out of range for insert"));
12339 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
12340}
12341
12342static void
12343do_neon_qshlu_imm (void)
12344{
12345 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12346 struct neon_type_el et = neon_check_type (2, rs,
12347 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
12348 int imm = inst.operands[2].imm;
12349 constraint (imm < 0 || (unsigned)imm >= et.size,
12350 _("immediate out of range for shift"));
12351 /* Only encodes the 'U present' variant of the instruction.
12352 In this case, signed types have OP (bit 8) set to 0.
12353 Unsigned types have OP set to 1. */
12354 inst.instruction |= (et.type == NT_unsigned) << 8;
12355 /* The rest of the bits are the same as other immediate shifts. */
12356 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
12357}
12358
12359static void
12360do_neon_qmovn (void)
12361{
12362 struct neon_type_el et = neon_check_type (2, NS_DQ,
12363 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
12364 /* Saturating move where operands can be signed or unsigned, and the
12365 destination has the same signedness. */
12366 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12367 if (et.type == NT_unsigned)
12368 inst.instruction |= 0xc0;
12369 else
12370 inst.instruction |= 0x80;
12371 neon_two_same (0, 1, et.size / 2);
12372}
12373
12374static void
12375do_neon_qmovun (void)
12376{
12377 struct neon_type_el et = neon_check_type (2, NS_DQ,
12378 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
12379 /* Saturating move with unsigned results. Operands must be signed. */
12380 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12381 neon_two_same (0, 1, et.size / 2);
12382}
12383
12384static void
12385do_neon_rshift_sat_narrow (void)
12386{
12387 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12388 or unsigned. If operands are unsigned, results must also be unsigned. */
12389 struct neon_type_el et = neon_check_type (2, NS_DQI,
12390 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
12391 int imm = inst.operands[2].imm;
12392 /* This gets the bounds check, size encoding and immediate bits calculation
12393 right. */
12394 et.size /= 2;
12395
12396 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12397 VQMOVN.I<size> <Dd>, <Qm>. */
12398 if (imm == 0)
12399 {
12400 inst.operands[2].present = 0;
12401 inst.instruction = N_MNEM_vqmovn;
12402 do_neon_qmovn ();
12403 return;
12404 }
12405
12406 constraint (imm < 1 || (unsigned)imm > et.size,
12407 _("immediate out of range"));
12408 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
12409}
12410
12411static void
12412do_neon_rshift_sat_narrow_u (void)
12413{
12414 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12415 or unsigned. If operands are unsigned, results must also be unsigned. */
12416 struct neon_type_el et = neon_check_type (2, NS_DQI,
12417 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
12418 int imm = inst.operands[2].imm;
12419 /* This gets the bounds check, size encoding and immediate bits calculation
12420 right. */
12421 et.size /= 2;
12422
12423 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12424 VQMOVUN.I<size> <Dd>, <Qm>. */
12425 if (imm == 0)
12426 {
12427 inst.operands[2].present = 0;
12428 inst.instruction = N_MNEM_vqmovun;
12429 do_neon_qmovun ();
12430 return;
12431 }
12432
12433 constraint (imm < 1 || (unsigned)imm > et.size,
12434 _("immediate out of range"));
12435 /* FIXME: The manual is kind of unclear about what value U should have in
12436 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12437 must be 1. */
12438 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
12439}
12440
12441static void
12442do_neon_movn (void)
12443{
12444 struct neon_type_el et = neon_check_type (2, NS_DQ,
12445 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
12446 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12447 neon_two_same (0, 1, et.size / 2);
12448}
12449
12450static void
12451do_neon_rshift_narrow (void)
12452{
12453 struct neon_type_el et = neon_check_type (2, NS_DQI,
12454 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
12455 int imm = inst.operands[2].imm;
12456 /* This gets the bounds check, size encoding and immediate bits calculation
12457 right. */
12458 et.size /= 2;
12459
12460 /* If immediate is zero then we are a pseudo-instruction for
12461 VMOVN.I<size> <Dd>, <Qm> */
12462 if (imm == 0)
12463 {
12464 inst.operands[2].present = 0;
12465 inst.instruction = N_MNEM_vmovn;
12466 do_neon_movn ();
12467 return;
12468 }
12469
12470 constraint (imm < 1 || (unsigned)imm > et.size,
12471 _("immediate out of range for narrowing operation"));
12472 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
12473}
12474
12475static void
12476do_neon_shll (void)
12477{
12478 /* FIXME: Type checking when lengthening. */
12479 struct neon_type_el et = neon_check_type (2, NS_QDI,
12480 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
12481 unsigned imm = inst.operands[2].imm;
12482
12483 if (imm == et.size)
12484 {
12485 /* Maximum shift variant. */
12486 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12487 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12488 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12489 inst.instruction |= LOW4 (inst.operands[1].reg);
12490 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12491 inst.instruction |= neon_logbits (et.size) << 18;
12492
12493 inst.instruction = neon_dp_fixup (inst.instruction);
12494 }
12495 else
12496 {
12497 /* A more-specific type check for non-max versions. */
12498 et = neon_check_type (2, NS_QDI,
12499 N_EQK | N_DBL, N_SU_32 | N_KEY);
12500 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12501 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
12502 }
12503}
12504
12505/* Check the various types for the VCVT instruction, and return which version
12506 the current instruction is. */
12507
12508static int
12509neon_cvt_flavour (enum neon_shape rs)
12510{
12511#define CVT_VAR(C,X,Y) \
12512 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12513 if (et.type != NT_invtype) \
12514 { \
12515 inst.error = NULL; \
12516 return (C); \
12517 }
12518 struct neon_type_el et;
12519 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
12520 || rs == NS_FF) ? N_VFP : 0;
12521 /* The instruction versions which take an immediate take one register
12522 argument, which is extended to the width of the full register. Thus the
12523 "source" and "destination" registers must have the same width. Hack that
12524 here by making the size equal to the key (wider, in this case) operand. */
12525 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
12526
12527 CVT_VAR (0, N_S32, N_F32);
12528 CVT_VAR (1, N_U32, N_F32);
12529 CVT_VAR (2, N_F32, N_S32);
12530 CVT_VAR (3, N_F32, N_U32);
12531
12532 whole_reg = N_VFP;
12533
12534 /* VFP instructions. */
12535 CVT_VAR (4, N_F32, N_F64);
12536 CVT_VAR (5, N_F64, N_F32);
12537 CVT_VAR (6, N_S32, N_F64 | key);
12538 CVT_VAR (7, N_U32, N_F64 | key);
12539 CVT_VAR (8, N_F64 | key, N_S32);
12540 CVT_VAR (9, N_F64 | key, N_U32);
12541 /* VFP instructions with bitshift. */
12542 CVT_VAR (10, N_F32 | key, N_S16);
12543 CVT_VAR (11, N_F32 | key, N_U16);
12544 CVT_VAR (12, N_F64 | key, N_S16);
12545 CVT_VAR (13, N_F64 | key, N_U16);
12546 CVT_VAR (14, N_S16, N_F32 | key);
12547 CVT_VAR (15, N_U16, N_F32 | key);
12548 CVT_VAR (16, N_S16, N_F64 | key);
12549 CVT_VAR (17, N_U16, N_F64 | key);
12550
12551 return -1;
12552#undef CVT_VAR
12553}
12554
12555/* Neon-syntax VFP conversions. */
12556
12557static void
12558do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
12559{
12560 const char *opname = 0;
12561
12562 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
12563 {
12564 /* Conversions with immediate bitshift. */
12565 const char *enc[] =
12566 {
12567 "ftosls",
12568 "ftouls",
12569 "fsltos",
12570 "fultos",
12571 NULL,
12572 NULL,
12573 "ftosld",
12574 "ftould",
12575 "fsltod",
12576 "fultod",
12577 "fshtos",
12578 "fuhtos",
12579 "fshtod",
12580 "fuhtod",
12581 "ftoshs",
12582 "ftouhs",
12583 "ftoshd",
12584 "ftouhd"
12585 };
12586
12587 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
12588 {
12589 opname = enc[flavour];
12590 constraint (inst.operands[0].reg != inst.operands[1].reg,
12591 _("operands 0 and 1 must be the same register"));
12592 inst.operands[1] = inst.operands[2];
12593 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
12594 }
12595 }
12596 else
12597 {
12598 /* Conversions without bitshift. */
12599 const char *enc[] =
12600 {
12601 "ftosis",
12602 "ftouis",
12603 "fsitos",
12604 "fuitos",
12605 "fcvtsd",
12606 "fcvtds",
12607 "ftosid",
12608 "ftouid",
12609 "fsitod",
12610 "fuitod"
12611 };
12612
12613 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
12614 opname = enc[flavour];
12615 }
12616
12617 if (opname)
12618 do_vfp_nsyn_opcode (opname);
12619}
12620
12621static void
12622do_vfp_nsyn_cvtz (void)
12623{
12624 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
12625 int flavour = neon_cvt_flavour (rs);
12626 const char *enc[] =
12627 {
12628 "ftosizs",
12629 "ftouizs",
12630 NULL,
12631 NULL,
12632 NULL,
12633 NULL,
12634 "ftosizd",
12635 "ftouizd"
12636 };
12637
12638 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
12639 do_vfp_nsyn_opcode (enc[flavour]);
12640}
12641
12642static void
12643do_neon_cvt (void)
12644{
12645 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
12646 NS_FD, NS_DF, NS_FF, NS_NULL);
12647 int flavour = neon_cvt_flavour (rs);
12648
12649 /* VFP rather than Neon conversions. */
12650 if (flavour >= 4)
12651 {
12652 do_vfp_nsyn_cvt (rs, flavour);
12653 return;
12654 }
12655
12656 switch (rs)
12657 {
12658 case NS_DDI:
12659 case NS_QQI:
12660 {
12661 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12662 return;
12663
12664 /* Fixed-point conversion with #0 immediate is encoded as an
12665 integer conversion. */
12666 if (inst.operands[2].present && inst.operands[2].imm == 0)
12667 goto int_encode;
12668 unsigned immbits = 32 - inst.operands[2].imm;
12669 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12670 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12671 if (flavour != -1)
12672 inst.instruction |= enctab[flavour];
12673 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12674 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12675 inst.instruction |= LOW4 (inst.operands[1].reg);
12676 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12677 inst.instruction |= neon_quad (rs) << 6;
12678 inst.instruction |= 1 << 21;
12679 inst.instruction |= immbits << 16;
12680
12681 inst.instruction = neon_dp_fixup (inst.instruction);
12682 }
12683 break;
12684
12685 case NS_DD:
12686 case NS_QQ:
12687 int_encode:
12688 {
12689 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
12690
12691 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12692
12693 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12694 return;
12695
12696 if (flavour != -1)
12697 inst.instruction |= enctab[flavour];
12698
12699 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12700 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12701 inst.instruction |= LOW4 (inst.operands[1].reg);
12702 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12703 inst.instruction |= neon_quad (rs) << 6;
12704 inst.instruction |= 2 << 18;
12705
12706 inst.instruction = neon_dp_fixup (inst.instruction);
12707 }
12708 break;
12709
12710 default:
12711 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12712 do_vfp_nsyn_cvt (rs, flavour);
12713 }
12714}
12715
12716static void
12717neon_move_immediate (void)
12718{
12719 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
12720 struct neon_type_el et = neon_check_type (2, rs,
12721 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
12722 unsigned immlo, immhi = 0, immbits;
12723 int op, cmode, float_p;
12724
12725 constraint (et.type == NT_invtype,
12726 _("operand size must be specified for immediate VMOV"));
12727
12728 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12729 op = (inst.instruction & (1 << 5)) != 0;
12730
12731 immlo = inst.operands[1].imm;
12732 if (inst.operands[1].regisimm)
12733 immhi = inst.operands[1].reg;
12734
12735 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
12736 _("immediate has bits set outside the operand size"));
12737
12738 float_p = inst.operands[1].immisfloat;
12739
12740 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
12741 et.size, et.type)) == FAIL)
12742 {
12743 /* Invert relevant bits only. */
12744 neon_invert_size (&immlo, &immhi, et.size);
12745 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12746 with one or the other; those cases are caught by
12747 neon_cmode_for_move_imm. */
12748 op = !op;
12749 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
12750 &op, et.size, et.type)) == FAIL)
12751 {
12752 first_error (_("immediate out of range"));
12753 return;
12754 }
12755 }
12756
12757 inst.instruction &= ~(1 << 5);
12758 inst.instruction |= op << 5;
12759
12760 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12761 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12762 inst.instruction |= neon_quad (rs) << 6;
12763 inst.instruction |= cmode << 8;
12764
12765 neon_write_immbits (immbits);
12766}
12767
12768static void
12769do_neon_mvn (void)
12770{
12771 if (inst.operands[1].isreg)
12772 {
12773 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
12774
12775 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12776 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12777 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12778 inst.instruction |= LOW4 (inst.operands[1].reg);
12779 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12780 inst.instruction |= neon_quad (rs) << 6;
12781 }
12782 else
12783 {
12784 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12785 neon_move_immediate ();
12786 }
12787
12788 inst.instruction = neon_dp_fixup (inst.instruction);
12789}
12790
12791/* Encode instructions of form:
12792
12793 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12794 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm |
12795
12796*/
12797
12798static void
12799neon_mixed_length (struct neon_type_el et, unsigned size)
12800{
12801 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12802 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12803 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12804 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12805 inst.instruction |= LOW4 (inst.operands[2].reg);
12806 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
12807 inst.instruction |= (et.type == NT_unsigned) << 24;
12808 inst.instruction |= neon_logbits (size) << 20;
12809
12810 inst.instruction = neon_dp_fixup (inst.instruction);
12811}
12812
12813static void
12814do_neon_dyadic_long (void)
12815{
12816 /* FIXME: Type checking for lengthening op. */
12817 struct neon_type_el et = neon_check_type (3, NS_QDD,
12818 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
12819 neon_mixed_length (et, et.size);
12820}
12821
12822static void
12823do_neon_abal (void)
12824{
12825 struct neon_type_el et = neon_check_type (3, NS_QDD,
12826 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
12827 neon_mixed_length (et, et.size);
12828}
12829
12830static void
12831neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
12832{
12833 if (inst.operands[2].isscalar)
12834 {
12835 struct neon_type_el et = neon_check_type (3, NS_QDS,
12836 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
12837 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
12838 neon_mul_mac (et, et.type == NT_unsigned);
12839 }
12840 else
12841 {
12842 struct neon_type_el et = neon_check_type (3, NS_QDD,
12843 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
12844 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12845 neon_mixed_length (et, et.size);
12846 }
12847}
12848
12849static void
12850do_neon_mac_maybe_scalar_long (void)
12851{
12852 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
12853}
12854
12855static void
12856do_neon_dyadic_wide (void)
12857{
12858 struct neon_type_el et = neon_check_type (3, NS_QQD,
12859 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
12860 neon_mixed_length (et, et.size);
12861}
12862
12863static void
12864do_neon_dyadic_narrow (void)
12865{
12866 struct neon_type_el et = neon_check_type (3, NS_QDD,
12867 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
12868 /* Operand sign is unimportant, and the U bit is part of the opcode,
12869 so force the operand type to integer. */
12870 et.type = NT_integer;
12871 neon_mixed_length (et, et.size / 2);
12872}
12873
12874static void
12875do_neon_mul_sat_scalar_long (void)
12876{
12877 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
12878}
12879
12880static void
12881do_neon_vmull (void)
12882{
12883 if (inst.operands[2].isscalar)
12884 do_neon_mac_maybe_scalar_long ();
12885 else
12886 {
12887 struct neon_type_el et = neon_check_type (3, NS_QDD,
12888 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
12889 if (et.type == NT_poly)
12890 inst.instruction = NEON_ENC_POLY (inst.instruction);
12891 else
12892 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12893 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12894 zero. Should be OK as-is. */
12895 neon_mixed_length (et, et.size);
12896 }
12897}
12898
12899static void
12900do_neon_ext (void)
12901{
12902 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
12903 struct neon_type_el et = neon_check_type (3, rs,
12904 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
12905 unsigned imm = (inst.operands[3].imm * et.size) / 8;
12906 constraint (imm >= (neon_quad (rs) ? 16 : 8), _("shift out of range"));
12907 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12908 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12909 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12910 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12911 inst.instruction |= LOW4 (inst.operands[2].reg);
12912 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
12913 inst.instruction |= neon_quad (rs) << 6;
12914 inst.instruction |= imm << 8;
12915
12916 inst.instruction = neon_dp_fixup (inst.instruction);
12917}
12918
12919static void
12920do_neon_rev (void)
12921{
12922 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
12923 struct neon_type_el et = neon_check_type (2, rs,
12924 N_EQK, N_8 | N_16 | N_32 | N_KEY);
12925 unsigned op = (inst.instruction >> 7) & 3;
12926 /* N (width of reversed regions) is encoded as part of the bitmask. We
12927 extract it here to check the elements to be reversed are smaller.
12928 Otherwise we'd get a reserved instruction. */
12929 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
12930 assert (elsize != 0);
12931 constraint (et.size >= elsize,
12932 _("elements must be smaller than reversal region"));
12933 neon_two_same (neon_quad (rs), 1, et.size);
12934}
12935
12936static void
12937do_neon_dup (void)
12938{
12939 if (inst.operands[1].isscalar)
12940 {
12941 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
12942 struct neon_type_el et = neon_check_type (2, rs,
12943 N_EQK, N_8 | N_16 | N_32 | N_KEY);
12944 unsigned sizebits = et.size >> 3;
12945 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
12946 int logsize = neon_logbits (et.size);
12947 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
12948
12949 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
12950 return;
12951
12952 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
12953 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12954 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12955 inst.instruction |= LOW4 (dm);
12956 inst.instruction |= HI1 (dm) << 5;
12957 inst.instruction |= neon_quad (rs) << 6;
12958 inst.instruction |= x << 17;
12959 inst.instruction |= sizebits << 16;
12960
12961 inst.instruction = neon_dp_fixup (inst.instruction);
12962 }
12963 else
12964 {
12965 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
12966 struct neon_type_el et = neon_check_type (2, rs,
12967 N_8 | N_16 | N_32 | N_KEY, N_EQK);
12968 /* Duplicate ARM register to lanes of vector. */
12969 inst.instruction = NEON_ENC_ARMREG (inst.instruction);
12970 switch (et.size)
12971 {
12972 case 8: inst.instruction |= 0x400000; break;
12973 case 16: inst.instruction |= 0x000020; break;
12974 case 32: inst.instruction |= 0x000000; break;
12975 default: break;
12976 }
12977 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
12978 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
12979 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
12980 inst.instruction |= neon_quad (rs) << 21;
12981 /* The encoding for this instruction is identical for the ARM and Thumb
12982 variants, except for the condition field. */
12983 do_vfp_cond_or_thumb ();
12984 }
12985}
12986
12987/* VMOV has particularly many variations. It can be one of:
12988 0. VMOV<c><q> <Qd>, <Qm>
12989 1. VMOV<c><q> <Dd>, <Dm>
12990 (Register operations, which are VORR with Rm = Rn.)
12991 2. VMOV<c><q>.<dt> <Qd>, #<imm>
12992 3. VMOV<c><q>.<dt> <Dd>, #<imm>
12993 (Immediate loads.)
12994 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
12995 (ARM register to scalar.)
12996 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
12997 (Two ARM registers to vector.)
12998 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
12999 (Scalar to ARM register.)
13000 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13001 (Vector to two ARM registers.)
13002 8. VMOV.F32 <Sd>, <Sm>
13003 9. VMOV.F64 <Dd>, <Dm>
13004 (VFP register moves.)
13005 10. VMOV.F32 <Sd>, #imm
13006 11. VMOV.F64 <Dd>, #imm
13007 (VFP float immediate load.)
13008 12. VMOV <Rd>, <Sm>
13009 (VFP single to ARM reg.)
13010 13. VMOV <Sd>, <Rm>
13011 (ARM reg to VFP single.)
13012 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13013 (Two ARM regs to two VFP singles.)
13014 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13015 (Two VFP singles to two ARM regs.)
13016
13017 These cases can be disambiguated using neon_select_shape, except cases 1/9
13018 and 3/11 which depend on the operand type too.
13019
13020 All the encoded bits are hardcoded by this function.
13021
13022 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13023 Cases 5, 7 may be used with VFPv2 and above.
13024
13025 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13026 can specify a type where it doesn't make sense to, and is ignored).
13027*/
13028
13029static void
13030do_neon_mov (void)
13031{
13032 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
13033 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
13034 NS_NULL);
13035 struct neon_type_el et;
13036 const char *ldconst = 0;
13037
13038 switch (rs)
13039 {
13040 case NS_DD: /* case 1/9. */
13041 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
13042 /* It is not an error here if no type is given. */
13043 inst.error = NULL;
13044 if (et.type == NT_float && et.size == 64)
13045 {
13046 do_vfp_nsyn_opcode ("fcpyd");
13047 break;
13048 }
13049 /* fall through. */
13050
13051 case NS_QQ: /* case 0/1. */
13052 {
13053 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13054 return;
13055 /* The architecture manual I have doesn't explicitly state which
13056 value the U bit should have for register->register moves, but
13057 the equivalent VORR instruction has U = 0, so do that. */
13058 inst.instruction = 0x0200110;
13059 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13060 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13061 inst.instruction |= LOW4 (inst.operands[1].reg);
13062 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13063 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13064 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13065 inst.instruction |= neon_quad (rs) << 6;
13066
13067 inst.instruction = neon_dp_fixup (inst.instruction);
13068 }
13069 break;
13070
13071 case NS_DI: /* case 3/11. */
13072 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
13073 inst.error = NULL;
13074 if (et.type == NT_float && et.size == 64)
13075 {
13076 /* case 11 (fconstd). */
13077 ldconst = "fconstd";
13078 goto encode_fconstd;
13079 }
13080 /* fall through. */
13081
13082 case NS_QI: /* case 2/3. */
13083 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13084 return;
13085 inst.instruction = 0x0800010;
13086 neon_move_immediate ();
13087 inst.instruction = neon_dp_fixup (inst.instruction);
13088 break;
13089
13090 case NS_SR: /* case 4. */
13091 {
13092 unsigned bcdebits = 0;
13093 struct neon_type_el et = neon_check_type (2, NS_NULL,
13094 N_8 | N_16 | N_32 | N_KEY, N_EQK);
13095 int logsize = neon_logbits (et.size);
13096 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
13097 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
13098
13099 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
13100 _(BAD_FPU));
13101 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
13102 && et.size != 32, _(BAD_FPU));
13103 constraint (et.type == NT_invtype, _("bad type for scalar"));
13104 constraint (x >= 64 / et.size, _("scalar index out of range"));
13105
13106 switch (et.size)
13107 {
13108 case 8: bcdebits = 0x8; break;
13109 case 16: bcdebits = 0x1; break;
13110 case 32: bcdebits = 0x0; break;
13111 default: ;
13112 }
13113
13114 bcdebits |= x << logsize;
13115
13116 inst.instruction = 0xe000b10;
13117 do_vfp_cond_or_thumb ();
13118 inst.instruction |= LOW4 (dn) << 16;
13119 inst.instruction |= HI1 (dn) << 7;
13120 inst.instruction |= inst.operands[1].reg << 12;
13121 inst.instruction |= (bcdebits & 3) << 5;
13122 inst.instruction |= (bcdebits >> 2) << 21;
13123 }
13124 break;
13125
13126 case NS_DRR: /* case 5 (fmdrr). */
13127 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
13128 _(BAD_FPU));
13129
13130 inst.instruction = 0xc400b10;
13131 do_vfp_cond_or_thumb ();
13132 inst.instruction |= LOW4 (inst.operands[0].reg);
13133 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
13134 inst.instruction |= inst.operands[1].reg << 12;
13135 inst.instruction |= inst.operands[2].reg << 16;
13136 break;
13137
13138 case NS_RS: /* case 6. */
13139 {
13140 struct neon_type_el et = neon_check_type (2, NS_NULL,
13141 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
13142 unsigned logsize = neon_logbits (et.size);
13143 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
13144 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
13145 unsigned abcdebits = 0;
13146
13147 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
13148 _(BAD_FPU));
13149 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
13150 && et.size != 32, _(BAD_FPU));
13151 constraint (et.type == NT_invtype, _("bad type for scalar"));
13152 constraint (x >= 64 / et.size, _("scalar index out of range"));
13153
13154 switch (et.size)
13155 {
13156 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
13157 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
13158 case 32: abcdebits = 0x00; break;
13159 default: ;
13160 }
13161
13162 abcdebits |= x << logsize;
13163 inst.instruction = 0xe100b10;
13164 do_vfp_cond_or_thumb ();
13165 inst.instruction |= LOW4 (dn) << 16;
13166 inst.instruction |= HI1 (dn) << 7;
13167 inst.instruction |= inst.operands[0].reg << 12;
13168 inst.instruction |= (abcdebits & 3) << 5;
13169 inst.instruction |= (abcdebits >> 2) << 21;
13170 }
13171 break;
13172
13173 case NS_RRD: /* case 7 (fmrrd). */
13174 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
13175 _(BAD_FPU));
13176
13177 inst.instruction = 0xc500b10;
13178 do_vfp_cond_or_thumb ();
13179 inst.instruction |= inst.operands[0].reg << 12;
13180 inst.instruction |= inst.operands[1].reg << 16;
13181 inst.instruction |= LOW4 (inst.operands[2].reg);
13182 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13183 break;
13184
13185 case NS_FF: /* case 8 (fcpys). */
13186 do_vfp_nsyn_opcode ("fcpys");
13187 break;
13188
13189 case NS_FI: /* case 10 (fconsts). */
13190 ldconst = "fconsts";
13191 encode_fconstd:
13192 if (is_quarter_float (inst.operands[1].imm))
13193 {
13194 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
13195 do_vfp_nsyn_opcode (ldconst);
13196 }
13197 else
13198 first_error (_("immediate out of range"));
13199 break;
13200
13201 case NS_RF: /* case 12 (fmrs). */
13202 do_vfp_nsyn_opcode ("fmrs");
13203 break;
13204
13205 case NS_FR: /* case 13 (fmsr). */
13206 do_vfp_nsyn_opcode ("fmsr");
13207 break;
13208
13209 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13210 (one of which is a list), but we have parsed four. Do some fiddling to
13211 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13212 expect. */
13213 case NS_RRFF: /* case 14 (fmrrs). */
13214 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
13215 _("VFP registers must be adjacent"));
13216 inst.operands[2].imm = 2;
13217 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
13218 do_vfp_nsyn_opcode ("fmrrs");
13219 break;
13220
13221 case NS_FFRR: /* case 15 (fmsrr). */
13222 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
13223 _("VFP registers must be adjacent"));
13224 inst.operands[1] = inst.operands[2];
13225 inst.operands[2] = inst.operands[3];
13226 inst.operands[0].imm = 2;
13227 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
13228 do_vfp_nsyn_opcode ("fmsrr");
13229 break;
13230
13231 default:
13232 abort ();
13233 }
13234}
13235
13236static void
13237do_neon_rshift_round_imm (void)
13238{
13239 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13240 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13241 int imm = inst.operands[2].imm;
13242
13243 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13244 if (imm == 0)
13245 {
13246 inst.operands[2].present = 0;
13247 do_neon_mov ();
13248 return;
13249 }
13250
13251 constraint (imm < 1 || (unsigned)imm > et.size,
13252 _("immediate out of range for shift"));
13253 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13254 et.size - imm);
13255}
13256
13257static void
13258do_neon_movl (void)
13259{
13260 struct neon_type_el et = neon_check_type (2, NS_QD,
13261 N_EQK | N_DBL, N_SU_32 | N_KEY);
13262 unsigned sizebits = et.size >> 3;
13263 inst.instruction |= sizebits << 19;
13264 neon_two_same (0, et.type == NT_unsigned, -1);
13265}
13266
13267static void
13268do_neon_trn (void)
13269{
13270 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13271 struct neon_type_el et = neon_check_type (2, rs,
13272 N_EQK, N_8 | N_16 | N_32 | N_KEY);
13273 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
13274 neon_two_same (neon_quad (rs), 1, et.size);
13275}
13276
13277static void
13278do_neon_zip_uzp (void)
13279{
13280 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13281 struct neon_type_el et = neon_check_type (2, rs,
13282 N_EQK, N_8 | N_16 | N_32 | N_KEY);
13283 if (rs == NS_DD && et.size == 32)
13284 {
13285 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13286 inst.instruction = N_MNEM_vtrn;
13287 do_neon_trn ();
13288 return;
13289 }
13290 neon_two_same (neon_quad (rs), 1, et.size);
13291}
13292
13293static void
13294do_neon_sat_abs_neg (void)
13295{
13296 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13297 struct neon_type_el et = neon_check_type (2, rs,
13298 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
13299 neon_two_same (neon_quad (rs), 1, et.size);
13300}
13301
13302static void
13303do_neon_pair_long (void)
13304{
13305 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13306 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
13307 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13308 inst.instruction |= (et.type == NT_unsigned) << 7;
13309 neon_two_same (neon_quad (rs), 1, et.size);
13310}
13311
13312static void
13313do_neon_recip_est (void)
13314{
13315 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13316 struct neon_type_el et = neon_check_type (2, rs,
13317 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
13318 inst.instruction |= (et.type == NT_float) << 8;
13319 neon_two_same (neon_quad (rs), 1, et.size);
13320}
13321
13322static void
13323do_neon_cls (void)
13324{
13325 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13326 struct neon_type_el et = neon_check_type (2, rs,
13327 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
13328 neon_two_same (neon_quad (rs), 1, et.size);
13329}
13330
13331static void
13332do_neon_clz (void)
13333{
13334 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13335 struct neon_type_el et = neon_check_type (2, rs,
13336 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
13337 neon_two_same (neon_quad (rs), 1, et.size);
13338}
13339
13340static void
13341do_neon_cnt (void)
13342{
13343 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13344 struct neon_type_el et = neon_check_type (2, rs,
13345 N_EQK | N_INT, N_8 | N_KEY);
13346 neon_two_same (neon_quad (rs), 1, et.size);
13347}
13348
13349static void
13350do_neon_swp (void)
13351{
13352 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13353 neon_two_same (neon_quad (rs), 1, -1);
13354}
13355
13356static void
13357do_neon_tbl_tbx (void)
13358{
13359 unsigned listlenbits;
13360 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
13361
13362 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
13363 {
13364 first_error (_("bad list length for table lookup"));
13365 return;
13366 }
13367
13368 listlenbits = inst.operands[1].imm - 1;
13369 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13370 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13371 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13372 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13373 inst.instruction |= LOW4 (inst.operands[2].reg);
13374 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13375 inst.instruction |= listlenbits << 8;
13376
13377 inst.instruction = neon_dp_fixup (inst.instruction);
13378}
13379
13380static void
13381do_neon_ldm_stm (void)
13382{
13383 /* P, U and L bits are part of bitmask. */
13384 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
13385 unsigned offsetbits = inst.operands[1].imm * 2;
13386
13387 if (inst.operands[1].issingle)
13388 {
13389 do_vfp_nsyn_ldm_stm (is_dbmode);
13390 return;
13391 }
13392
13393 constraint (is_dbmode && !inst.operands[0].writeback,
13394 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13395
13396 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
13397 _("register list must contain at least 1 and at most 16 "
13398 "registers"));
13399
13400 inst.instruction |= inst.operands[0].reg << 16;
13401 inst.instruction |= inst.operands[0].writeback << 21;
13402 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
13403 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
13404
13405 inst.instruction |= offsetbits;
13406
13407 do_vfp_cond_or_thumb ();
13408}
13409
13410static void
13411do_neon_ldr_str (void)
13412{
13413 int is_ldr = (inst.instruction & (1 << 20)) != 0;
13414
13415 if (inst.operands[0].issingle)
13416 {
13417 if (is_ldr)
13418 do_vfp_nsyn_opcode ("flds");
13419 else
13420 do_vfp_nsyn_opcode ("fsts");
13421 }
13422 else
13423 {
13424 if (is_ldr)
13425 do_vfp_nsyn_opcode ("fldd");
13426 else
13427 do_vfp_nsyn_opcode ("fstd");
13428 }
13429}
13430
13431/* "interleave" version also handles non-interleaving register VLD1/VST1
13432 instructions. */
13433
13434static void
13435do_neon_ld_st_interleave (void)
13436{
13437 struct neon_type_el et = neon_check_type (1, NS_NULL,
13438 N_8 | N_16 | N_32 | N_64);
13439 unsigned alignbits = 0;
13440 unsigned idx;
13441 /* The bits in this table go:
13442 0: register stride of one (0) or two (1)
13443 1,2: register list length, minus one (1, 2, 3, 4).
13444 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13445 We use -1 for invalid entries. */
13446 const int typetable[] =
13447 {
13448 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13449 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13450 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13451 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13452 };
13453 int typebits;
13454
13455 if (et.type == NT_invtype)
13456 return;
13457
13458 if (inst.operands[1].immisalign)
13459 switch (inst.operands[1].imm >> 8)
13460 {
13461 case 64: alignbits = 1; break;
13462 case 128:
13463 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3)
13464 goto bad_alignment;
13465 alignbits = 2;
13466 break;
13467 case 256:
13468 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3)
13469 goto bad_alignment;
13470 alignbits = 3;
13471 break;
13472 default:
13473 bad_alignment:
13474 first_error (_("bad alignment"));
13475 return;
13476 }
13477
13478 inst.instruction |= alignbits << 4;
13479 inst.instruction |= neon_logbits (et.size) << 6;
13480
13481 /* Bits [4:6] of the immediate in a list specifier encode register stride
13482 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13483 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13484 up the right value for "type" in a table based on this value and the given
13485 list style, then stick it back. */
13486 idx = ((inst.operands[0].imm >> 4) & 7)
13487 | (((inst.instruction >> 8) & 3) << 3);
13488
13489 typebits = typetable[idx];
13490
13491 constraint (typebits == -1, _("bad list type for instruction"));
13492
13493 inst.instruction &= ~0xf00;
13494 inst.instruction |= typebits << 8;
13495}
13496
13497/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13498 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13499 otherwise. The variable arguments are a list of pairs of legal (size, align)
13500 values, terminated with -1. */
13501
13502static int
13503neon_alignment_bit (int size, int align, int *do_align, ...)
13504{
13505 va_list ap;
13506 int result = FAIL, thissize, thisalign;
13507
13508 if (!inst.operands[1].immisalign)
13509 {
13510 *do_align = 0;
13511 return SUCCESS;
13512 }
13513
13514 va_start (ap, do_align);
13515
13516 do
13517 {
13518 thissize = va_arg (ap, int);
13519 if (thissize == -1)
13520 break;
13521 thisalign = va_arg (ap, int);
13522
13523 if (size == thissize && align == thisalign)
13524 result = SUCCESS;
13525 }
13526 while (result != SUCCESS);
13527
13528 va_end (ap);
13529
13530 if (result == SUCCESS)
13531 *do_align = 1;
13532 else
13533 first_error (_("unsupported alignment for instruction"));
13534
13535 return result;
13536}
13537
13538static void
13539do_neon_ld_st_lane (void)
13540{
13541 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
13542 int align_good, do_align = 0;
13543 int logsize = neon_logbits (et.size);
13544 int align = inst.operands[1].imm >> 8;
13545 int n = (inst.instruction >> 8) & 3;
13546 int max_el = 64 / et.size;
13547
13548 if (et.type == NT_invtype)
13549 return;
13550
13551 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
13552 _("bad list length"));
13553 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
13554 _("scalar index out of range"));
13555 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
13556 && et.size == 8,
13557 _("stride of 2 unavailable when element size is 8"));
13558
13559 switch (n)
13560 {
13561 case 0: /* VLD1 / VST1. */
13562 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
13563 32, 32, -1);
13564 if (align_good == FAIL)
13565 return;
13566 if (do_align)
13567 {
13568 unsigned alignbits = 0;
13569 switch (et.size)
13570 {
13571 case 16: alignbits = 0x1; break;
13572 case 32: alignbits = 0x3; break;
13573 default: ;
13574 }
13575 inst.instruction |= alignbits << 4;
13576 }
13577 break;
13578
13579 case 1: /* VLD2 / VST2. */
13580 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
13581 32, 64, -1);
13582 if (align_good == FAIL)
13583 return;
13584 if (do_align)
13585 inst.instruction |= 1 << 4;
13586 break;
13587
13588 case 2: /* VLD3 / VST3. */
13589 constraint (inst.operands[1].immisalign,
13590 _("can't use alignment with this instruction"));
13591 break;
13592
13593 case 3: /* VLD4 / VST4. */
13594 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
13595 16, 64, 32, 64, 32, 128, -1);
13596 if (align_good == FAIL)
13597 return;
13598 if (do_align)
13599 {
13600 unsigned alignbits = 0;
13601 switch (et.size)
13602 {
13603 case 8: alignbits = 0x1; break;
13604 case 16: alignbits = 0x1; break;
13605 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
13606 default: ;
13607 }
13608 inst.instruction |= alignbits << 4;
13609 }
13610 break;
13611
13612 default: ;
13613 }
13614
13615 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13616 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13617 inst.instruction |= 1 << (4 + logsize);
13618
13619 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
13620 inst.instruction |= logsize << 10;
13621}
13622
13623/* Encode single n-element structure to all lanes VLD<n> instructions. */
13624
13625static void
13626do_neon_ld_dup (void)
13627{
13628 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
13629 int align_good, do_align = 0;
13630
13631 if (et.type == NT_invtype)
13632 return;
13633
13634 switch ((inst.instruction >> 8) & 3)
13635 {
13636 case 0: /* VLD1. */
13637 assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
13638 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
13639 &do_align, 16, 16, 32, 32, -1);
13640 if (align_good == FAIL)
13641 return;
13642 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
13643 {
13644 case 1: break;
13645 case 2: inst.instruction |= 1 << 5; break;
13646 default: first_error (_("bad list length")); return;
13647 }
13648 inst.instruction |= neon_logbits (et.size) << 6;
13649 break;
13650
13651 case 1: /* VLD2. */
13652 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
13653 &do_align, 8, 16, 16, 32, 32, 64, -1);
13654 if (align_good == FAIL)
13655 return;
13656 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
13657 _("bad list length"));
13658 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13659 inst.instruction |= 1 << 5;
13660 inst.instruction |= neon_logbits (et.size) << 6;
13661 break;
13662
13663 case 2: /* VLD3. */
13664 constraint (inst.operands[1].immisalign,
13665 _("can't use alignment with this instruction"));
13666 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
13667 _("bad list length"));
13668 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13669 inst.instruction |= 1 << 5;
13670 inst.instruction |= neon_logbits (et.size) << 6;
13671 break;
13672
13673 case 3: /* VLD4. */
13674 {
13675 int align = inst.operands[1].imm >> 8;
13676 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
13677 16, 64, 32, 64, 32, 128, -1);
13678 if (align_good == FAIL)
13679 return;
13680 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
13681 _("bad list length"));
13682 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13683 inst.instruction |= 1 << 5;
13684 if (et.size == 32 && align == 128)
13685 inst.instruction |= 0x3 << 6;
13686 else
13687 inst.instruction |= neon_logbits (et.size) << 6;
13688 }
13689 break;
13690
13691 default: ;
13692 }
13693
13694 inst.instruction |= do_align << 4;
13695}
13696
13697/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13698 apart from bits [11:4]. */
13699
13700static void
13701do_neon_ldx_stx (void)
13702{
13703 switch (NEON_LANE (inst.operands[0].imm))
13704 {
13705 case NEON_INTERLEAVE_LANES:
13706 inst.instruction = NEON_ENC_INTERLV (inst.instruction);
13707 do_neon_ld_st_interleave ();
13708 break;
13709
13710 case NEON_ALL_LANES:
13711 inst.instruction = NEON_ENC_DUP (inst.instruction);
13712 do_neon_ld_dup ();
13713 break;
13714
13715 default:
13716 inst.instruction = NEON_ENC_LANE (inst.instruction);
13717 do_neon_ld_st_lane ();
13718 }
13719
13720 /* L bit comes from bit mask. */
13721 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13722 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13723 inst.instruction |= inst.operands[1].reg << 16;
13724
13725 if (inst.operands[1].postind)
13726 {
13727 int postreg = inst.operands[1].imm & 0xf;
13728 constraint (!inst.operands[1].immisreg,
13729 _("post-index must be a register"));
13730 constraint (postreg == 0xd || postreg == 0xf,
13731 _("bad register for post-index"));
13732 inst.instruction |= postreg;
13733 }
13734 else if (inst.operands[1].writeback)
13735 {
13736 inst.instruction |= 0xd;
13737 }
13738 else
13739 inst.instruction |= 0xf;
13740
13741 if (thumb_mode)
13742 inst.instruction |= 0xf9000000;
13743 else
13744 inst.instruction |= 0xf4000000;
13745}
13746
13747
13748/* Overall per-instruction processing. */
13749
13750/* We need to be able to fix up arbitrary expressions in some statements.
13751 This is so that we can handle symbols that are an arbitrary distance from
13752 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13753 which returns part of an address in a form which will be valid for
13754 a data instruction. We do this by pushing the expression into a symbol
13755 in the expr_section, and creating a fix for that. */
13756
13757static void
13758fix_new_arm (fragS * frag,
13759 int where,
13760 short int size,
13761 expressionS * exp,
13762 int pc_rel,
13763 int reloc)
13764{
13765 fixS * new_fix;
13766
13767 switch (exp->X_op)
13768 {
13769 case O_constant:
13770 case O_symbol:
13771 case O_add:
13772 case O_subtract:
13773 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
13774 break;
13775
13776 default:
13777 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
13778 pc_rel, reloc);
13779 break;
13780 }
13781
13782 /* Mark whether the fix is to a THUMB instruction, or an ARM
13783 instruction. */
13784 new_fix->tc_fix_data = thumb_mode;
13785}
13786
13787/* Create a frg for an instruction requiring relaxation. */
13788static void
13789output_relax_insn (void)
13790{
13791 char * to;
13792 symbolS *sym;
13793 int offset;
13794
13795 /* The size of the instruction is unknown, so tie the debug info to the
13796 start of the instruction. */
13797 dwarf2_emit_insn (0);
13798
13799 switch (inst.reloc.exp.X_op)
13800 {
13801 case O_symbol:
13802 sym = inst.reloc.exp.X_add_symbol;
13803 offset = inst.reloc.exp.X_add_number;
13804 break;
13805 case O_constant:
13806 sym = NULL;
13807 offset = inst.reloc.exp.X_add_number;
13808 break;
13809 default:
13810 sym = make_expr_symbol (&inst.reloc.exp);
13811 offset = 0;
13812 break;
13813 }
13814 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
13815 inst.relax, sym, offset, NULL/*offset, opcode*/);
13816 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
13817}
13818
13819/* Write a 32-bit thumb instruction to buf. */
13820static void
13821put_thumb32_insn (char * buf, unsigned long insn)
13822{
13823 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
13824 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
13825}
13826
13827static void
13828output_inst (const char * str)
13829{
13830 char * to = NULL;
13831
13832 if (inst.error)
13833 {
13834 as_bad ("%s -- `%s'", inst.error, str);
13835 return;
13836 }
13837 if (inst.relax) {
13838 output_relax_insn();
13839 return;
13840 }
13841 if (inst.size == 0)
13842 return;
13843
13844 to = frag_more (inst.size);
13845
13846 if (thumb_mode && (inst.size > THUMB_SIZE))
13847 {
13848 assert (inst.size == (2 * THUMB_SIZE));
13849 put_thumb32_insn (to, inst.instruction);
13850 }
13851 else if (inst.size > INSN_SIZE)
13852 {
13853 assert (inst.size == (2 * INSN_SIZE));
13854 md_number_to_chars (to, inst.instruction, INSN_SIZE);
13855 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
13856 }
13857 else
13858 md_number_to_chars (to, inst.instruction, inst.size);
13859
13860 if (inst.reloc.type != BFD_RELOC_UNUSED)
13861 fix_new_arm (frag_now, to - frag_now->fr_literal,
13862 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
13863 inst.reloc.type);
13864
13865 dwarf2_emit_insn (inst.size);
13866}
13867
13868/* Tag values used in struct asm_opcode's tag field. */
13869enum opcode_tag
13870{
13871 OT_unconditional, /* Instruction cannot be conditionalized.
13872 The ARM condition field is still 0xE. */
13873 OT_unconditionalF, /* Instruction cannot be conditionalized
13874 and carries 0xF in its ARM condition field. */
13875 OT_csuffix, /* Instruction takes a conditional suffix. */
13876 OT_csuffixF, /* Some forms of the instruction take a conditional
13877 suffix, others place 0xF where the condition field
13878 would be. */
13879 OT_cinfix3, /* Instruction takes a conditional infix,
13880 beginning at character index 3. (In
13881 unified mode, it becomes a suffix.) */
13882 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
13883 tsts, cmps, cmns, and teqs. */
13884 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
13885 character index 3, even in unified mode. Used for
13886 legacy instructions where suffix and infix forms
13887 may be ambiguous. */
13888 OT_csuf_or_in3, /* Instruction takes either a conditional
13889 suffix or an infix at character index 3. */
13890 OT_odd_infix_unc, /* This is the unconditional variant of an
13891 instruction that takes a conditional infix
13892 at an unusual position. In unified mode,
13893 this variant will accept a suffix. */
13894 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
13895 are the conditional variants of instructions that
13896 take conditional infixes in unusual positions.
13897 The infix appears at character index
13898 (tag - OT_odd_infix_0). These are not accepted
13899 in unified mode. */
13900};
13901
13902/* Subroutine of md_assemble, responsible for looking up the primary
13903 opcode from the mnemonic the user wrote. STR points to the
13904 beginning of the mnemonic.
13905
13906 This is not simply a hash table lookup, because of conditional
13907 variants. Most instructions have conditional variants, which are
13908 expressed with a _conditional affix_ to the mnemonic. If we were
13909 to encode each conditional variant as a literal string in the opcode
13910 table, it would have approximately 20,000 entries.
13911
13912 Most mnemonics take this affix as a suffix, and in unified syntax,
13913 'most' is upgraded to 'all'. However, in the divided syntax, some
13914 instructions take the affix as an infix, notably the s-variants of
13915 the arithmetic instructions. Of those instructions, all but six
13916 have the infix appear after the third character of the mnemonic.
13917
13918 Accordingly, the algorithm for looking up primary opcodes given
13919 an identifier is:
13920
13921 1. Look up the identifier in the opcode table.
13922 If we find a match, go to step U.
13923
13924 2. Look up the last two characters of the identifier in the
13925 conditions table. If we find a match, look up the first N-2
13926 characters of the identifier in the opcode table. If we
13927 find a match, go to step CE.
13928
13929 3. Look up the fourth and fifth characters of the identifier in
13930 the conditions table. If we find a match, extract those
13931 characters from the identifier, and look up the remaining
13932 characters in the opcode table. If we find a match, go
13933 to step CM.
13934
13935 4. Fail.
13936
13937 U. Examine the tag field of the opcode structure, in case this is
13938 one of the six instructions with its conditional infix in an
13939 unusual place. If it is, the tag tells us where to find the
13940 infix; look it up in the conditions table and set inst.cond
13941 accordingly. Otherwise, this is an unconditional instruction.
13942 Again set inst.cond accordingly. Return the opcode structure.
13943
13944 CE. Examine the tag field to make sure this is an instruction that
13945 should receive a conditional suffix. If it is not, fail.
13946 Otherwise, set inst.cond from the suffix we already looked up,
13947 and return the opcode structure.
13948
13949 CM. Examine the tag field to make sure this is an instruction that
13950 should receive a conditional infix after the third character.
13951 If it is not, fail. Otherwise, undo the edits to the current
13952 line of input and proceed as for case CE. */
13953
13954static const struct asm_opcode *
13955opcode_lookup (char **str)
13956{
13957 char *end, *base;
13958 char *affix;
13959 const struct asm_opcode *opcode;
13960 const struct asm_cond *cond;
13961 char save[2];
13962 bfd_boolean neon_supported;
13963
13964 neon_supported = ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1);
13965
13966 /* Scan up to the end of the mnemonic, which must end in white space,
13967 '.' (in unified mode, or for Neon instructions), or end of string. */
13968 for (base = end = *str; *end != '\0'; end++)
13969 if (*end == ' ' || ((unified_syntax || neon_supported) && *end == '.'))
13970 break;
13971
13972 if (end == base)
13973 return 0;
13974
13975 /* Handle a possible width suffix and/or Neon type suffix. */
13976 if (end[0] == '.')
13977 {
13978 int offset = 2;
13979
13980 /* The .w and .n suffixes are only valid if the unified syntax is in
13981 use. */
13982 if (unified_syntax && end[1] == 'w')
13983 inst.size_req = 4;
13984 else if (unified_syntax && end[1] == 'n')
13985 inst.size_req = 2;
13986 else
13987 offset = 0;
13988
13989 inst.vectype.elems = 0;
13990
13991 *str = end + offset;
13992
13993 if (end[offset] == '.')
13994 {
13995 /* See if we have a Neon type suffix (possible in either unified or
13996 non-unified ARM syntax mode). */
13997 if (parse_neon_type (&inst.vectype, str) == FAIL)
13998 return 0;
13999 }
14000 else if (end[offset] != '\0' && end[offset] != ' ')
14001 return 0;
14002 }
14003 else
14004 *str = end;
14005
14006 /* Look for unaffixed or special-case affixed mnemonic. */
14007 opcode = hash_find_n (arm_ops_hsh, base, end - base);
14008 if (opcode)
14009 {
14010 /* step U */
14011 if (opcode->tag < OT_odd_infix_0)
14012 {
14013 inst.cond = COND_ALWAYS;
14014 return opcode;
14015 }
14016
14017 if (unified_syntax)
14018 as_warn (_("conditional infixes are deprecated in unified syntax"));
14019 affix = base + (opcode->tag - OT_odd_infix_0);
14020 cond = hash_find_n (arm_cond_hsh, affix, 2);
14021 assert (cond);
14022
14023 inst.cond = cond->value;
14024 return opcode;
14025 }
14026
14027 /* Cannot have a conditional suffix on a mnemonic of less than two
14028 characters. */
14029 if (end - base < 3)
14030 return 0;
14031
14032 /* Look for suffixed mnemonic. */
14033 affix = end - 2;
14034 cond = hash_find_n (arm_cond_hsh, affix, 2);
14035 opcode = hash_find_n (arm_ops_hsh, base, affix - base);
14036 if (opcode && cond)
14037 {
14038 /* step CE */
14039 switch (opcode->tag)
14040 {
14041 case OT_cinfix3_legacy:
14042 /* Ignore conditional suffixes matched on infix only mnemonics. */
14043 break;
14044
14045 case OT_cinfix3:
14046 case OT_cinfix3_deprecated:
14047 case OT_odd_infix_unc:
14048 if (!unified_syntax)
14049 return 0;
14050 /* else fall through */
14051
14052 case OT_csuffix:
14053 case OT_csuffixF:
14054 case OT_csuf_or_in3:
14055 inst.cond = cond->value;
14056 return opcode;
14057
14058 case OT_unconditional:
14059 case OT_unconditionalF:
14060 if (thumb_mode)
14061 {
14062 inst.cond = cond->value;
14063 }
14064 else
14065 {
14066 /* delayed diagnostic */
14067 inst.error = BAD_COND;
14068 inst.cond = COND_ALWAYS;
14069 }
14070 return opcode;
14071
14072 default:
14073 return 0;
14074 }
14075 }
14076
14077 /* Cannot have a usual-position infix on a mnemonic of less than
14078 six characters (five would be a suffix). */
14079 if (end - base < 6)
14080 return 0;
14081
14082 /* Look for infixed mnemonic in the usual position. */
14083 affix = base + 3;
14084 cond = hash_find_n (arm_cond_hsh, affix, 2);
14085 if (!cond)
14086 return 0;
14087
14088 memcpy (save, affix, 2);
14089 memmove (affix, affix + 2, (end - affix) - 2);
14090 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2);
14091 memmove (affix + 2, affix, (end - affix) - 2);
14092 memcpy (affix, save, 2);
14093
14094 if (opcode
14095 && (opcode->tag == OT_cinfix3
14096 || opcode->tag == OT_cinfix3_deprecated
14097 || opcode->tag == OT_csuf_or_in3
14098 || opcode->tag == OT_cinfix3_legacy))
14099 {
14100 /* step CM */
14101 if (unified_syntax
14102 && (opcode->tag == OT_cinfix3
14103 || opcode->tag == OT_cinfix3_deprecated))
14104 as_warn (_("conditional infixes are deprecated in unified syntax"));
14105
14106 inst.cond = cond->value;
14107 return opcode;
14108 }
14109
14110 return 0;
14111}
14112
14113void
14114md_assemble (char *str)
14115{
14116 char *p = str;
14117 const struct asm_opcode * opcode;
14118
14119 /* Align the previous label if needed. */
14120 if (last_label_seen != NULL)
14121 {
14122 symbol_set_frag (last_label_seen, frag_now);
14123 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
14124 S_SET_SEGMENT (last_label_seen, now_seg);
14125 }
14126
14127 memset (&inst, '\0', sizeof (inst));
14128 inst.reloc.type = BFD_RELOC_UNUSED;
14129
14130 opcode = opcode_lookup (&p);
14131 if (!opcode)
14132 {
14133 /* It wasn't an instruction, but it might be a register alias of
14134 the form alias .req reg, or a Neon .dn/.qn directive. */
14135 if (!create_register_alias (str, p)
14136 && !create_neon_reg_alias (str, p))
14137 as_bad (_("bad instruction `%s'"), str);
14138
14139 return;
14140 }
14141
14142 if (opcode->tag == OT_cinfix3_deprecated)
14143 as_warn (_("s suffix on comparison instruction is deprecated"));
14144
14145 /* The value which unconditional instructions should have in place of the
14146 condition field. */
14147 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
14148
14149 if (thumb_mode)
14150 {
14151 arm_feature_set variant;
14152
14153 variant = cpu_variant;
14154 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
14155 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
14156 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
14157 /* Check that this instruction is supported for this CPU. */
14158 if (!opcode->tvariant
14159 || (thumb_mode == 1
14160 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
14161 {
14162 as_bad (_("selected processor does not support `%s'"), str);
14163 return;
14164 }
14165 if (inst.cond != COND_ALWAYS && !unified_syntax
14166 && opcode->tencode != do_t_branch)
14167 {
14168 as_bad (_("Thumb does not support conditional execution"));
14169 return;
14170 }
14171
14172 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req)
14173 {
14174 /* Implicit require narrow instructions on Thumb-1. This avoids
14175 relaxation accidentally introducing Thumb-2 instructions. */
14176 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23)
14177 inst.size_req = 2;
14178 }
14179
14180 /* Check conditional suffixes. */
14181 if (current_it_mask)
14182 {
14183 int cond;
14184 cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1;
14185 current_it_mask <<= 1;
14186 current_it_mask &= 0x1f;
14187 /* The BKPT instruction is unconditional even in an IT block. */
14188 if (!inst.error
14189 && cond != inst.cond && opcode->tencode != do_t_bkpt)
14190 {
14191 as_bad (_("incorrect condition in IT block"));
14192 return;
14193 }
14194 }
14195 else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch)
14196 {
14197 as_bad (_("thumb conditional instrunction not in IT block"));
14198 return;
14199 }
14200
14201 mapping_state (MAP_THUMB);
14202 inst.instruction = opcode->tvalue;
14203
14204 if (!parse_operands (p, opcode->operands))
14205 opcode->tencode ();
14206
14207 /* Clear current_it_mask at the end of an IT block. */
14208 if (current_it_mask == 0x10)
14209 current_it_mask = 0;
14210
14211 if (!(inst.error || inst.relax))
14212 {
14213 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
14214 inst.size = (inst.instruction > 0xffff ? 4 : 2);
14215 if (inst.size_req && inst.size_req != inst.size)
14216 {
14217 as_bad (_("cannot honor width suffix -- `%s'"), str);
14218 return;
14219 }
14220 }
14221
14222 /* Something has gone badly wrong if we try to relax a fixed size
14223 instruction. */
14224 assert (inst.size_req == 0 || !inst.relax);
14225
14226 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
14227 *opcode->tvariant);
14228 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14229 set those bits when Thumb-2 32-bit instructions are seen. ie.
14230 anything other than bl/blx.
14231 This is overly pessimistic for relaxable instructions. */
14232 if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
14233 || inst.relax)
14234 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
14235 arm_ext_v6t2);
14236 }
14237 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
14238 {
14239 /* Check that this instruction is supported for this CPU. */
14240 if (!opcode->avariant ||
14241 !ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))
14242 {
14243 as_bad (_("selected processor does not support `%s'"), str);
14244 return;
14245 }
14246 if (inst.size_req)
14247 {
14248 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
14249 return;
14250 }
14251
14252 mapping_state (MAP_ARM);
14253 inst.instruction = opcode->avalue;
14254 if (opcode->tag == OT_unconditionalF)
14255 inst.instruction |= 0xF << 28;
14256 else
14257 inst.instruction |= inst.cond << 28;
14258 inst.size = INSN_SIZE;
14259 if (!parse_operands (p, opcode->operands))
14260 opcode->aencode ();
14261 /* Arm mode bx is marked as both v4T and v5 because it's still required
14262 on a hypothetical non-thumb v5 core. */
14263 if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t)
14264 || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5))
14265 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
14266 else
14267 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
14268 *opcode->avariant);
14269 }
14270 else
14271 {
14272 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14273 "-- `%s'"), str);
14274 return;
14275 }
14276 output_inst (str);
14277}
14278
14279/* Various frobbings of labels and their addresses. */
14280
14281void
14282arm_start_line_hook (void)
14283{
14284 last_label_seen = NULL;
14285}
14286
14287void
14288arm_frob_label (symbolS * sym)
14289{
14290 last_label_seen = sym;
14291
14292 ARM_SET_THUMB (sym, thumb_mode);
14293
14294#if defined OBJ_COFF || defined OBJ_ELF
14295 ARM_SET_INTERWORK (sym, support_interwork);
14296#endif
14297
14298 /* Note - do not allow local symbols (.Lxxx) to be labeled
14299 as Thumb functions. This is because these labels, whilst
14300 they exist inside Thumb code, are not the entry points for
14301 possible ARM->Thumb calls. Also, these labels can be used
14302 as part of a computed goto or switch statement. eg gcc
14303 can generate code that looks like this:
14304
14305 ldr r2, [pc, .Laaa]
14306 lsl r3, r3, #2
14307 ldr r2, [r3, r2]
14308 mov pc, r2
14309
14310 .Lbbb: .word .Lxxx
14311 .Lccc: .word .Lyyy
14312 ..etc...
14313 .Laaa: .word Lbbb
14314
14315 The first instruction loads the address of the jump table.
14316 The second instruction converts a table index into a byte offset.
14317 The third instruction gets the jump address out of the table.
14318 The fourth instruction performs the jump.
14319
14320 If the address stored at .Laaa is that of a symbol which has the
14321 Thumb_Func bit set, then the linker will arrange for this address
14322 to have the bottom bit set, which in turn would mean that the
14323 address computation performed by the third instruction would end
14324 up with the bottom bit set. Since the ARM is capable of unaligned
14325 word loads, the instruction would then load the incorrect address
14326 out of the jump table, and chaos would ensue. */
14327 if (label_is_thumb_function_name
14328 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
14329 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
14330 {
14331 /* When the address of a Thumb function is taken the bottom
14332 bit of that address should be set. This will allow
14333 interworking between Arm and Thumb functions to work
14334 correctly. */
14335
14336 THUMB_SET_FUNC (sym, 1);
14337
14338 label_is_thumb_function_name = FALSE;
14339 }
14340
14341 dwarf2_emit_label (sym);
14342}
14343
14344int
14345arm_data_in_code (void)
14346{
14347 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
14348 {
14349 *input_line_pointer = '/';
14350 input_line_pointer += 5;
14351 *input_line_pointer = 0;
14352 return 1;
14353 }
14354
14355 return 0;
14356}
14357
14358char *
14359arm_canonicalize_symbol_name (char * name)
14360{
14361 int len;
14362
14363 if (thumb_mode && (len = strlen (name)) > 5
14364 && streq (name + len - 5, "/data"))
14365 *(name + len - 5) = 0;
14366
14367 return name;
14368}
14369
14370/* Table of all register names defined by default. The user can
14371 define additional names with .req. Note that all register names
14372 should appear in both upper and lowercase variants. Some registers
14373 also have mixed-case names. */
14374
14375#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14376#define REGNUM(p,n,t) REGDEF(p##n, n, t)
14377#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14378#define REGSET(p,t) \
14379 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14380 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14381 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14382 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14383#define REGSETH(p,t) \
14384 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14385 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14386 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14387 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14388#define REGSET2(p,t) \
14389 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14390 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14391 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14392 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14393
14394static const struct reg_entry reg_names[] =
14395{
14396 /* ARM integer registers. */
14397 REGSET(r, RN), REGSET(R, RN),
14398
14399 /* ATPCS synonyms. */
14400 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
14401 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
14402 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
14403
14404 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
14405 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
14406 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
14407
14408 /* Well-known aliases. */
14409 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
14410 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
14411
14412 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
14413 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
14414
14415 /* Coprocessor numbers. */
14416 REGSET(p, CP), REGSET(P, CP),
14417
14418 /* Coprocessor register numbers. The "cr" variants are for backward
14419 compatibility. */
14420 REGSET(c, CN), REGSET(C, CN),
14421 REGSET(cr, CN), REGSET(CR, CN),
14422
14423 /* FPA registers. */
14424 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
14425 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
14426
14427 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
14428 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
14429
14430 /* VFP SP registers. */
14431 REGSET(s,VFS), REGSET(S,VFS),
14432 REGSETH(s,VFS), REGSETH(S,VFS),
14433
14434 /* VFP DP Registers. */
14435 REGSET(d,VFD), REGSET(D,VFD),
14436 /* Extra Neon DP registers. */
14437 REGSETH(d,VFD), REGSETH(D,VFD),
14438
14439 /* Neon QP registers. */
14440 REGSET2(q,NQ), REGSET2(Q,NQ),
14441
14442 /* VFP control registers. */
14443 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
14444 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
14445 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
14446 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
14447 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
14448 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
14449
14450 /* Maverick DSP coprocessor registers. */
14451 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
14452 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
14453
14454 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
14455 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
14456 REGDEF(dspsc,0,DSPSC),
14457
14458 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
14459 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
14460 REGDEF(DSPSC,0,DSPSC),
14461
14462 /* iWMMXt data registers - p0, c0-15. */
14463 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
14464
14465 /* iWMMXt control registers - p1, c0-3. */
14466 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
14467 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
14468 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
14469 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
14470
14471 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14472 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
14473 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
14474 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
14475 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
14476
14477 /* XScale accumulator registers. */
14478 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
14479};
14480#undef REGDEF
14481#undef REGNUM
14482#undef REGSET
14483
14484/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14485 within psr_required_here. */
14486static const struct asm_psr psrs[] =
14487{
14488 /* Backward compatibility notation. Note that "all" is no longer
14489 truly all possible PSR bits. */
14490 {"all", PSR_c | PSR_f},
14491 {"flg", PSR_f},
14492 {"ctl", PSR_c},
14493
14494 /* Individual flags. */
14495 {"f", PSR_f},
14496 {"c", PSR_c},
14497 {"x", PSR_x},
14498 {"s", PSR_s},
14499 /* Combinations of flags. */
14500 {"fs", PSR_f | PSR_s},
14501 {"fx", PSR_f | PSR_x},
14502 {"fc", PSR_f | PSR_c},
14503 {"sf", PSR_s | PSR_f},
14504 {"sx", PSR_s | PSR_x},
14505 {"sc", PSR_s | PSR_c},
14506 {"xf", PSR_x | PSR_f},
14507 {"xs", PSR_x | PSR_s},
14508 {"xc", PSR_x | PSR_c},
14509 {"cf", PSR_c | PSR_f},
14510 {"cs", PSR_c | PSR_s},
14511 {"cx", PSR_c | PSR_x},
14512 {"fsx", PSR_f | PSR_s | PSR_x},
14513 {"fsc", PSR_f | PSR_s | PSR_c},
14514 {"fxs", PSR_f | PSR_x | PSR_s},
14515 {"fxc", PSR_f | PSR_x | PSR_c},
14516 {"fcs", PSR_f | PSR_c | PSR_s},
14517 {"fcx", PSR_f | PSR_c | PSR_x},
14518 {"sfx", PSR_s | PSR_f | PSR_x},
14519 {"sfc", PSR_s | PSR_f | PSR_c},
14520 {"sxf", PSR_s | PSR_x | PSR_f},
14521 {"sxc", PSR_s | PSR_x | PSR_c},
14522 {"scf", PSR_s | PSR_c | PSR_f},
14523 {"scx", PSR_s | PSR_c | PSR_x},
14524 {"xfs", PSR_x | PSR_f | PSR_s},
14525 {"xfc", PSR_x | PSR_f | PSR_c},
14526 {"xsf", PSR_x | PSR_s | PSR_f},
14527 {"xsc", PSR_x | PSR_s | PSR_c},
14528 {"xcf", PSR_x | PSR_c | PSR_f},
14529 {"xcs", PSR_x | PSR_c | PSR_s},
14530 {"cfs", PSR_c | PSR_f | PSR_s},
14531 {"cfx", PSR_c | PSR_f | PSR_x},
14532 {"csf", PSR_c | PSR_s | PSR_f},
14533 {"csx", PSR_c | PSR_s | PSR_x},
14534 {"cxf", PSR_c | PSR_x | PSR_f},
14535 {"cxs", PSR_c | PSR_x | PSR_s},
14536 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
14537 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
14538 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
14539 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
14540 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
14541 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
14542 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
14543 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
14544 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
14545 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
14546 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
14547 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
14548 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
14549 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
14550 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
14551 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
14552 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
14553 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
14554 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
14555 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
14556 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
14557 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
14558 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
14559 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
14560};
14561
14562/* Table of V7M psr names. */
14563static const struct asm_psr v7m_psrs[] =
14564{
14565 {"apsr", 0 }, {"APSR", 0 },
14566 {"iapsr", 1 }, {"IAPSR", 1 },
14567 {"eapsr", 2 }, {"EAPSR", 2 },
14568 {"psr", 3 }, {"PSR", 3 },
14569 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
14570 {"ipsr", 5 }, {"IPSR", 5 },
14571 {"epsr", 6 }, {"EPSR", 6 },
14572 {"iepsr", 7 }, {"IEPSR", 7 },
14573 {"msp", 8 }, {"MSP", 8 },
14574 {"psp", 9 }, {"PSP", 9 },
14575 {"primask", 16}, {"PRIMASK", 16},
14576 {"basepri", 17}, {"BASEPRI", 17},
14577 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
14578 {"faultmask", 19}, {"FAULTMASK", 19},
14579 {"control", 20}, {"CONTROL", 20}
14580};
14581
14582/* Table of all shift-in-operand names. */
14583static const struct asm_shift_name shift_names [] =
14584{
14585 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
14586 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
14587 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
14588 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
14589 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
14590 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
14591};
14592
14593/* Table of all explicit relocation names. */
14594#ifdef OBJ_ELF
14595static struct reloc_entry reloc_names[] =
14596{
14597 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
14598 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
14599 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
14600 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
14601 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
14602 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
14603 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
14604 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
14605 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
14606 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
14607 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}
14608};
14609#endif
14610
14611/* Table of all conditional affixes. 0xF is not defined as a condition code. */
14612static const struct asm_cond conds[] =
14613{
14614 {"eq", 0x0},
14615 {"ne", 0x1},
14616 {"cs", 0x2}, {"hs", 0x2},
14617 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14618 {"mi", 0x4},
14619 {"pl", 0x5},
14620 {"vs", 0x6},
14621 {"vc", 0x7},
14622 {"hi", 0x8},
14623 {"ls", 0x9},
14624 {"ge", 0xa},
14625 {"lt", 0xb},
14626 {"gt", 0xc},
14627 {"le", 0xd},
14628 {"al", 0xe}
14629};
14630
14631static struct asm_barrier_opt barrier_opt_names[] =
14632{
14633 { "sy", 0xf },
14634 { "un", 0x7 },
14635 { "st", 0xe },
14636 { "unst", 0x6 }
14637};
14638
14639/* Table of ARM-format instructions. */
14640
14641/* Macros for gluing together operand strings. N.B. In all cases
14642 other than OPS0, the trailing OP_stop comes from default
14643 zero-initialization of the unspecified elements of the array. */
14644#define OPS0() { OP_stop, }
14645#define OPS1(a) { OP_##a, }
14646#define OPS2(a,b) { OP_##a,OP_##b, }
14647#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14648#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14649#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14650#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14651
14652/* These macros abstract out the exact format of the mnemonic table and
14653 save some repeated characters. */
14654
14655/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14656#define TxCE(mnem, op, top, nops, ops, ae, te) \
14657 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14658 THUMB_VARIANT, do_##ae, do_##te }
14659
14660/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14661 a T_MNEM_xyz enumerator. */
14662#define TCE(mnem, aop, top, nops, ops, ae, te) \
14663 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14664#define tCE(mnem, aop, top, nops, ops, ae, te) \
14665 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14666
14667/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14668 infix after the third character. */
14669#define TxC3(mnem, op, top, nops, ops, ae, te) \
14670 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14671 THUMB_VARIANT, do_##ae, do_##te }
14672#define TxC3w(mnem, op, top, nops, ops, ae, te) \
14673 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14674 THUMB_VARIANT, do_##ae, do_##te }
14675#define TC3(mnem, aop, top, nops, ops, ae, te) \
14676 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14677#define TC3w(mnem, aop, top, nops, ops, ae, te) \
14678 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14679#define tC3(mnem, aop, top, nops, ops, ae, te) \
14680 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14681#define tC3w(mnem, aop, top, nops, ops, ae, te) \
14682 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14683
14684/* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14685 appear in the condition table. */
14686#define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14687 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14688 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14689
14690#define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14691 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14692 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14693 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14694 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14695 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14696 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14697 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14698 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14699 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14700 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14701 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14702 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14703 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14704 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14705 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14706 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14707 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14708 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14709 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14710
14711#define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14712 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14713#define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14714 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14715
14716/* Mnemonic that cannot be conditionalized. The ARM condition-code
14717 field is still 0xE. Many of the Thumb variants can be executed
14718 conditionally, so this is checked separately. */
14719#define TUE(mnem, op, top, nops, ops, ae, te) \
14720 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14721 THUMB_VARIANT, do_##ae, do_##te }
14722
14723/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14724 condition code field. */
14725#define TUF(mnem, op, top, nops, ops, ae, te) \
14726 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14727 THUMB_VARIANT, do_##ae, do_##te }
14728
14729/* ARM-only variants of all the above. */
14730#define CE(mnem, op, nops, ops, ae) \
14731 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14732
14733#define C3(mnem, op, nops, ops, ae) \
14734 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14735
14736/* Legacy mnemonics that always have conditional infix after the third
14737 character. */
14738#define CL(mnem, op, nops, ops, ae) \
14739 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14740 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14741
14742/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14743#define cCE(mnem, op, nops, ops, ae) \
14744 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14745
14746/* Legacy coprocessor instructions where conditional infix and conditional
14747 suffix are ambiguous. For consistency this includes all FPA instructions,
14748 not just the potentially ambiguous ones. */
14749#define cCL(mnem, op, nops, ops, ae) \
14750 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14751 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14752
14753/* Coprocessor, takes either a suffix or a position-3 infix
14754 (for an FPA corner case). */
14755#define C3E(mnem, op, nops, ops, ae) \
14756 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14757 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14758
14759#define xCM_(m1, m2, m3, op, nops, ops, ae) \
14760 { #m1 #m2 #m3, OPS##nops ops, \
14761 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14762 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14763
14764#define CM(m1, m2, op, nops, ops, ae) \
14765 xCM_(m1, , m2, op, nops, ops, ae), \
14766 xCM_(m1, eq, m2, op, nops, ops, ae), \
14767 xCM_(m1, ne, m2, op, nops, ops, ae), \
14768 xCM_(m1, cs, m2, op, nops, ops, ae), \
14769 xCM_(m1, hs, m2, op, nops, ops, ae), \
14770 xCM_(m1, cc, m2, op, nops, ops, ae), \
14771 xCM_(m1, ul, m2, op, nops, ops, ae), \
14772 xCM_(m1, lo, m2, op, nops, ops, ae), \
14773 xCM_(m1, mi, m2, op, nops, ops, ae), \
14774 xCM_(m1, pl, m2, op, nops, ops, ae), \
14775 xCM_(m1, vs, m2, op, nops, ops, ae), \
14776 xCM_(m1, vc, m2, op, nops, ops, ae), \
14777 xCM_(m1, hi, m2, op, nops, ops, ae), \
14778 xCM_(m1, ls, m2, op, nops, ops, ae), \
14779 xCM_(m1, ge, m2, op, nops, ops, ae), \
14780 xCM_(m1, lt, m2, op, nops, ops, ae), \
14781 xCM_(m1, gt, m2, op, nops, ops, ae), \
14782 xCM_(m1, le, m2, op, nops, ops, ae), \
14783 xCM_(m1, al, m2, op, nops, ops, ae)
14784
14785#define UE(mnem, op, nops, ops, ae) \
14786 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14787
14788#define UF(mnem, op, nops, ops, ae) \
14789 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14790
14791/* Neon data-processing. ARM versions are unconditional with cond=0xf.
14792 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14793 use the same encoding function for each. */
14794#define NUF(mnem, op, nops, ops, enc) \
14795 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14796 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14797
14798/* Neon data processing, version which indirects through neon_enc_tab for
14799 the various overloaded versions of opcodes. */
14800#define nUF(mnem, op, nops, ops, enc) \
14801 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14802 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14803
14804/* Neon insn with conditional suffix for the ARM version, non-overloaded
14805 version. */
14806#define NCE_tag(mnem, op, nops, ops, enc, tag) \
14807 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14808 THUMB_VARIANT, do_##enc, do_##enc }
14809
14810#define NCE(mnem, op, nops, ops, enc) \
14811 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14812
14813#define NCEF(mnem, op, nops, ops, enc) \
14814 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14815
14816/* Neon insn with conditional suffix for the ARM version, overloaded types. */
14817#define nCE_tag(mnem, op, nops, ops, enc, tag) \
14818 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14819 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14820
14821#define nCE(mnem, op, nops, ops, enc) \
14822 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14823
14824#define nCEF(mnem, op, nops, ops, enc) \
14825 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14826
14827#define do_0 0
14828
14829/* Thumb-only, unconditional. */
14830#define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14831
14832static const struct asm_opcode insns[] =
14833{
14834#define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14835#define THUMB_VARIANT &arm_ext_v4t
14836 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c),
14837 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c),
14838 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c),
14839 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c),
14840 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub),
14841 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub),
14842 tCE(add, 0800000, add, 3, (RR, oRR, SHG), arit, t_add_sub),
14843 tC3(adds, 0900000, adds, 3, (RR, oRR, SHG), arit, t_add_sub),
14844 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c),
14845 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c),
14846 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3),
14847 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3),
14848 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c),
14849 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c),
14850 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3),
14851 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3),
14852
14853 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14854 for setting PSR flag bits. They are obsolete in V6 and do not
14855 have Thumb equivalents. */
14856 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
14857 tC3w(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
14858 CL(tstp, 110f000, 2, (RR, SH), cmp),
14859 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
14860 tC3w(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
14861 CL(cmpp, 150f000, 2, (RR, SH), cmp),
14862 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
14863 tC3w(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
14864 CL(cmnp, 170f000, 2, (RR, SH), cmp),
14865
14866 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp),
14867 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp),
14868 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst),
14869 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst),
14870
14871 tCE(ldr, 4100000, ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
14872 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDRGLDR),ldst, t_ldst),
14873 tCE(str, 4000000, str, 2, (RR, ADDRGLDR),ldst, t_ldst),
14874 tC3(strb, 4400000, strb, 2, (RR, ADDRGLDR),ldst, t_ldst),
14875
14876 tCE(stm, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14877 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14878 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14879 tCE(ldm, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14880 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14881 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14882
14883 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi),
14884 TCE(svc, f000000, df00, 1, (EXPi), swi, t_swi),
14885 tCE(b, a000000, b, 1, (EXPr), branch, t_branch),
14886 TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23),
14887
14888 /* Pseudo ops. */
14889 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr),
14890 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
14891 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop),
14892
14893 /* Thumb-compatibility pseudo ops. */
14894 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift),
14895 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift),
14896 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift),
14897 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift),
14898 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift),
14899 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift),
14900 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift),
14901 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift),
14902 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg),
14903 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg),
14904 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop),
14905 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop),
14906
14907 /* These may simplify to neg. */
14908 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
14909 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
14910
14911 TCE(rrx, 1a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rd_rm),
14912 TCE(rrxs, 1b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rd_rm),
14913
14914#undef THUMB_VARIANT
14915#define THUMB_VARIANT &arm_ext_v6
14916 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
14917
14918 /* V1 instructions with no Thumb analogue prior to V6T2. */
14919#undef THUMB_VARIANT
14920#define THUMB_VARIANT &arm_ext_v6t2
14921 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
14922 TC3w(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
14923 CL(teqp, 130f000, 2, (RR, SH), cmp),
14924
14925 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt),
14926 TC3(ldrbt, 4700000, f8100e00, 2, (RR, ADDR), ldstt, t_ldstt),
14927 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt),
14928 TC3(strbt, 4600000, f8000e00, 2, (RR, ADDR), ldstt, t_ldstt),
14929
14930 TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14931 TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14932
14933 TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14934 TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14935
14936 /* V1 instructions with no Thumb analogue at all. */
14937 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit),
14938 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
14939
14940 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
14941 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
14942 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
14943 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
14944 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
14945 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
14946 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
14947 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
14948
14949#undef ARM_VARIANT
14950#define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
14951#undef THUMB_VARIANT
14952#define THUMB_VARIANT &arm_ext_v4t
14953 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
14954 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
14955
14956#undef THUMB_VARIANT
14957#define THUMB_VARIANT &arm_ext_v6t2
14958 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
14959 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
14960
14961 /* Generic coprocessor instructions. */
14962 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
14963 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
14964 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
14965 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
14966 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
14967 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
14968 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
14969
14970#undef ARM_VARIANT
14971#define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
14972 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
14973 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
14974
14975#undef ARM_VARIANT
14976#define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
14977 TCE(mrs, 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs),
14978 TCE(msr, 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr),
14979
14980#undef ARM_VARIANT
14981#define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
14982 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
14983 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
14984 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
14985 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
14986 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
14987 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
14988 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
14989 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
14990
14991#undef ARM_VARIANT
14992#define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
14993#undef THUMB_VARIANT
14994#define THUMB_VARIANT &arm_ext_v4t
14995 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
14996 tC3(strh, 00000b0, strh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
14997 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
14998 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
14999 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15000 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15001
15002#undef ARM_VARIANT
15003#define ARM_VARIANT &arm_ext_v4t_5
15004 /* ARM Architecture 4T. */
15005 /* Note: bx (and blx) are required on V5, even if the processor does
15006 not support Thumb. */
15007 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx),
15008
15009#undef ARM_VARIANT
15010#define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
15011#undef THUMB_VARIANT
15012#define THUMB_VARIANT &arm_ext_v5t
15013 /* Note: blx has 2 variants; the .value coded here is for
15014 BLX(2). Only this variant has conditional execution. */
15015 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
15016 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
15017
15018#undef THUMB_VARIANT
15019#define THUMB_VARIANT &arm_ext_v6t2
15020 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
15021 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15022 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15023 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15024 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15025 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
15026 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
15027 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
15028
15029#undef ARM_VARIANT
15030#define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
15031 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15032 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15033 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15034 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15035
15036 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15037 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15038
15039 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15040 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15041 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15042 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15043
15044 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15045 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15046 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15047 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15048
15049 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15050 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15051
15052 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15053 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15054 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15055 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15056
15057#undef ARM_VARIANT
15058#define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
15059 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld),
15060 TC3(ldrd, 00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
15061 TC3(strd, 00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
15062
15063 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15064 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15065
15066#undef ARM_VARIANT
15067#define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
15068 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
15069
15070#undef ARM_VARIANT
15071#define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
15072#undef THUMB_VARIANT
15073#define THUMB_VARIANT &arm_ext_v6
15074 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
15075 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
15076 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
15077 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
15078 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
15079 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15080 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15081 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15082 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15083 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend),
15084
15085#undef THUMB_VARIANT
15086#define THUMB_VARIANT &arm_ext_v6t2
15087 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex),
15088 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex),
15089 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15090 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15091
15092 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
15093 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
15094
15095/* ARM V6 not included in V7M (eg. integer SIMD). */
15096#undef THUMB_VARIANT
15097#define THUMB_VARIANT &arm_ext_v6_notm
15098 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, t_cps),
15099 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
15100 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
15101 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15102 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15103 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15104 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15105 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15106 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15107 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15108 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15109 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15110 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15111 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15112 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15113 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15114 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15115 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15116 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15117 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15118 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15119 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15120 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15121 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15122 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15123 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15124 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15125 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15126 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15127 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15128 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15129 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15130 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15131 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15132 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15133 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15134 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15135 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15136 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15137 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe),
15138 UF(rfeib, 9900a00, 1, (RRw), rfe),
15139 UF(rfeda, 8100a00, 1, (RRw), rfe),
15140 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe),
15141 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe),
15142 UF(rfefa, 9900a00, 1, (RRw), rfe),
15143 UF(rfeea, 8100a00, 1, (RRw), rfe),
15144 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe),
15145 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15146 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15147 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15148 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15149 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15150 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15151 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15152 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15153 TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15154 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15155 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15156 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15157 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15158 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15159 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15160 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15161 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15162 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15163 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15164 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15165 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15166 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15167 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15168 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15169 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15170 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15171 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15172 TUF(srsia, 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
15173 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
15174 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
15175 TUF(srsdb, 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
15176 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
15177 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
15178 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15179 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15180 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
15181
15182#undef ARM_VARIANT
15183#define ARM_VARIANT &arm_ext_v6k
15184#undef THUMB_VARIANT
15185#define THUMB_VARIANT &arm_ext_v6k
15186 tCE(yield, 320f001, yield, 0, (), noargs, t_hint),
15187 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint),
15188 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint),
15189 tCE(sev, 320f004, sev, 0, (), noargs, t_hint),
15190
15191#undef THUMB_VARIANT
15192#define THUMB_VARIANT &arm_ext_v6_notm
15193 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd),
15194 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd),
15195
15196#undef THUMB_VARIANT
15197#define THUMB_VARIANT &arm_ext_v6t2
15198 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
15199 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
15200 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
15201 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
15202 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
15203
15204#undef ARM_VARIANT
15205#define ARM_VARIANT &arm_ext_v6z
15206 TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc),
15207
15208#undef ARM_VARIANT
15209#define ARM_VARIANT &arm_ext_v6t2
15210 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
15211 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
15212 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
15213 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
15214
15215 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
15216 TCE(movw, 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
15217 TCE(movt, 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
15218 TCE(rbit, 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
15219
15220 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15221 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15222 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15223 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15224
15225 UT(cbnz, b900, 2, (RR, EXP), t_cbz),
15226 UT(cbz, b100, 2, (RR, EXP), t_cbz),
15227 /* ARM does not really have an IT instruction, so always allow it. */
15228#undef ARM_VARIANT
15229#define ARM_VARIANT &arm_ext_v1
15230 TUE(it, 0, bf08, 1, (COND), it, t_it),
15231 TUE(itt, 0, bf0c, 1, (COND), it, t_it),
15232 TUE(ite, 0, bf04, 1, (COND), it, t_it),
15233 TUE(ittt, 0, bf0e, 1, (COND), it, t_it),
15234 TUE(itet, 0, bf06, 1, (COND), it, t_it),
15235 TUE(itte, 0, bf0a, 1, (COND), it, t_it),
15236 TUE(itee, 0, bf02, 1, (COND), it, t_it),
15237 TUE(itttt, 0, bf0f, 1, (COND), it, t_it),
15238 TUE(itett, 0, bf07, 1, (COND), it, t_it),
15239 TUE(ittet, 0, bf0b, 1, (COND), it, t_it),
15240 TUE(iteet, 0, bf03, 1, (COND), it, t_it),
15241 TUE(ittte, 0, bf0d, 1, (COND), it, t_it),
15242 TUE(itete, 0, bf05, 1, (COND), it, t_it),
15243 TUE(ittee, 0, bf09, 1, (COND), it, t_it),
15244 TUE(iteee, 0, bf01, 1, (COND), it, t_it),
15245
15246 /* Thumb2 only instructions. */
15247#undef ARM_VARIANT
15248#define ARM_VARIANT NULL
15249
15250 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
15251 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
15252 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb),
15253 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb),
15254
15255 /* Thumb-2 hardware division instructions (R and M profiles only). */
15256#undef THUMB_VARIANT
15257#define THUMB_VARIANT &arm_ext_div
15258 TCE(sdiv, 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div),
15259 TCE(udiv, 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div),
15260
15261 /* ARM V7 instructions. */
15262#undef ARM_VARIANT
15263#define ARM_VARIANT &arm_ext_v7
15264#undef THUMB_VARIANT
15265#define THUMB_VARIANT &arm_ext_v7
15266 TUF(pli, 450f000, f910f000, 1, (ADDR), pli, t_pld),
15267 TCE(dbg, 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
15268 TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier),
15269 TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier),
15270 TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier),
15271
15272#undef ARM_VARIANT
15273#define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
15274 cCE(wfs, e200110, 1, (RR), rd),
15275 cCE(rfs, e300110, 1, (RR), rd),
15276 cCE(wfc, e400110, 1, (RR), rd),
15277 cCE(rfc, e500110, 1, (RR), rd),
15278
15279 cCL(ldfs, c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
15280 cCL(ldfd, c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
15281 cCL(ldfe, c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
15282 cCL(ldfp, c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
15283
15284 cCL(stfs, c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
15285 cCL(stfd, c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
15286 cCL(stfe, c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
15287 cCL(stfp, c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
15288
15289 cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm),
15290 cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm),
15291 cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm),
15292 cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm),
15293 cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm),
15294 cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm),
15295 cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm),
15296 cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm),
15297 cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm),
15298 cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm),
15299 cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm),
15300 cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm),
15301
15302 cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm),
15303 cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm),
15304 cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm),
15305 cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm),
15306 cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm),
15307 cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm),
15308 cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm),
15309 cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm),
15310 cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm),
15311 cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm),
15312 cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm),
15313 cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm),
15314
15315 cCL(abss, e208100, 2, (RF, RF_IF), rd_rm),
15316 cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm),
15317 cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm),
15318 cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm),
15319 cCL(absd, e208180, 2, (RF, RF_IF), rd_rm),
15320 cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm),
15321 cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm),
15322 cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm),
15323 cCL(abse, e288100, 2, (RF, RF_IF), rd_rm),
15324 cCL(absep, e288120, 2, (RF, RF_IF), rd_rm),
15325 cCL(absem, e288140, 2, (RF, RF_IF), rd_rm),
15326 cCL(absez, e288160, 2, (RF, RF_IF), rd_rm),
15327
15328 cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm),
15329 cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm),
15330 cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm),
15331 cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm),
15332 cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm),
15333 cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm),
15334 cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm),
15335 cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm),
15336 cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm),
15337 cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm),
15338 cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm),
15339 cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm),
15340
15341 cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm),
15342 cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm),
15343 cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm),
15344 cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm),
15345 cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm),
15346 cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm),
15347 cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm),
15348 cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm),
15349 cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm),
15350 cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm),
15351 cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm),
15352 cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm),
15353
15354 cCL(logs, e508100, 2, (RF, RF_IF), rd_rm),
15355 cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm),
15356 cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm),
15357 cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm),
15358 cCL(logd, e508180, 2, (RF, RF_IF), rd_rm),
15359 cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm),
15360 cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm),
15361 cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm),
15362 cCL(loge, e588100, 2, (RF, RF_IF), rd_rm),
15363 cCL(logep, e588120, 2, (RF, RF_IF), rd_rm),
15364 cCL(logem, e588140, 2, (RF, RF_IF), rd_rm),
15365 cCL(logez, e588160, 2, (RF, RF_IF), rd_rm),
15366
15367 cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm),
15368 cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm),
15369 cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm),
15370 cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm),
15371 cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm),
15372 cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm),
15373 cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm),
15374 cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm),
15375 cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm),
15376 cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm),
15377 cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm),
15378 cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm),
15379
15380 cCL(exps, e708100, 2, (RF, RF_IF), rd_rm),
15381 cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm),
15382 cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm),
15383 cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm),
15384 cCL(expd, e708180, 2, (RF, RF_IF), rd_rm),
15385 cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm),
15386 cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm),
15387 cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm),
15388 cCL(expe, e788100, 2, (RF, RF_IF), rd_rm),
15389 cCL(expep, e788120, 2, (RF, RF_IF), rd_rm),
15390 cCL(expem, e788140, 2, (RF, RF_IF), rd_rm),
15391 cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm),
15392
15393 cCL(sins, e808100, 2, (RF, RF_IF), rd_rm),
15394 cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm),
15395 cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm),
15396 cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm),
15397 cCL(sind, e808180, 2, (RF, RF_IF), rd_rm),
15398 cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm),
15399 cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm),
15400 cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm),
15401 cCL(sine, e888100, 2, (RF, RF_IF), rd_rm),
15402 cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm),
15403 cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm),
15404 cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm),
15405
15406 cCL(coss, e908100, 2, (RF, RF_IF), rd_rm),
15407 cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm),
15408 cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm),
15409 cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm),
15410 cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm),
15411 cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm),
15412 cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm),
15413 cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm),
15414 cCL(cose, e988100, 2, (RF, RF_IF), rd_rm),
15415 cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm),
15416 cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm),
15417 cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm),
15418
15419 cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm),
15420 cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm),
15421 cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm),
15422 cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm),
15423 cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm),
15424 cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm),
15425 cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm),
15426 cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm),
15427 cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm),
15428 cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm),
15429 cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm),
15430 cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm),
15431
15432 cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm),
15433 cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm),
15434 cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm),
15435 cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm),
15436 cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm),
15437 cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm),
15438 cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm),
15439 cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm),
15440 cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm),
15441 cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm),
15442 cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm),
15443 cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm),
15444
15445 cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm),
15446 cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm),
15447 cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm),
15448 cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm),
15449 cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm),
15450 cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm),
15451 cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm),
15452 cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm),
15453 cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm),
15454 cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm),
15455 cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm),
15456 cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm),
15457
15458 cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm),
15459 cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm),
15460 cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm),
15461 cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm),
15462 cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm),
15463 cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm),
15464 cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm),
15465 cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm),
15466 cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm),
15467 cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm),
15468 cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm),
15469 cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm),
15470
15471 cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm),
15472 cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm),
15473 cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm),
15474 cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm),
15475 cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm),
15476 cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm),
15477 cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm),
15478 cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm),
15479 cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm),
15480 cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm),
15481 cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm),
15482 cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm),
15483
15484 cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm),
15485 cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm),
15486 cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm),
15487 cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm),
15488 cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm),
15489 cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm),
15490 cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm),
15491 cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm),
15492 cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm),
15493 cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm),
15494 cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm),
15495 cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm),
15496
15497 cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
15498 cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
15499 cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
15500 cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
15501 cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
15502 cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15503 cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15504 cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15505 cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
15506 cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
15507 cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
15508 cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
15509
15510 cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
15511 cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
15512 cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
15513 cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
15514 cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
15515 cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15516 cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15517 cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15518 cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
15519 cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
15520 cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
15521 cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
15522
15523 cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
15524 cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
15525 cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
15526 cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
15527 cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
15528 cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15529 cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15530 cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15531 cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
15532 cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
15533 cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
15534 cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
15535
15536 cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
15537 cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
15538 cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
15539 cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
15540 cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
15541 cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15542 cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15543 cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15544 cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
15545 cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
15546 cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
15547 cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
15548
15549 cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
15550 cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
15551 cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
15552 cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
15553 cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
15554 cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15555 cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15556 cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15557 cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
15558 cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
15559 cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
15560 cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
15561
15562 cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
15563 cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
15564 cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
15565 cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
15566 cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
15567 cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15568 cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15569 cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15570 cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
15571 cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
15572 cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
15573 cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
15574
15575 cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
15576 cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
15577 cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
15578 cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
15579 cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
15580 cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15581 cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15582 cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15583 cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
15584 cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
15585 cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
15586 cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
15587
15588 cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
15589 cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
15590 cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
15591 cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
15592 cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
15593 cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15594 cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15595 cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15596 cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
15597 cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
15598 cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
15599 cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
15600
15601 cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
15602 cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
15603 cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
15604 cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
15605 cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
15606 cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15607 cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15608 cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15609 cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
15610 cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
15611 cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
15612 cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
15613
15614 cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
15615 cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
15616 cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
15617 cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
15618 cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
15619 cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15620 cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15621 cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15622 cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
15623 cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
15624 cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
15625 cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
15626
15627 cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
15628 cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
15629 cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
15630 cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
15631 cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
15632 cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15633 cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15634 cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15635 cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
15636 cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
15637 cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
15638 cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
15639
15640 cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
15641 cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
15642 cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
15643 cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
15644 cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
15645 cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15646 cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15647 cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15648 cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
15649 cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
15650 cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
15651 cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
15652
15653 cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
15654 cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
15655 cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
15656 cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
15657 cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
15658 cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15659 cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15660 cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15661 cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
15662 cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
15663 cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
15664 cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
15665
15666 cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
15667 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
15668 cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
15669 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
15670
15671 cCL(flts, e000110, 2, (RF, RR), rn_rd),
15672 cCL(fltsp, e000130, 2, (RF, RR), rn_rd),
15673 cCL(fltsm, e000150, 2, (RF, RR), rn_rd),
15674 cCL(fltsz, e000170, 2, (RF, RR), rn_rd),
15675 cCL(fltd, e000190, 2, (RF, RR), rn_rd),
15676 cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd),
15677 cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd),
15678 cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd),
15679 cCL(flte, e080110, 2, (RF, RR), rn_rd),
15680 cCL(fltep, e080130, 2, (RF, RR), rn_rd),
15681 cCL(fltem, e080150, 2, (RF, RR), rn_rd),
15682 cCL(fltez, e080170, 2, (RF, RR), rn_rd),
15683
15684 /* The implementation of the FIX instruction is broken on some
15685 assemblers, in that it accepts a precision specifier as well as a
15686 rounding specifier, despite the fact that this is meaningless.
15687 To be more compatible, we accept it as well, though of course it
15688 does not set any bits. */
15689 cCE(fix, e100110, 2, (RR, RF), rd_rm),
15690 cCL(fixp, e100130, 2, (RR, RF), rd_rm),
15691 cCL(fixm, e100150, 2, (RR, RF), rd_rm),
15692 cCL(fixz, e100170, 2, (RR, RF), rd_rm),
15693 cCL(fixsp, e100130, 2, (RR, RF), rd_rm),
15694 cCL(fixsm, e100150, 2, (RR, RF), rd_rm),
15695 cCL(fixsz, e100170, 2, (RR, RF), rd_rm),
15696 cCL(fixdp, e100130, 2, (RR, RF), rd_rm),
15697 cCL(fixdm, e100150, 2, (RR, RF), rd_rm),
15698 cCL(fixdz, e100170, 2, (RR, RF), rd_rm),
15699 cCL(fixep, e100130, 2, (RR, RF), rd_rm),
15700 cCL(fixem, e100150, 2, (RR, RF), rd_rm),
15701 cCL(fixez, e100170, 2, (RR, RF), rd_rm),
15702
15703 /* Instructions that were new with the real FPA, call them V2. */
15704#undef ARM_VARIANT
15705#define ARM_VARIANT &fpu_fpa_ext_v2
15706 cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15707 cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15708 cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15709 cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15710 cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15711 cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15712
15713#undef ARM_VARIANT
15714#define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15715 /* Moves and type conversions. */
15716 cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
15717 cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
15718 cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
15719 cCE(fmstat, ef1fa10, 0, (), noargs),
15720 cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
15721 cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
15722 cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
15723 cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
15724 cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
15725 cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
15726 cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn),
15727 cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
15728
15729 /* Memory operations. */
15730 cCE(flds, d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
15731 cCE(fsts, d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
15732 cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15733 cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15734 cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15735 cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15736 cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15737 cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15738 cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15739 cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15740 cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15741 cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15742 cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15743 cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15744 cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15745 cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15746 cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15747 cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15748
15749 /* Monadic operations. */
15750 cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
15751 cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
15752 cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
15753
15754 /* Dyadic operations. */
15755 cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15756 cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15757 cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15758 cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15759 cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15760 cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15761 cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15762 cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15763 cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15764
15765 /* Comparisons. */
15766 cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
15767 cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
15768 cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
15769 cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
15770
15771#undef ARM_VARIANT
15772#define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15773 /* Moves and type conversions. */
15774 cCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
15775 cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
15776 cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
15777 cCE(fmdhr, e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
15778 cCE(fmdlr, e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
15779 cCE(fmrdh, e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
15780 cCE(fmrdl, e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
15781 cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
15782 cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
15783 cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
15784 cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
15785 cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
15786 cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
15787
15788 /* Memory operations. */
15789 cCE(fldd, d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
15790 cCE(fstd, d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
15791 cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15792 cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15793 cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15794 cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15795 cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15796 cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15797 cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15798 cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15799
15800 /* Monadic operations. */
15801 cCE(fabsd, eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
15802 cCE(fnegd, eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
15803 cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
15804
15805 /* Dyadic operations. */
15806 cCE(faddd, e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15807 cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15808 cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15809 cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15810 cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15811 cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15812 cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15813 cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15814 cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15815
15816 /* Comparisons. */
15817 cCE(fcmpd, eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
15818 cCE(fcmpzd, eb50b40, 1, (RVD), vfp_dp_rd),
15819 cCE(fcmped, eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
15820 cCE(fcmpezd, eb50bc0, 1, (RVD), vfp_dp_rd),
15821
15822#undef ARM_VARIANT
15823#define ARM_VARIANT &fpu_vfp_ext_v2
15824 cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
15825 cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
15826 cCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
15827 cCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
15828
15829/* Instructions which may belong to either the Neon or VFP instruction sets.
15830 Individual encoder functions perform additional architecture checks. */
15831#undef ARM_VARIANT
15832#define ARM_VARIANT &fpu_vfp_ext_v1xd
15833#undef THUMB_VARIANT
15834#define THUMB_VARIANT &fpu_vfp_ext_v1xd
15835 /* These mnemonics are unique to VFP. */
15836 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
15837 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
15838 nCE(vnmul, vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
15839 nCE(vnmla, vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
15840 nCE(vnmls, vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
15841 nCE(vcmp, vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
15842 nCE(vcmpe, vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
15843 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
15844 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
15845 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
15846
15847 /* Mnemonics shared by Neon and VFP. */
15848 nCEF(vmul, vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
15849 nCEF(vmla, vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
15850 nCEF(vmls, vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
15851
15852 nCEF(vadd, vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
15853 nCEF(vsub, vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
15854
15855 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
15856 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
15857
15858 NCE(vldm, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15859 NCE(vldmia, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15860 NCE(vldmdb, d100b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15861 NCE(vstm, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15862 NCE(vstmia, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15863 NCE(vstmdb, d000b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15864 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
15865 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
15866
15867 nCEF(vcvt, vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt),
15868
15869 /* NOTE: All VMOV encoding is special-cased! */
15870 NCE(vmov, 0, 1, (VMOV), neon_mov),
15871 NCE(vmovq, 0, 1, (VMOV), neon_mov),
15872
15873#undef THUMB_VARIANT
15874#define THUMB_VARIANT &fpu_neon_ext_v1
15875#undef ARM_VARIANT
15876#define ARM_VARIANT &fpu_neon_ext_v1
15877 /* Data processing with three registers of the same length. */
15878 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15879 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
15880 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
15881 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
15882 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
15883 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
15884 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
15885 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
15886 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
15887 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15888 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
15889 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
15890 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
15891 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
15892 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
15893 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
15894 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
15895 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
15896 /* If not immediate, fall back to neon_dyadic_i64_su.
15897 shl_imm should accept I8 I16 I32 I64,
15898 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15899 nUF(vshl, vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
15900 nUF(vshlq, vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
15901 nUF(vqshl, vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
15902 nUF(vqshlq, vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
15903 /* Logic ops, types optional & ignored. */
15904 nUF(vand, vand, 2, (RNDQ, NILO), neon_logic),
15905 nUF(vandq, vand, 2, (RNQ, NILO), neon_logic),
15906 nUF(vbic, vbic, 2, (RNDQ, NILO), neon_logic),
15907 nUF(vbicq, vbic, 2, (RNQ, NILO), neon_logic),
15908 nUF(vorr, vorr, 2, (RNDQ, NILO), neon_logic),
15909 nUF(vorrq, vorr, 2, (RNQ, NILO), neon_logic),
15910 nUF(vorn, vorn, 2, (RNDQ, NILO), neon_logic),
15911 nUF(vornq, vorn, 2, (RNQ, NILO), neon_logic),
15912 nUF(veor, veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
15913 nUF(veorq, veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
15914 /* Bitfield ops, untyped. */
15915 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
15916 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
15917 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
15918 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
15919 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
15920 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
15921 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15922 nUF(vabd, vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
15923 nUF(vabdq, vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
15924 nUF(vmax, vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
15925 nUF(vmaxq, vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
15926 nUF(vmin, vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
15927 nUF(vminq, vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
15928 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15929 back to neon_dyadic_if_su. */
15930 nUF(vcge, vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
15931 nUF(vcgeq, vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
15932 nUF(vcgt, vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
15933 nUF(vcgtq, vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
15934 nUF(vclt, vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
15935 nUF(vcltq, vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
15936 nUF(vcle, vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
15937 nUF(vcleq, vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
15938 /* Comparison. Type I8 I16 I32 F32. */
15939 nUF(vceq, vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
15940 nUF(vceqq, vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
15941 /* As above, D registers only. */
15942 nUF(vpmax, vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
15943 nUF(vpmin, vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
15944 /* Int and float variants, signedness unimportant. */
15945 nUF(vmlaq, vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
15946 nUF(vmlsq, vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
15947 nUF(vpadd, vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
15948 /* Add/sub take types I8 I16 I32 I64 F32. */
15949 nUF(vaddq, vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
15950 nUF(vsubq, vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
15951 /* vtst takes sizes 8, 16, 32. */
15952 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
15953 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
15954 /* VMUL takes I8 I16 I32 F32 P8. */
15955 nUF(vmulq, vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
15956 /* VQD{R}MULH takes S16 S32. */
15957 nUF(vqdmulh, vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
15958 nUF(vqdmulhq, vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
15959 nUF(vqrdmulh, vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
15960 nUF(vqrdmulhq, vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
15961 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
15962 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
15963 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
15964 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
15965 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
15966 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
15967 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
15968 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
15969 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
15970 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
15971 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
15972 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
15973
15974 /* Two address, int/float. Types S8 S16 S32 F32. */
15975 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
15976 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
15977
15978 /* Data processing with two registers and a shift amount. */
15979 /* Right shifts, and variants with rounding.
15980 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
15981 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
15982 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
15983 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
15984 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
15985 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
15986 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
15987 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
15988 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
15989 /* Shift and insert. Sizes accepted 8 16 32 64. */
15990 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
15991 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
15992 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
15993 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
15994 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
15995 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
15996 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
15997 /* Right shift immediate, saturating & narrowing, with rounding variants.
15998 Types accepted S16 S32 S64 U16 U32 U64. */
15999 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
16000 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
16001 /* As above, unsigned. Types accepted S16 S32 S64. */
16002 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
16003 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
16004 /* Right shift narrowing. Types accepted I16 I32 I64. */
16005 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
16006 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
16007 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
16008 nUF(vshll, vshll, 3, (RNQ, RND, I32), neon_shll),
16009 /* CVT with optional immediate for fixed-point variant. */
16010 nUF(vcvtq, vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
16011
16012 nUF(vmvn, vmvn, 2, (RNDQ, RNDQ_IMVNb), neon_mvn),
16013 nUF(vmvnq, vmvn, 2, (RNQ, RNDQ_IMVNb), neon_mvn),
16014
16015 /* Data processing, three registers of different lengths. */
16016 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
16017 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
16018 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
16019 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
16020 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
16021 /* If not scalar, fall back to neon_dyadic_long.
16022 Vector types as above, scalar types S16 S32 U16 U32. */
16023 nUF(vmlal, vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
16024 nUF(vmlsl, vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
16025 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
16026 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
16027 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
16028 /* Dyadic, narrowing insns. Types I16 I32 I64. */
16029 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16030 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16031 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16032 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16033 /* Saturating doubling multiplies. Types S16 S32. */
16034 nUF(vqdmlal, vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
16035 nUF(vqdmlsl, vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
16036 nUF(vqdmull, vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
16037 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
16038 S16 S32 U16 U32. */
16039 nUF(vmull, vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
16040
16041 /* Extract. Size 8. */
16042 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
16043 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
16044
16045 /* Two registers, miscellaneous. */
16046 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
16047 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
16048 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
16049 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
16050 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
16051 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
16052 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
16053 /* Vector replicate. Sizes 8 16 32. */
16054 nCE(vdup, vdup, 2, (RNDQ, RR_RNSC), neon_dup),
16055 nCE(vdupq, vdup, 2, (RNQ, RR_RNSC), neon_dup),
16056 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
16057 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
16058 /* VMOVN. Types I16 I32 I64. */
16059 nUF(vmovn, vmovn, 2, (RND, RNQ), neon_movn),
16060 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
16061 nUF(vqmovn, vqmovn, 2, (RND, RNQ), neon_qmovn),
16062 /* VQMOVUN. Types S16 S32 S64. */
16063 nUF(vqmovun, vqmovun, 2, (RND, RNQ), neon_qmovun),
16064 /* VZIP / VUZP. Sizes 8 16 32. */
16065 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
16066 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
16067 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
16068 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
16069 /* VQABS / VQNEG. Types S8 S16 S32. */
16070 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
16071 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
16072 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
16073 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
16074 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
16075 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
16076 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
16077 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
16078 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
16079 /* Reciprocal estimates. Types U32 F32. */
16080 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
16081 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
16082 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
16083 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
16084 /* VCLS. Types S8 S16 S32. */
16085 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
16086 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
16087 /* VCLZ. Types I8 I16 I32. */
16088 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
16089 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
16090 /* VCNT. Size 8. */
16091 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
16092 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
16093 /* Two address, untyped. */
16094 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
16095 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
16096 /* VTRN. Sizes 8 16 32. */
16097 nUF(vtrn, vtrn, 2, (RNDQ, RNDQ), neon_trn),
16098 nUF(vtrnq, vtrn, 2, (RNQ, RNQ), neon_trn),
16099
16100 /* Table lookup. Size 8. */
16101 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
16102 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
16103
16104#undef THUMB_VARIANT
16105#define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
16106#undef ARM_VARIANT
16107#define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
16108 /* Neon element/structure load/store. */
16109 nUF(vld1, vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
16110 nUF(vst1, vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
16111 nUF(vld2, vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
16112 nUF(vst2, vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
16113 nUF(vld3, vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
16114 nUF(vst3, vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
16115 nUF(vld4, vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
16116 nUF(vst4, vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
16117
16118#undef THUMB_VARIANT
16119#define THUMB_VARIANT &fpu_vfp_ext_v3
16120#undef ARM_VARIANT
16121#define ARM_VARIANT &fpu_vfp_ext_v3
16122 cCE(fconsts, eb00a00, 2, (RVS, I255), vfp_sp_const),
16123 cCE(fconstd, eb00b00, 2, (RVD, I255), vfp_dp_const),
16124 cCE(fshtos, eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16125 cCE(fshtod, eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16126 cCE(fsltos, eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16127 cCE(fsltod, eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16128 cCE(fuhtos, ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16129 cCE(fuhtod, ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16130 cCE(fultos, ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16131 cCE(fultod, ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16132 cCE(ftoshs, ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16133 cCE(ftoshd, ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16134 cCE(ftosls, ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16135 cCE(ftosld, ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16136 cCE(ftouhs, ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16137 cCE(ftouhd, ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16138 cCE(ftouls, ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16139 cCE(ftould, ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16140
16141#undef THUMB_VARIANT
16142#undef ARM_VARIANT
16143#define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
16144 cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16145 cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16146 cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16147 cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16148 cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16149 cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16150 cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
16151 cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
16152
16153#undef ARM_VARIANT
16154#define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
16155 cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
16156 cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
16157 cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
16158 cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd),
16159 cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd),
16160 cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd),
16161 cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
16162 cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
16163 cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
16164 cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
16165 cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
16166 cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
16167 cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
16168 cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
16169 cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
16170 cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
16171 cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
16172 cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
16173 cCE(tmcr, e000110, 2, (RIWC_RIWG, RR), rn_rd),
16174 cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
16175 cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16176 cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16177 cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16178 cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16179 cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16180 cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16181 cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
16182 cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
16183 cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
16184 cCE(tmrc, e100110, 2, (RR, RIWC_RIWG), rd_rn),
16185 cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
16186 cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
16187 cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
16188 cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
16189 cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn),
16190 cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn),
16191 cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn),
16192 cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16193 cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16194 cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16195 cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16196 cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16197 cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16198 cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16199 cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16200 cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16201 cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
16202 cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16203 cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16204 cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16205 cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16206 cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16207 cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16208 cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16209 cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16210 cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16211 cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16212 cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16213 cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16214 cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16215 cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16216 cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16217 cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16218 cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16219 cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16220 cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16221 cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16222 cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16223 cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
16224 cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
16225 cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16226 cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16227 cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16228 cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16229 cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16230 cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16231 cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16232 cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16233 cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16234 cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16235 cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16236 cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16237 cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16238 cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16239 cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16240 cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16241 cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16242 cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16243 cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
16244 cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16245 cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16246 cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16247 cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16248 cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16249 cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16250 cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16251 cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16252 cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16253 cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16254 cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16255 cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16256 cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16257 cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16258 cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16259 cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16260 cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16261 cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16262 cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16263 cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16264 cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16265 cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
16266 cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16267 cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16268 cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16269 cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16270 cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16271 cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16272 cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16273 cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16274 cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16275 cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16276 cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16277 cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16278 cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16279 cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16280 cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16281 cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16282 cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16283 cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16284 cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16285 cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16286 cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
16287 cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
16288 cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16289 cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16290 cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16291 cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16292 cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16293 cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16294 cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16295 cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16296 cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16297 cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn),
16298 cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn),
16299 cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn),
16300 cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn),
16301 cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn),
16302 cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn),
16303 cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16304 cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16305 cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16306 cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn),
16307 cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn),
16308 cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn),
16309 cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn),
16310 cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn),
16311 cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn),
16312 cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16313 cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16314 cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16315 cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16316 cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
16317
16318#undef ARM_VARIANT
16319#define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16320 cCE(torvscb, e13f190, 1, (RR), iwmmxt_tandorc),
16321 cCE(torvsch, e53f190, 1, (RR), iwmmxt_tandorc),
16322 cCE(torvscw, e93f190, 1, (RR), iwmmxt_tandorc),
16323 cCE(wabsb, e2001c0, 2, (RIWR, RIWR), rd_rn),
16324 cCE(wabsh, e6001c0, 2, (RIWR, RIWR), rd_rn),
16325 cCE(wabsw, ea001c0, 2, (RIWR, RIWR), rd_rn),
16326 cCE(wabsdiffb, e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16327 cCE(wabsdiffh, e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16328 cCE(wabsdiffw, e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16329 cCE(waddbhusl, e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16330 cCE(waddbhusm, e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16331 cCE(waddhc, e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16332 cCE(waddwc, ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16333 cCE(waddsubhx, ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16334 cCE(wavg4, e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16335 cCE(wavg4r, e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16336 cCE(wmaddsn, ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16337 cCE(wmaddsx, eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16338 cCE(wmaddun, ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16339 cCE(wmaddux, e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16340 cCE(wmerge, e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
16341 cCE(wmiabb, e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16342 cCE(wmiabt, e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16343 cCE(wmiatb, e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16344 cCE(wmiatt, e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16345 cCE(wmiabbn, e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16346 cCE(wmiabtn, e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16347 cCE(wmiatbn, e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16348 cCE(wmiattn, e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16349 cCE(wmiawbb, e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16350 cCE(wmiawbt, e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16351 cCE(wmiawtb, ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16352 cCE(wmiawtt, eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16353 cCE(wmiawbbn, ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16354 cCE(wmiawbtn, ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16355 cCE(wmiawtbn, ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16356 cCE(wmiawttn, ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16357 cCE(wmulsmr, ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16358 cCE(wmulumr, ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16359 cCE(wmulwumr, ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16360 cCE(wmulwsmr, ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16361 cCE(wmulwum, ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16362 cCE(wmulwsm, ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16363 cCE(wmulwl, eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16364 cCE(wqmiabb, e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16365 cCE(wqmiabt, e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16366 cCE(wqmiatb, ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16367 cCE(wqmiatt, eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16368 cCE(wqmiabbn, ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16369 cCE(wqmiabtn, ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16370 cCE(wqmiatbn, ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16371 cCE(wqmiattn, ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16372 cCE(wqmulm, e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16373 cCE(wqmulmr, e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16374 cCE(wqmulwm, ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16375 cCE(wqmulwmr, ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16376 cCE(wsubaddhx, ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16377
16378#undef ARM_VARIANT
16379#define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
16380 cCE(cfldrs, c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
16381 cCE(cfldrd, c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
16382 cCE(cfldr32, c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
16383 cCE(cfldr64, c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
16384 cCE(cfstrs, c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
16385 cCE(cfstrd, c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
16386 cCE(cfstr32, c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
16387 cCE(cfstr64, c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
16388 cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
16389 cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
16390 cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
16391 cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn),
16392 cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd),
16393 cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn),
16394 cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd),
16395 cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn),
16396 cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd),
16397 cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn),
16398 cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn),
16399 cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn),
16400 cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn),
16401 cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn),
16402 cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn),
16403 cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn),
16404 cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn),
16405 cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn),
16406 cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn),
16407 cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn),
16408 cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc),
16409 cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd),
16410 cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn),
16411 cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn),
16412 cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn),
16413 cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn),
16414 cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn),
16415 cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn),
16416 cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn),
16417 cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn),
16418 cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn),
16419 cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn),
16420 cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn),
16421 cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn),
16422 cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple),
16423 cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple),
16424 cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
16425 cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
16426 cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm),
16427 cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
16428 cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
16429 cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
16430 cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn),
16431 cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn),
16432 cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn),
16433 cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn),
16434 cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
16435 cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
16436 cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
16437 cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
16438 cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
16439 cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
16440 cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn),
16441 cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn),
16442 cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn),
16443 cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn),
16444 cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16445 cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
16446 cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16447 cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
16448 cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16449 cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
16450 cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16451 cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16452 cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
16453 cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
16454 cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
16455 cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
16456};
16457#undef ARM_VARIANT
16458#undef THUMB_VARIANT
16459#undef TCE
16460#undef TCM
16461#undef TUE
16462#undef TUF
16463#undef TCC
16464#undef cCE
16465#undef cCL
16466#undef C3E
16467#undef CE
16468#undef CM
16469#undef UE
16470#undef UF
16471#undef UT
16472#undef NUF
16473#undef nUF
16474#undef NCE
16475#undef nCE
16476#undef OPS0
16477#undef OPS1
16478#undef OPS2
16479#undef OPS3
16480#undef OPS4
16481#undef OPS5
16482#undef OPS6
16483#undef do_0
16484
16485/* MD interface: bits in the object file. */
16486
16487/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16488 for use in the a.out file, and stores them in the array pointed to by buf.
16489 This knows about the endian-ness of the target machine and does
16490 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16491 2 (short) and 4 (long) Floating numbers are put out as a series of
16492 LITTLENUMS (shorts, here at least). */
16493
16494void
16495md_number_to_chars (char * buf, valueT val, int n)
16496{
16497 if (target_big_endian)
16498 number_to_chars_bigendian (buf, val, n);
16499 else
16500 number_to_chars_littleendian (buf, val, n);
16501}
16502
16503static valueT
16504md_chars_to_number (char * buf, int n)
16505{
16506 valueT result = 0;
16507 unsigned char * where = (unsigned char *) buf;
16508
16509 if (target_big_endian)
16510 {
16511 while (n--)
16512 {
16513 result <<= 8;
16514 result |= (*where++ & 255);
16515 }
16516 }
16517 else
16518 {
16519 while (n--)
16520 {
16521 result <<= 8;
16522 result |= (where[n] & 255);
16523 }
16524 }
16525
16526 return result;
16527}
16528
16529/* MD interface: Sections. */
16530
16531/* Estimate the size of a frag before relaxing. Assume everything fits in
16532 2 bytes. */
16533
16534int
16535md_estimate_size_before_relax (fragS * fragp,
16536 segT segtype ATTRIBUTE_UNUSED)
16537{
16538 fragp->fr_var = 2;
16539 return 2;
16540}
16541
16542/* Convert a machine dependent frag. */
16543
16544void
16545md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
16546{
16547 unsigned long insn;
16548 unsigned long old_op;
16549 char *buf;
16550 expressionS exp;
16551 fixS *fixp;
16552 int reloc_type;
16553 int pc_rel;
16554 int opcode;
16555
16556 buf = fragp->fr_literal + fragp->fr_fix;
16557
16558 old_op = bfd_get_16(abfd, buf);
16559 if (fragp->fr_symbol) {
16560 exp.X_op = O_symbol;
16561 exp.X_add_symbol = fragp->fr_symbol;
16562 } else {
16563 exp.X_op = O_constant;
16564 }
16565 exp.X_add_number = fragp->fr_offset;
16566 opcode = fragp->fr_subtype;
16567 switch (opcode)
16568 {
16569 case T_MNEM_ldr_pc:
16570 case T_MNEM_ldr_pc2:
16571 case T_MNEM_ldr_sp:
16572 case T_MNEM_str_sp:
16573 case T_MNEM_ldr:
16574 case T_MNEM_ldrb:
16575 case T_MNEM_ldrh:
16576 case T_MNEM_str:
16577 case T_MNEM_strb:
16578 case T_MNEM_strh:
16579 if (fragp->fr_var == 4)
16580 {
16581 insn = THUMB_OP32(opcode);
16582 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
16583 {
16584 insn |= (old_op & 0x700) << 4;
16585 }
16586 else
16587 {
16588 insn |= (old_op & 7) << 12;
16589 insn |= (old_op & 0x38) << 13;
16590 }
16591 insn |= 0x00000c00;
16592 put_thumb32_insn (buf, insn);
16593 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
16594 }
16595 else
16596 {
16597 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
16598 }
16599 pc_rel = (opcode == T_MNEM_ldr_pc2);
16600 break;
16601 case T_MNEM_adr:
16602 if (fragp->fr_var == 4)
16603 {
16604 insn = THUMB_OP32 (opcode);
16605 insn |= (old_op & 0xf0) << 4;
16606 put_thumb32_insn (buf, insn);
16607 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
16608 }
16609 else
16610 {
16611 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
16612 exp.X_add_number -= 4;
16613 }
16614 pc_rel = 1;
16615 break;
16616 case T_MNEM_mov:
16617 case T_MNEM_movs:
16618 case T_MNEM_cmp:
16619 case T_MNEM_cmn:
16620 if (fragp->fr_var == 4)
16621 {
16622 int r0off = (opcode == T_MNEM_mov
16623 || opcode == T_MNEM_movs) ? 0 : 8;
16624 insn = THUMB_OP32 (opcode);
16625 insn = (insn & 0xe1ffffff) | 0x10000000;
16626 insn |= (old_op & 0x700) << r0off;
16627 put_thumb32_insn (buf, insn);
16628 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
16629 }
16630 else
16631 {
16632 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
16633 }
16634 pc_rel = 0;
16635 break;
16636 case T_MNEM_b:
16637 if (fragp->fr_var == 4)
16638 {
16639 insn = THUMB_OP32(opcode);
16640 put_thumb32_insn (buf, insn);
16641 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
16642 }
16643 else
16644 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
16645 pc_rel = 1;
16646 break;
16647 case T_MNEM_bcond:
16648 if (fragp->fr_var == 4)
16649 {
16650 insn = THUMB_OP32(opcode);
16651 insn |= (old_op & 0xf00) << 14;
16652 put_thumb32_insn (buf, insn);
16653 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
16654 }
16655 else
16656 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
16657 pc_rel = 1;
16658 break;
16659 case T_MNEM_add_sp:
16660 case T_MNEM_add_pc:
16661 case T_MNEM_inc_sp:
16662 case T_MNEM_dec_sp:
16663 if (fragp->fr_var == 4)
16664 {
16665 /* ??? Choose between add and addw. */
16666 insn = THUMB_OP32 (opcode);
16667 insn |= (old_op & 0xf0) << 4;
16668 put_thumb32_insn (buf, insn);
16669 if (opcode == T_MNEM_add_pc)
16670 reloc_type = BFD_RELOC_ARM_T32_IMM12;
16671 else
16672 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
16673 }
16674 else
16675 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
16676 pc_rel = 0;
16677 break;
16678
16679 case T_MNEM_addi:
16680 case T_MNEM_addis:
16681 case T_MNEM_subi:
16682 case T_MNEM_subis:
16683 if (fragp->fr_var == 4)
16684 {
16685 insn = THUMB_OP32 (opcode);
16686 insn |= (old_op & 0xf0) << 4;
16687 insn |= (old_op & 0xf) << 16;
16688 put_thumb32_insn (buf, insn);
16689 if (insn & (1 << 20))
16690 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
16691 else
16692 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
16693 }
16694 else
16695 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
16696 pc_rel = 0;
16697 break;
16698 default:
16699 abort();
16700 }
16701 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
16702 reloc_type);
16703 fixp->fx_file = fragp->fr_file;
16704 fixp->fx_line = fragp->fr_line;
16705 fragp->fr_fix += fragp->fr_var;
16706}
16707
16708/* Return the size of a relaxable immediate operand instruction.
16709 SHIFT and SIZE specify the form of the allowable immediate. */
16710static int
16711relax_immediate (fragS *fragp, int size, int shift)
16712{
16713 offsetT offset;
16714 offsetT mask;
16715 offsetT low;
16716
16717 /* ??? Should be able to do better than this. */
16718 if (fragp->fr_symbol)
16719 return 4;
16720
16721 low = (1 << shift) - 1;
16722 mask = (1 << (shift + size)) - (1 << shift);
16723 offset = fragp->fr_offset;
16724 /* Force misaligned offsets to 32-bit variant. */
16725 if (offset & low)
16726 return 4;
16727 if (offset & ~mask)
16728 return 4;
16729 return 2;
16730}
16731
16732/* Get the address of a symbol during relaxation. */
16733static addressT
16734relaxed_symbol_addr(fragS *fragp, long stretch)
16735{
16736 fragS *sym_frag;
16737 addressT addr;
16738 symbolS *sym;
16739
16740 sym = fragp->fr_symbol;
16741 sym_frag = symbol_get_frag (sym);
16742 know (S_GET_SEGMENT (sym) != absolute_section
16743 || sym_frag == &zero_address_frag);
16744 addr = S_GET_VALUE (sym) + fragp->fr_offset;
16745
16746 /* If frag has yet to be reached on this pass, assume it will
16747 move by STRETCH just as we did. If this is not so, it will
16748 be because some frag between grows, and that will force
16749 another pass. */
16750
16751 if (stretch != 0
16752 && sym_frag->relax_marker != fragp->relax_marker)
16753 addr += stretch;
16754
16755 return addr;
16756}
16757
16758/* Return the size of a relaxable adr pseudo-instruction or PC-relative
16759 load. */
16760static int
16761relax_adr (fragS *fragp, asection *sec, long stretch)
16762{
16763 addressT addr;
16764 offsetT val;
16765
16766 /* Assume worst case for symbols not known to be in the same section. */
16767 if (!S_IS_DEFINED(fragp->fr_symbol)
16768 || sec != S_GET_SEGMENT (fragp->fr_symbol))
16769 return 4;
16770
16771 val = relaxed_symbol_addr(fragp, stretch);
16772 addr = fragp->fr_address + fragp->fr_fix;
16773 addr = (addr + 4) & ~3;
16774 /* Force misaligned targets to 32-bit variant. */
16775 if (val & 3)
16776 return 4;
16777 val -= addr;
16778 if (val < 0 || val > 1020)
16779 return 4;
16780 return 2;
16781}
16782
16783/* Return the size of a relaxable add/sub immediate instruction. */
16784static int
16785relax_addsub (fragS *fragp, asection *sec)
16786{
16787 char *buf;
16788 int op;
16789
16790 buf = fragp->fr_literal + fragp->fr_fix;
16791 op = bfd_get_16(sec->owner, buf);
16792 if ((op & 0xf) == ((op >> 4) & 0xf))
16793 return relax_immediate (fragp, 8, 0);
16794 else
16795 return relax_immediate (fragp, 3, 0);
16796}
16797
16798
16799/* Return the size of a relaxable branch instruction. BITS is the
16800 size of the offset field in the narrow instruction. */
16801
16802static int
16803relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
16804{
16805 addressT addr;
16806 offsetT val;
16807 offsetT limit;
16808
16809 /* Assume worst case for symbols not known to be in the same section. */
16810 if (!S_IS_DEFINED(fragp->fr_symbol)
16811 || sec != S_GET_SEGMENT (fragp->fr_symbol))
16812 return 4;
16813
16814 val = relaxed_symbol_addr(fragp, stretch);
16815 addr = fragp->fr_address + fragp->fr_fix + 4;
16816 val -= addr;
16817
16818 /* Offset is a signed value *2 */
16819 limit = 1 << bits;
16820 if (val >= limit || val < -limit)
16821 return 4;
16822 return 2;
16823}
16824
16825
16826/* Relax a machine dependent frag. This returns the amount by which
16827 the current size of the frag should change. */
16828
16829int
16830arm_relax_frag (asection *sec, fragS *fragp, long stretch)
16831{
16832 int oldsize;
16833 int newsize;
16834
16835 oldsize = fragp->fr_var;
16836 switch (fragp->fr_subtype)
16837 {
16838 case T_MNEM_ldr_pc2:
16839 newsize = relax_adr(fragp, sec, stretch);
16840 break;
16841 case T_MNEM_ldr_pc:
16842 case T_MNEM_ldr_sp:
16843 case T_MNEM_str_sp:
16844 newsize = relax_immediate(fragp, 8, 2);
16845 break;
16846 case T_MNEM_ldr:
16847 case T_MNEM_str:
16848 newsize = relax_immediate(fragp, 5, 2);
16849 break;
16850 case T_MNEM_ldrh:
16851 case T_MNEM_strh:
16852 newsize = relax_immediate(fragp, 5, 1);
16853 break;
16854 case T_MNEM_ldrb:
16855 case T_MNEM_strb:
16856 newsize = relax_immediate(fragp, 5, 0);
16857 break;
16858 case T_MNEM_adr:
16859 newsize = relax_adr(fragp, sec, stretch);
16860 break;
16861 case T_MNEM_mov:
16862 case T_MNEM_movs:
16863 case T_MNEM_cmp:
16864 case T_MNEM_cmn:
16865 newsize = relax_immediate(fragp, 8, 0);
16866 break;
16867 case T_MNEM_b:
16868 newsize = relax_branch(fragp, sec, 11, stretch);
16869 break;
16870 case T_MNEM_bcond:
16871 newsize = relax_branch(fragp, sec, 8, stretch);
16872 break;
16873 case T_MNEM_add_sp:
16874 case T_MNEM_add_pc:
16875 newsize = relax_immediate (fragp, 8, 2);
16876 break;
16877 case T_MNEM_inc_sp:
16878 case T_MNEM_dec_sp:
16879 newsize = relax_immediate (fragp, 7, 2);
16880 break;
16881 case T_MNEM_addi:
16882 case T_MNEM_addis:
16883 case T_MNEM_subi:
16884 case T_MNEM_subis:
16885 newsize = relax_addsub (fragp, sec);
16886 break;
16887 default:
16888 abort();
16889 }
16890
16891 fragp->fr_var = newsize;
16892 /* Freeze wide instructions that are at or before the same location as
16893 in the previous pass. This avoids infinite loops.
16894 Don't freeze them unconditionally because targets may be artificialy
16895 misaligned by the expansion of preceeding frags. */
16896 if (stretch <= 0 && newsize > 2)
16897 {
16898 md_convert_frag (sec->owner, sec, fragp);
16899 frag_wane(fragp);
16900 }
16901
16902 return newsize - oldsize;
16903}
16904
16905/* Round up a section size to the appropriate boundary. */
16906
16907valueT
16908md_section_align (segT segment ATTRIBUTE_UNUSED,
16909 valueT size)
16910{
16911#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
16912 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
16913 {
16914 /* For a.out, force the section size to be aligned. If we don't do
16915 this, BFD will align it for us, but it will not write out the
16916 final bytes of the section. This may be a bug in BFD, but it is
16917 easier to fix it here since that is how the other a.out targets
16918 work. */
16919 int align;
16920
16921 align = bfd_get_section_alignment (stdoutput, segment);
16922 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
16923 }
16924#endif
16925
16926 return size;
16927}
16928
16929/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
16930 of an rs_align_code fragment. */
16931
16932void
16933arm_handle_align (fragS * fragP)
16934{
16935 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
16936 static char const thumb_noop[2] = { 0xc0, 0x46 };
16937 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
16938 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
16939
16940 int bytes, fix, noop_size;
16941 char * p;
16942 const char * noop;
16943
16944 if (fragP->fr_type != rs_align_code)
16945 return;
16946
16947 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
16948 p = fragP->fr_literal + fragP->fr_fix;
16949 fix = 0;
16950
16951 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
16952 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
16953
16954 if (fragP->tc_frag_data)
16955 {
16956 if (target_big_endian)
16957 noop = thumb_bigend_noop;
16958 else
16959 noop = thumb_noop;
16960 noop_size = sizeof (thumb_noop);
16961 }
16962 else
16963 {
16964 if (target_big_endian)
16965 noop = arm_bigend_noop;
16966 else
16967 noop = arm_noop;
16968 noop_size = sizeof (arm_noop);
16969 }
16970
16971 if (bytes & (noop_size - 1))
16972 {
16973 fix = bytes & (noop_size - 1);
16974 memset (p, 0, fix);
16975 p += fix;
16976 bytes -= fix;
16977 }
16978
16979 while (bytes >= noop_size)
16980 {
16981 memcpy (p, noop, noop_size);
16982 p += noop_size;
16983 bytes -= noop_size;
16984 fix += noop_size;
16985 }
16986
16987 fragP->fr_fix += fix;
16988 fragP->fr_var = noop_size;
16989}
16990
16991/* Called from md_do_align. Used to create an alignment
16992 frag in a code section. */
16993
16994void
16995arm_frag_align_code (int n, int max)
16996{
16997 char * p;
16998
16999 /* We assume that there will never be a requirement
17000 to support alignments greater than 32 bytes. */
17001 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
17002 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
17003
17004 p = frag_var (rs_align_code,
17005 MAX_MEM_FOR_RS_ALIGN_CODE,
17006 1,
17007 (relax_substateT) max,
17008 (symbolS *) NULL,
17009 (offsetT) n,
17010 (char *) NULL);
17011 *p = 0;
17012}
17013
17014/* Perform target specific initialisation of a frag. */
17015
17016void
17017arm_init_frag (fragS * fragP)
17018{
17019 /* Record whether this frag is in an ARM or a THUMB area. */
17020 fragP->tc_frag_data = thumb_mode;
17021}
17022
17023#ifdef OBJ_ELF
17024/* When we change sections we need to issue a new mapping symbol. */
17025
17026void
17027arm_elf_change_section (void)
17028{
17029 flagword flags;
17030 segment_info_type *seginfo;
17031
17032 /* Link an unlinked unwind index table section to the .text section. */
17033 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
17034 && elf_linked_to_section (now_seg) == NULL)
17035 elf_linked_to_section (now_seg) = text_section;
17036
17037 if (!SEG_NORMAL (now_seg))
17038 return;
17039
17040 flags = bfd_get_section_flags (stdoutput, now_seg);
17041
17042 /* We can ignore sections that only contain debug info. */
17043 if ((flags & SEC_ALLOC) == 0)
17044 return;
17045
17046 seginfo = seg_info (now_seg);
17047 mapstate = seginfo->tc_segment_info_data.mapstate;
17048 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency;
17049}
17050
17051int
17052arm_elf_section_type (const char * str, size_t len)
17053{
17054 if (len == 5 && strncmp (str, "exidx", 5) == 0)
17055 return SHT_ARM_EXIDX;
17056
17057 return -1;
17058}
17059
17060/* Code to deal with unwinding tables. */
17061
17062static void add_unwind_adjustsp (offsetT);
17063
17064/* Cenerate and deferred unwind frame offset. */
17065
17066static void
17067flush_pending_unwind (void)
17068{
17069 offsetT offset;
17070
17071 offset = unwind.pending_offset;
17072 unwind.pending_offset = 0;
17073 if (offset != 0)
17074 add_unwind_adjustsp (offset);
17075}
17076
17077/* Add an opcode to this list for this function. Two-byte opcodes should
17078 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
17079 order. */
17080
17081static void
17082add_unwind_opcode (valueT op, int length)
17083{
17084 /* Add any deferred stack adjustment. */
17085 if (unwind.pending_offset)
17086 flush_pending_unwind ();
17087
17088 unwind.sp_restored = 0;
17089
17090 if (unwind.opcode_count + length > unwind.opcode_alloc)
17091 {
17092 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
17093 if (unwind.opcodes)
17094 unwind.opcodes = xrealloc (unwind.opcodes,
17095 unwind.opcode_alloc);
17096 else
17097 unwind.opcodes = xmalloc (unwind.opcode_alloc);
17098 }
17099 while (length > 0)
17100 {
17101 length--;
17102 unwind.opcodes[unwind.opcode_count] = op & 0xff;
17103 op >>= 8;
17104 unwind.opcode_count++;
17105 }
17106}
17107
17108/* Add unwind opcodes to adjust the stack pointer. */
17109
17110static void
17111add_unwind_adjustsp (offsetT offset)
17112{
17113 valueT op;
17114
17115 if (offset > 0x200)
17116 {
17117 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17118 char bytes[5];
17119 int n;
17120 valueT o;
17121
17122 /* Long form: 0xb2, uleb128. */
17123 /* This might not fit in a word so add the individual bytes,
17124 remembering the list is built in reverse order. */
17125 o = (valueT) ((offset - 0x204) >> 2);
17126 if (o == 0)
17127 add_unwind_opcode (0, 1);
17128
17129 /* Calculate the uleb128 encoding of the offset. */
17130 n = 0;
17131 while (o)
17132 {
17133 bytes[n] = o & 0x7f;
17134 o >>= 7;
17135 if (o)
17136 bytes[n] |= 0x80;
17137 n++;
17138 }
17139 /* Add the insn. */
17140 for (; n; n--)
17141 add_unwind_opcode (bytes[n - 1], 1);
17142 add_unwind_opcode (0xb2, 1);
17143 }
17144 else if (offset > 0x100)
17145 {
17146 /* Two short opcodes. */
17147 add_unwind_opcode (0x3f, 1);
17148 op = (offset - 0x104) >> 2;
17149 add_unwind_opcode (op, 1);
17150 }
17151 else if (offset > 0)
17152 {
17153 /* Short opcode. */
17154 op = (offset - 4) >> 2;
17155 add_unwind_opcode (op, 1);
17156 }
17157 else if (offset < 0)
17158 {
17159 offset = -offset;
17160 while (offset > 0x100)
17161 {
17162 add_unwind_opcode (0x7f, 1);
17163 offset -= 0x100;
17164 }
17165 op = ((offset - 4) >> 2) | 0x40;
17166 add_unwind_opcode (op, 1);
17167 }
17168}
17169
17170/* Finish the list of unwind opcodes for this function. */
17171static void
17172finish_unwind_opcodes (void)
17173{
17174 valueT op;
17175
17176 if (unwind.fp_used)
17177 {
17178 /* Adjust sp as necessary. */
17179 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
17180 flush_pending_unwind ();
17181
17182 /* After restoring sp from the frame pointer. */
17183 op = 0x90 | unwind.fp_reg;
17184 add_unwind_opcode (op, 1);
17185 }
17186 else
17187 flush_pending_unwind ();
17188}
17189
17190
17191/* Start an exception table entry. If idx is nonzero this is an index table
17192 entry. */
17193
17194static void
17195start_unwind_section (const segT text_seg, int idx)
17196{
17197 const char * text_name;
17198 const char * prefix;
17199 const char * prefix_once;
17200 const char * group_name;
17201 size_t prefix_len;
17202 size_t text_len;
17203 char * sec_name;
17204 size_t sec_name_len;
17205 int type;
17206 int flags;
17207 int linkonce;
17208
17209 if (idx)
17210 {
17211 prefix = ELF_STRING_ARM_unwind;
17212 prefix_once = ELF_STRING_ARM_unwind_once;
17213 type = SHT_ARM_EXIDX;
17214 }
17215 else
17216 {
17217 prefix = ELF_STRING_ARM_unwind_info;
17218 prefix_once = ELF_STRING_ARM_unwind_info_once;
17219 type = SHT_PROGBITS;
17220 }
17221
17222 text_name = segment_name (text_seg);
17223 if (streq (text_name, ".text"))
17224 text_name = "";
17225
17226 if (strncmp (text_name, ".gnu.linkonce.t.",
17227 strlen (".gnu.linkonce.t.")) == 0)
17228 {
17229 prefix = prefix_once;
17230 text_name += strlen (".gnu.linkonce.t.");
17231 }
17232
17233 prefix_len = strlen (prefix);
17234 text_len = strlen (text_name);
17235 sec_name_len = prefix_len + text_len;
17236 sec_name = xmalloc (sec_name_len + 1);
17237 memcpy (sec_name, prefix, prefix_len);
17238 memcpy (sec_name + prefix_len, text_name, text_len);
17239 sec_name[prefix_len + text_len] = '\0';
17240
17241 flags = SHF_ALLOC;
17242 linkonce = 0;
17243 group_name = 0;
17244
17245 /* Handle COMDAT group. */
17246 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
17247 {
17248 group_name = elf_group_name (text_seg);
17249 if (group_name == NULL)
17250 {
17251 as_bad ("Group section `%s' has no group signature",
17252 segment_name (text_seg));
17253 ignore_rest_of_line ();
17254 return;
17255 }
17256 flags |= SHF_GROUP;
17257 linkonce = 1;
17258 }
17259
17260 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
17261
17262 /* Set the setion link for index tables. */
17263 if (idx)
17264 elf_linked_to_section (now_seg) = text_seg;
17265}
17266
17267
17268/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17269 personality routine data. Returns zero, or the index table value for
17270 and inline entry. */
17271
17272static valueT
17273create_unwind_entry (int have_data)
17274{
17275 int size;
17276 addressT where;
17277 char *ptr;
17278 /* The current word of data. */
17279 valueT data;
17280 /* The number of bytes left in this word. */
17281 int n;
17282
17283 finish_unwind_opcodes ();
17284
17285 /* Remember the current text section. */
17286 unwind.saved_seg = now_seg;
17287 unwind.saved_subseg = now_subseg;
17288
17289 start_unwind_section (now_seg, 0);
17290
17291 if (unwind.personality_routine == NULL)
17292 {
17293 if (unwind.personality_index == -2)
17294 {
17295 if (have_data)
17296 as_bad (_("handerdata in cantunwind frame"));
17297 return 1; /* EXIDX_CANTUNWIND. */
17298 }
17299
17300 /* Use a default personality routine if none is specified. */
17301 if (unwind.personality_index == -1)
17302 {
17303 if (unwind.opcode_count > 3)
17304 unwind.personality_index = 1;
17305 else
17306 unwind.personality_index = 0;
17307 }
17308
17309 /* Space for the personality routine entry. */
17310 if (unwind.personality_index == 0)
17311 {
17312 if (unwind.opcode_count > 3)
17313 as_bad (_("too many unwind opcodes for personality routine 0"));
17314
17315 if (!have_data)
17316 {
17317 /* All the data is inline in the index table. */
17318 data = 0x80;
17319 n = 3;
17320 while (unwind.opcode_count > 0)
17321 {
17322 unwind.opcode_count--;
17323 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
17324 n--;
17325 }
17326
17327 /* Pad with "finish" opcodes. */
17328 while (n--)
17329 data = (data << 8) | 0xb0;
17330
17331 return data;
17332 }
17333 size = 0;
17334 }
17335 else
17336 /* We get two opcodes "free" in the first word. */
17337 size = unwind.opcode_count - 2;
17338 }
17339 else
17340 /* An extra byte is required for the opcode count. */
17341 size = unwind.opcode_count + 1;
17342
17343 size = (size + 3) >> 2;
17344 if (size > 0xff)
17345 as_bad (_("too many unwind opcodes"));
17346
17347 frag_align (2, 0, 0);
17348 record_alignment (now_seg, 2);
17349 unwind.table_entry = expr_build_dot ();
17350
17351 /* Allocate the table entry. */
17352 ptr = frag_more ((size << 2) + 4);
17353 where = frag_now_fix () - ((size << 2) + 4);
17354
17355 switch (unwind.personality_index)
17356 {
17357 case -1:
17358 /* ??? Should this be a PLT generating relocation? */
17359 /* Custom personality routine. */
17360 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
17361 BFD_RELOC_ARM_PREL31);
17362
17363 where += 4;
17364 ptr += 4;
17365
17366 /* Set the first byte to the number of additional words. */
17367 data = size - 1;
17368 n = 3;
17369 break;
17370
17371 /* ABI defined personality routines. */
17372 case 0:
17373 /* Three opcodes bytes are packed into the first word. */
17374 data = 0x80;
17375 n = 3;
17376 break;
17377
17378 case 1:
17379 case 2:
17380 /* The size and first two opcode bytes go in the first word. */
17381 data = ((0x80 + unwind.personality_index) << 8) | size;
17382 n = 2;
17383 break;
17384
17385 default:
17386 /* Should never happen. */
17387 abort ();
17388 }
17389
17390 /* Pack the opcodes into words (MSB first), reversing the list at the same
17391 time. */
17392 while (unwind.opcode_count > 0)
17393 {
17394 if (n == 0)
17395 {
17396 md_number_to_chars (ptr, data, 4);
17397 ptr += 4;
17398 n = 4;
17399 data = 0;
17400 }
17401 unwind.opcode_count--;
17402 n--;
17403 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
17404 }
17405
17406 /* Finish off the last word. */
17407 if (n < 4)
17408 {
17409 /* Pad with "finish" opcodes. */
17410 while (n--)
17411 data = (data << 8) | 0xb0;
17412
17413 md_number_to_chars (ptr, data, 4);
17414 }
17415
17416 if (!have_data)
17417 {
17418 /* Add an empty descriptor if there is no user-specified data. */
17419 ptr = frag_more (4);
17420 md_number_to_chars (ptr, 0, 4);
17421 }
17422
17423 return 0;
17424}
17425
17426
17427/* Initialize the DWARF-2 unwind information for this procedure. */
17428
17429void
17430tc_arm_frame_initial_instructions (void)
17431{
17432 cfi_add_CFA_def_cfa (REG_SP, 0);
17433}
17434#endif /* OBJ_ELF */
17435
17436/* Convert REGNAME to a DWARF-2 register number. */
17437
17438int
17439tc_arm_regname_to_dw2regnum (char *regname)
17440{
17441 int reg = arm_reg_parse (®name, REG_TYPE_RN);
17442
17443 if (reg == FAIL)
17444 return -1;
17445
17446 return reg;
17447}
17448
17449#ifdef TE_PE
17450void
17451tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
17452{
17453 expressionS expr;
17454
17455 expr.X_op = O_secrel;
17456 expr.X_add_symbol = symbol;
17457 expr.X_add_number = 0;
17458 emit_expr (&expr, size);
17459}
17460#endif
17461
17462/* MD interface: Symbol and relocation handling. */
17463
17464/* Return the address within the segment that a PC-relative fixup is
17465 relative to. For ARM, PC-relative fixups applied to instructions
17466 are generally relative to the location of the fixup plus 8 bytes.
17467 Thumb branches are offset by 4, and Thumb loads relative to PC
17468 require special handling. */
17469
17470long
17471md_pcrel_from_section (fixS * fixP, segT seg)
17472{
17473 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
17474
17475 /* If this is pc-relative and we are going to emit a relocation
17476 then we just want to put out any pipeline compensation that the linker
17477 will need. Otherwise we want to use the calculated base.
17478 For WinCE we skip the bias for externals as well, since this
17479 is how the MS ARM-CE assembler behaves and we want to be compatible. */
17480 if (fixP->fx_pcrel
17481 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
17482 || (arm_force_relocation (fixP)
17483#ifdef TE_WINCE
17484 && !S_IS_EXTERNAL (fixP->fx_addsy)
17485#endif
17486 )))
17487 base = 0;
17488
17489 switch (fixP->fx_r_type)
17490 {
17491 /* PC relative addressing on the Thumb is slightly odd as the
17492 bottom two bits of the PC are forced to zero for the
17493 calculation. This happens *after* application of the
17494 pipeline offset. However, Thumb adrl already adjusts for
17495 this, so we need not do it again. */
17496 case BFD_RELOC_ARM_THUMB_ADD:
17497 return base & ~3;
17498
17499 case BFD_RELOC_ARM_THUMB_OFFSET:
17500 case BFD_RELOC_ARM_T32_OFFSET_IMM:
17501 case BFD_RELOC_ARM_T32_ADD_PC12:
17502 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
17503 return (base + 4) & ~3;
17504
17505 /* Thumb branches are simply offset by +4. */
17506 case BFD_RELOC_THUMB_PCREL_BRANCH7:
17507 case BFD_RELOC_THUMB_PCREL_BRANCH9:
17508 case BFD_RELOC_THUMB_PCREL_BRANCH12:
17509 case BFD_RELOC_THUMB_PCREL_BRANCH20:
17510 case BFD_RELOC_THUMB_PCREL_BRANCH23:
17511 case BFD_RELOC_THUMB_PCREL_BRANCH25:
17512 case BFD_RELOC_THUMB_PCREL_BLX:
17513 return base + 4;
17514
17515 /* ARM mode branches are offset by +8. However, the Windows CE
17516 loader expects the relocation not to take this into account. */
17517 case BFD_RELOC_ARM_PCREL_BRANCH:
17518 case BFD_RELOC_ARM_PCREL_CALL:
17519 case BFD_RELOC_ARM_PCREL_JUMP:
17520 case BFD_RELOC_ARM_PCREL_BLX:
17521 case BFD_RELOC_ARM_PLT32:
17522#ifdef TE_WINCE
17523 /* When handling fixups immediately, because we have already
17524 discovered the value of a symbol, or the address of the frag involved
17525 we must account for the offset by +8, as the OS loader will never see the reloc.
17526 see fixup_segment() in write.c
17527 The S_IS_EXTERNAL test handles the case of global symbols.
17528 Those need the calculated base, not just the pipe compensation the linker will need. */
17529 if (fixP->fx_pcrel
17530 && fixP->fx_addsy != NULL
17531 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
17532 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
17533 return base + 8;
17534 return base;
17535#else
17536 return base + 8;
17537#endif
17538
17539 /* ARM mode loads relative to PC are also offset by +8. Unlike
17540 branches, the Windows CE loader *does* expect the relocation
17541 to take this into account. */
17542 case BFD_RELOC_ARM_OFFSET_IMM:
17543 case BFD_RELOC_ARM_OFFSET_IMM8:
17544 case BFD_RELOC_ARM_HWLITERAL:
17545 case BFD_RELOC_ARM_LITERAL:
17546 case BFD_RELOC_ARM_CP_OFF_IMM:
17547 return base + 8;
17548
17549
17550 /* Other PC-relative relocations are un-offset. */
17551 default:
17552 return base;
17553 }
17554}
17555
17556/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17557 Otherwise we have no need to default values of symbols. */
17558
17559symbolS *
17560md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
17561{
17562#ifdef OBJ_ELF
17563 if (name[0] == '_' && name[1] == 'G'
17564 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
17565 {
17566 if (!GOT_symbol)
17567 {
17568 if (symbol_find (name))
17569 as_bad ("GOT already in the symbol table");
17570
17571 GOT_symbol = symbol_new (name, undefined_section,
17572 (valueT) 0, & zero_address_frag);
17573 }
17574
17575 return GOT_symbol;
17576 }
17577#endif
17578
17579 return 0;
17580}
17581
17582/* Subroutine of md_apply_fix. Check to see if an immediate can be
17583 computed as two separate immediate values, added together. We
17584 already know that this value cannot be computed by just one ARM
17585 instruction. */
17586
17587static unsigned int
17588validate_immediate_twopart (unsigned int val,
17589 unsigned int * highpart)
17590{
17591 unsigned int a;
17592 unsigned int i;
17593
17594 for (i = 0; i < 32; i += 2)
17595 if (((a = rotate_left (val, i)) & 0xff) != 0)
17596 {
17597 if (a & 0xff00)
17598 {
17599 if (a & ~ 0xffff)
17600 continue;
17601 * highpart = (a >> 8) | ((i + 24) << 7);
17602 }
17603 else if (a & 0xff0000)
17604 {
17605 if (a & 0xff000000)
17606 continue;
17607 * highpart = (a >> 16) | ((i + 16) << 7);
17608 }
17609 else
17610 {
17611 assert (a & 0xff000000);
17612 * highpart = (a >> 24) | ((i + 8) << 7);
17613 }
17614
17615 return (a & 0xff) | (i << 7);
17616 }
17617
17618 return FAIL;
17619}
17620
17621static int
17622validate_offset_imm (unsigned int val, int hwse)
17623{
17624 if ((hwse && val > 255) || val > 4095)
17625 return FAIL;
17626 return val;
17627}
17628
17629/* Subroutine of md_apply_fix. Do those data_ops which can take a
17630 negative immediate constant by altering the instruction. A bit of
17631 a hack really.
17632 MOV <-> MVN
17633 AND <-> BIC
17634 ADC <-> SBC
17635 by inverting the second operand, and
17636 ADD <-> SUB
17637 CMP <-> CMN
17638 by negating the second operand. */
17639
17640static int
17641negate_data_op (unsigned long * instruction,
17642 unsigned long value)
17643{
17644 int op, new_inst;
17645 unsigned long negated, inverted;
17646
17647 negated = encode_arm_immediate (-value);
17648 inverted = encode_arm_immediate (~value);
17649
17650 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
17651 switch (op)
17652 {
17653 /* First negates. */
17654 case OPCODE_SUB: /* ADD <-> SUB */
17655 new_inst = OPCODE_ADD;
17656 value = negated;
17657 break;
17658
17659 case OPCODE_ADD:
17660 new_inst = OPCODE_SUB;
17661 value = negated;
17662 break;
17663
17664 case OPCODE_CMP: /* CMP <-> CMN */
17665 new_inst = OPCODE_CMN;
17666 value = negated;
17667 break;
17668
17669 case OPCODE_CMN:
17670 new_inst = OPCODE_CMP;
17671 value = negated;
17672 break;
17673
17674 /* Now Inverted ops. */
17675 case OPCODE_MOV: /* MOV <-> MVN */
17676 new_inst = OPCODE_MVN;
17677 value = inverted;
17678 break;
17679
17680 case OPCODE_MVN:
17681 new_inst = OPCODE_MOV;
17682 value = inverted;
17683 break;
17684
17685 case OPCODE_AND: /* AND <-> BIC */
17686 new_inst = OPCODE_BIC;
17687 value = inverted;
17688 break;
17689
17690 case OPCODE_BIC:
17691 new_inst = OPCODE_AND;
17692 value = inverted;
17693 break;
17694
17695 case OPCODE_ADC: /* ADC <-> SBC */
17696 new_inst = OPCODE_SBC;
17697 value = inverted;
17698 break;
17699
17700 case OPCODE_SBC:
17701 new_inst = OPCODE_ADC;
17702 value = inverted;
17703 break;
17704
17705 /* We cannot do anything. */
17706 default:
17707 return FAIL;
17708 }
17709
17710 if (value == (unsigned) FAIL)
17711 return FAIL;
17712
17713 *instruction &= OPCODE_MASK;
17714 *instruction |= new_inst << DATA_OP_SHIFT;
17715 return value;
17716}
17717
17718/* Like negate_data_op, but for Thumb-2. */
17719
17720static unsigned int
17721thumb32_negate_data_op (offsetT *instruction, unsigned int value)
17722{
17723 int op, new_inst;
17724 int rd;
17725 unsigned int negated, inverted;
17726
17727 negated = encode_thumb32_immediate (-value);
17728 inverted = encode_thumb32_immediate (~value);
17729
17730 rd = (*instruction >> 8) & 0xf;
17731 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
17732 switch (op)
17733 {
17734 /* ADD <-> SUB. Includes CMP <-> CMN. */
17735 case T2_OPCODE_SUB:
17736 new_inst = T2_OPCODE_ADD;
17737 value = negated;
17738 break;
17739
17740 case T2_OPCODE_ADD:
17741 new_inst = T2_OPCODE_SUB;
17742 value = negated;
17743 break;
17744
17745 /* ORR <-> ORN. Includes MOV <-> MVN. */
17746 case T2_OPCODE_ORR:
17747 new_inst = T2_OPCODE_ORN;
17748 value = inverted;
17749 break;
17750
17751 case T2_OPCODE_ORN:
17752 new_inst = T2_OPCODE_ORR;
17753 value = inverted;
17754 break;
17755
17756 /* AND <-> BIC. TST has no inverted equivalent. */
17757 case T2_OPCODE_AND:
17758 new_inst = T2_OPCODE_BIC;
17759 if (rd == 15)
17760 value = FAIL;
17761 else
17762 value = inverted;
17763 break;
17764
17765 case T2_OPCODE_BIC:
17766 new_inst = T2_OPCODE_AND;
17767 value = inverted;
17768 break;
17769
17770 /* ADC <-> SBC */
17771 case T2_OPCODE_ADC:
17772 new_inst = T2_OPCODE_SBC;
17773 value = inverted;
17774 break;
17775
17776 case T2_OPCODE_SBC:
17777 new_inst = T2_OPCODE_ADC;
17778 value = inverted;
17779 break;
17780
17781 /* We cannot do anything. */
17782 default:
17783 return FAIL;
17784 }
17785
17786 if (value == (unsigned int)FAIL)
17787 return FAIL;
17788
17789 *instruction &= T2_OPCODE_MASK;
17790 *instruction |= new_inst << T2_DATA_OP_SHIFT;
17791 return value;
17792}
17793
17794/* Read a 32-bit thumb instruction from buf. */
17795static unsigned long
17796get_thumb32_insn (char * buf)
17797{
17798 unsigned long insn;
17799 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
17800 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
17801
17802 return insn;
17803}
17804
17805
17806/* We usually want to set the low bit on the address of thumb function
17807 symbols. In particular .word foo - . should have the low bit set.
17808 Generic code tries to fold the difference of two symbols to
17809 a constant. Prevent this and force a relocation when the first symbols
17810 is a thumb function. */
17811int
17812arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
17813{
17814 if (op == O_subtract
17815 && l->X_op == O_symbol
17816 && r->X_op == O_symbol
17817 && THUMB_IS_FUNC (l->X_add_symbol))
17818 {
17819 l->X_op = O_subtract;
17820 l->X_op_symbol = r->X_add_symbol;
17821 l->X_add_number -= r->X_add_number;
17822 return 1;
17823 }
17824 /* Process as normal. */
17825 return 0;
17826}
17827
17828void
17829md_apply_fix (fixS * fixP,
17830 valueT * valP,
17831 segT seg)
17832{
17833 offsetT value = * valP;
17834 offsetT newval;
17835 unsigned int newimm;
17836 unsigned long temp;
17837 int sign;
17838 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
17839
17840 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
17841
17842 /* Note whether this will delete the relocation. */
17843
17844 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
17845 fixP->fx_done = 1;
17846
17847 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17848 consistency with the behavior on 32-bit hosts. Remember value
17849 for emit_reloc. */
17850 value &= 0xffffffff;
17851 value ^= 0x80000000;
17852 value -= 0x80000000;
17853
17854 *valP = value;
17855 fixP->fx_addnumber = value;
17856
17857 /* Same treatment for fixP->fx_offset. */
17858 fixP->fx_offset &= 0xffffffff;
17859 fixP->fx_offset ^= 0x80000000;
17860 fixP->fx_offset -= 0x80000000;
17861
17862 switch (fixP->fx_r_type)
17863 {
17864 case BFD_RELOC_NONE:
17865 /* This will need to go in the object file. */
17866 fixP->fx_done = 0;
17867 break;
17868
17869 case BFD_RELOC_ARM_IMMEDIATE:
17870 /* We claim that this fixup has been processed here,
17871 even if in fact we generate an error because we do
17872 not have a reloc for it, so tc_gen_reloc will reject it. */
17873 fixP->fx_done = 1;
17874
17875 if (fixP->fx_addsy
17876 && ! S_IS_DEFINED (fixP->fx_addsy))
17877 {
17878 as_bad_where (fixP->fx_file, fixP->fx_line,
17879 _("undefined symbol %s used as an immediate value"),
17880 S_GET_NAME (fixP->fx_addsy));
17881 break;
17882 }
17883
17884 newimm = encode_arm_immediate (value);
17885 temp = md_chars_to_number (buf, INSN_SIZE);
17886
17887 /* If the instruction will fail, see if we can fix things up by
17888 changing the opcode. */
17889 if (newimm == (unsigned int) FAIL
17890 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
17891 {
17892 as_bad_where (fixP->fx_file, fixP->fx_line,
17893 _("invalid constant (%lx) after fixup"),
17894 (unsigned long) value);
17895 break;
17896 }
17897
17898 newimm |= (temp & 0xfffff000);
17899 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
17900 break;
17901
17902 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
17903 {
17904 unsigned int highpart = 0;
17905 unsigned int newinsn = 0xe1a00000; /* nop. */
17906
17907 newimm = encode_arm_immediate (value);
17908 temp = md_chars_to_number (buf, INSN_SIZE);
17909
17910 /* If the instruction will fail, see if we can fix things up by
17911 changing the opcode. */
17912 if (newimm == (unsigned int) FAIL
17913 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
17914 {
17915 /* No ? OK - try using two ADD instructions to generate
17916 the value. */
17917 newimm = validate_immediate_twopart (value, & highpart);
17918
17919 /* Yes - then make sure that the second instruction is
17920 also an add. */
17921 if (newimm != (unsigned int) FAIL)
17922 newinsn = temp;
17923 /* Still No ? Try using a negated value. */
17924 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
17925 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
17926 /* Otherwise - give up. */
17927 else
17928 {
17929 as_bad_where (fixP->fx_file, fixP->fx_line,
17930 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
17931 (long) value);
17932 break;
17933 }
17934
17935 /* Replace the first operand in the 2nd instruction (which
17936 is the PC) with the destination register. We have
17937 already added in the PC in the first instruction and we
17938 do not want to do it again. */
17939 newinsn &= ~ 0xf0000;
17940 newinsn |= ((newinsn & 0x0f000) << 4);
17941 }
17942
17943 newimm |= (temp & 0xfffff000);
17944 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
17945
17946 highpart |= (newinsn & 0xfffff000);
17947 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
17948 }
17949 break;
17950
17951 case BFD_RELOC_ARM_OFFSET_IMM:
17952 if (!fixP->fx_done && seg->use_rela_p)
17953 value = 0;
17954
17955 case BFD_RELOC_ARM_LITERAL:
17956 sign = value >= 0;
17957
17958 if (value < 0)
17959 value = - value;
17960
17961 if (validate_offset_imm (value, 0) == FAIL)
17962 {
17963 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
17964 as_bad_where (fixP->fx_file, fixP->fx_line,
17965 _("invalid literal constant: pool needs to be closer"));
17966 else
17967 as_bad_where (fixP->fx_file, fixP->fx_line,
17968 _("bad immediate value for offset (%ld)"),
17969 (long) value);
17970 break;
17971 }
17972
17973 newval = md_chars_to_number (buf, INSN_SIZE);
17974 newval &= 0xff7ff000;
17975 newval |= value | (sign ? INDEX_UP : 0);
17976 md_number_to_chars (buf, newval, INSN_SIZE);
17977 break;
17978
17979 case BFD_RELOC_ARM_OFFSET_IMM8:
17980 case BFD_RELOC_ARM_HWLITERAL:
17981 sign = value >= 0;
17982
17983 if (value < 0)
17984 value = - value;
17985
17986 if (validate_offset_imm (value, 1) == FAIL)
17987 {
17988 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
17989 as_bad_where (fixP->fx_file, fixP->fx_line,
17990 _("invalid literal constant: pool needs to be closer"));
17991 else
17992 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
17993 (long) value);
17994 break;
17995 }
17996
17997 newval = md_chars_to_number (buf, INSN_SIZE);
17998 newval &= 0xff7ff0f0;
17999 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
18000 md_number_to_chars (buf, newval, INSN_SIZE);
18001 break;
18002
18003 case BFD_RELOC_ARM_T32_OFFSET_U8:
18004 if (value < 0 || value > 1020 || value % 4 != 0)
18005 as_bad_where (fixP->fx_file, fixP->fx_line,
18006 _("bad immediate value for offset (%ld)"), (long) value);
18007 value /= 4;
18008
18009 newval = md_chars_to_number (buf+2, THUMB_SIZE);
18010 newval |= value;
18011 md_number_to_chars (buf+2, newval, THUMB_SIZE);
18012 break;
18013
18014 case BFD_RELOC_ARM_T32_OFFSET_IMM:
18015 /* This is a complicated relocation used for all varieties of Thumb32
18016 load/store instruction with immediate offset:
18017
18018 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
18019 *4, optional writeback(W)
18020 (doubleword load/store)
18021
18022 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
18023 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
18024 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
18025 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
18026 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
18027
18028 Uppercase letters indicate bits that are already encoded at
18029 this point. Lowercase letters are our problem. For the
18030 second block of instructions, the secondary opcode nybble
18031 (bits 8..11) is present, and bit 23 is zero, even if this is
18032 a PC-relative operation. */
18033 newval = md_chars_to_number (buf, THUMB_SIZE);
18034 newval <<= 16;
18035 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
18036
18037 if ((newval & 0xf0000000) == 0xe0000000)
18038 {
18039 /* Doubleword load/store: 8-bit offset, scaled by 4. */
18040 if (value >= 0)
18041 newval |= (1 << 23);
18042 else
18043 value = -value;
18044 if (value % 4 != 0)
18045 {
18046 as_bad_where (fixP->fx_file, fixP->fx_line,
18047 _("offset not a multiple of 4"));
18048 break;
18049 }
18050 value /= 4;
18051 if (value > 0xff)
18052 {
18053 as_bad_where (fixP->fx_file, fixP->fx_line,
18054 _("offset out of range"));
18055 break;
18056 }
18057 newval &= ~0xff;
18058 }
18059 else if ((newval & 0x000f0000) == 0x000f0000)
18060 {
18061 /* PC-relative, 12-bit offset. */
18062 if (value >= 0)
18063 newval |= (1 << 23);
18064 else
18065 value = -value;
18066 if (value > 0xfff)
18067 {
18068 as_bad_where (fixP->fx_file, fixP->fx_line,
18069 _("offset out of range"));
18070 break;
18071 }
18072 newval &= ~0xfff;
18073 }
18074 else if ((newval & 0x00000100) == 0x00000100)
18075 {
18076 /* Writeback: 8-bit, +/- offset. */
18077 if (value >= 0)
18078 newval |= (1 << 9);
18079 else
18080 value = -value;
18081 if (value > 0xff)
18082 {
18083 as_bad_where (fixP->fx_file, fixP->fx_line,
18084 _("offset out of range"));
18085 break;
18086 }
18087 newval &= ~0xff;
18088 }
18089 else if ((newval & 0x00000f00) == 0x00000e00)
18090 {
18091 /* T-instruction: positive 8-bit offset. */
18092 if (value < 0 || value > 0xff)
18093 {
18094 as_bad_where (fixP->fx_file, fixP->fx_line,
18095 _("offset out of range"));
18096 break;
18097 }
18098 newval &= ~0xff;
18099 newval |= value;
18100 }
18101 else
18102 {
18103 /* Positive 12-bit or negative 8-bit offset. */
18104 int limit;
18105 if (value >= 0)
18106 {
18107 newval |= (1 << 23);
18108 limit = 0xfff;
18109 }
18110 else
18111 {
18112 value = -value;
18113 limit = 0xff;
18114 }
18115 if (value > limit)
18116 {
18117 as_bad_where (fixP->fx_file, fixP->fx_line,
18118 _("offset out of range"));
18119 break;
18120 }
18121 newval &= ~limit;
18122 }
18123
18124 newval |= value;
18125 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
18126 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
18127 break;
18128
18129 case BFD_RELOC_ARM_SHIFT_IMM:
18130 newval = md_chars_to_number (buf, INSN_SIZE);
18131 if (((unsigned long) value) > 32
18132 || (value == 32
18133 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
18134 {
18135 as_bad_where (fixP->fx_file, fixP->fx_line,
18136 _("shift expression is too large"));
18137 break;
18138 }
18139
18140 if (value == 0)
18141 /* Shifts of zero must be done as lsl. */
18142 newval &= ~0x60;
18143 else if (value == 32)
18144 value = 0;
18145 newval &= 0xfffff07f;
18146 newval |= (value & 0x1f) << 7;
18147 md_number_to_chars (buf, newval, INSN_SIZE);
18148 break;
18149
18150 case BFD_RELOC_ARM_T32_IMMEDIATE:
18151 case BFD_RELOC_ARM_T32_ADD_IMM:
18152 case BFD_RELOC_ARM_T32_IMM12:
18153 case BFD_RELOC_ARM_T32_ADD_PC12:
18154 /* We claim that this fixup has been processed here,
18155 even if in fact we generate an error because we do
18156 not have a reloc for it, so tc_gen_reloc will reject it. */
18157 fixP->fx_done = 1;
18158
18159 if (fixP->fx_addsy
18160 && ! S_IS_DEFINED (fixP->fx_addsy))
18161 {
18162 as_bad_where (fixP->fx_file, fixP->fx_line,
18163 _("undefined symbol %s used as an immediate value"),
18164 S_GET_NAME (fixP->fx_addsy));
18165 break;
18166 }
18167
18168 newval = md_chars_to_number (buf, THUMB_SIZE);
18169 newval <<= 16;
18170 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
18171
18172 newimm = FAIL;
18173 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
18174 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
18175 {
18176 newimm = encode_thumb32_immediate (value);
18177 if (newimm == (unsigned int) FAIL)
18178 newimm = thumb32_negate_data_op (&newval, value);
18179 }
18180 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
18181 && newimm == (unsigned int) FAIL)
18182 {
18183 /* Turn add/sum into addw/subw. */
18184 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
18185 newval = (newval & 0xfeffffff) | 0x02000000;
18186
18187 /* 12 bit immediate for addw/subw. */
18188 if (value < 0)
18189 {
18190 value = -value;
18191 newval ^= 0x00a00000;
18192 }
18193 if (value > 0xfff)
18194 newimm = (unsigned int) FAIL;
18195 else
18196 newimm = value;
18197 }
18198
18199 if (newimm == (unsigned int)FAIL)
18200 {
18201 as_bad_where (fixP->fx_file, fixP->fx_line,
18202 _("invalid constant (%lx) after fixup"),
18203 (unsigned long) value);
18204 break;
18205 }
18206
18207 newval |= (newimm & 0x800) << 15;
18208 newval |= (newimm & 0x700) << 4;
18209 newval |= (newimm & 0x0ff);
18210
18211 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
18212 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
18213 break;
18214
18215 case BFD_RELOC_ARM_SMC:
18216 if (((unsigned long) value) > 0xffff)
18217 as_bad_where (fixP->fx_file, fixP->fx_line,
18218 _("invalid smc expression"));
18219 newval = md_chars_to_number (buf, INSN_SIZE);
18220 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
18221 md_number_to_chars (buf, newval, INSN_SIZE);
18222 break;
18223
18224 case BFD_RELOC_ARM_SWI:
18225 if (fixP->tc_fix_data != 0)
18226 {
18227 if (((unsigned long) value) > 0xff)
18228 as_bad_where (fixP->fx_file, fixP->fx_line,
18229 _("invalid swi expression"));
18230 newval = md_chars_to_number (buf, THUMB_SIZE);
18231 newval |= value;
18232 md_number_to_chars (buf, newval, THUMB_SIZE);
18233 }
18234 else
18235 {
18236 if (((unsigned long) value) > 0x00ffffff)
18237 as_bad_where (fixP->fx_file, fixP->fx_line,
18238 _("invalid swi expression"));
18239 newval = md_chars_to_number (buf, INSN_SIZE);
18240 newval |= value;
18241 md_number_to_chars (buf, newval, INSN_SIZE);
18242 }
18243 break;
18244
18245 case BFD_RELOC_ARM_MULTI:
18246 if (((unsigned long) value) > 0xffff)
18247 as_bad_where (fixP->fx_file, fixP->fx_line,
18248 _("invalid expression in load/store multiple"));
18249 newval = value | md_chars_to_number (buf, INSN_SIZE);
18250 md_number_to_chars (buf, newval, INSN_SIZE);
18251 break;
18252
18253#ifdef OBJ_ELF
18254 case BFD_RELOC_ARM_PCREL_CALL:
18255 newval = md_chars_to_number (buf, INSN_SIZE);
18256 if ((newval & 0xf0000000) == 0xf0000000)
18257 temp = 1;
18258 else
18259 temp = 3;
18260 goto arm_branch_common;
18261
18262 case BFD_RELOC_ARM_PCREL_JUMP:
18263 case BFD_RELOC_ARM_PLT32:
18264#endif
18265 case BFD_RELOC_ARM_PCREL_BRANCH:
18266 temp = 3;
18267 goto arm_branch_common;
18268
18269 case BFD_RELOC_ARM_PCREL_BLX:
18270 temp = 1;
18271 arm_branch_common:
18272 /* We are going to store value (shifted right by two) in the
18273 instruction, in a 24 bit, signed field. Bits 26 through 32 either
18274 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
18275 also be be clear. */
18276 if (value & temp)
18277 as_bad_where (fixP->fx_file, fixP->fx_line,
18278 _("misaligned branch destination"));
18279 if ((value & (offsetT)0xfe000000) != (offsetT)0
18280 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
18281 as_bad_where (fixP->fx_file, fixP->fx_line,
18282 _("branch out of range"));
18283
18284 if (fixP->fx_done || !seg->use_rela_p)
18285 {
18286 newval = md_chars_to_number (buf, INSN_SIZE);
18287 newval |= (value >> 2) & 0x00ffffff;
18288 /* Set the H bit on BLX instructions. */
18289 if (temp == 1)
18290 {
18291 if (value & 2)
18292 newval |= 0x01000000;
18293 else
18294 newval &= ~0x01000000;
18295 }
18296 md_number_to_chars (buf, newval, INSN_SIZE);
18297 }
18298 break;
18299
18300 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
18301 /* CBZ can only branch forward. */
18302
18303 /* Attempts to use CBZ to branch to the next instruction
18304 (which, strictly speaking, are prohibited) will be turned into
18305 no-ops.
18306
18307 FIXME: It may be better to remove the instruction completely and
18308 perform relaxation. */
18309 if (value == -2)
18310 {
18311 newval = md_chars_to_number (buf, THUMB_SIZE);
18312 newval = 0xbf00; /* NOP encoding T1 */
18313 md_number_to_chars (buf, newval, THUMB_SIZE);
18314 }
18315 else
18316 {
18317 if (value & ~0x7e)
18318 as_bad_where (fixP->fx_file, fixP->fx_line,
18319 _("branch out of range"));
18320
18321 if (fixP->fx_done || !seg->use_rela_p)
18322 {
18323 newval = md_chars_to_number (buf, THUMB_SIZE);
18324 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
18325 md_number_to_chars (buf, newval, THUMB_SIZE);
18326 }
18327 }
18328 break;
18329
18330 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
18331 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
18332 as_bad_where (fixP->fx_file, fixP->fx_line,
18333 _("branch out of range"));
18334
18335 if (fixP->fx_done || !seg->use_rela_p)
18336 {
18337 newval = md_chars_to_number (buf, THUMB_SIZE);
18338 newval |= (value & 0x1ff) >> 1;
18339 md_number_to_chars (buf, newval, THUMB_SIZE);
18340 }
18341 break;
18342
18343 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
18344 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
18345 as_bad_where (fixP->fx_file, fixP->fx_line,
18346 _("branch out of range"));
18347
18348 if (fixP->fx_done || !seg->use_rela_p)
18349 {
18350 newval = md_chars_to_number (buf, THUMB_SIZE);
18351 newval |= (value & 0xfff) >> 1;
18352 md_number_to_chars (buf, newval, THUMB_SIZE);
18353 }
18354 break;
18355
18356 case BFD_RELOC_THUMB_PCREL_BRANCH20:
18357 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
18358 as_bad_where (fixP->fx_file, fixP->fx_line,
18359 _("conditional branch out of range"));
18360
18361 if (fixP->fx_done || !seg->use_rela_p)
18362 {
18363 offsetT newval2;
18364 addressT S, J1, J2, lo, hi;
18365
18366 S = (value & 0x00100000) >> 20;
18367 J2 = (value & 0x00080000) >> 19;
18368 J1 = (value & 0x00040000) >> 18;
18369 hi = (value & 0x0003f000) >> 12;
18370 lo = (value & 0x00000ffe) >> 1;
18371
18372 newval = md_chars_to_number (buf, THUMB_SIZE);
18373 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
18374 newval |= (S << 10) | hi;
18375 newval2 |= (J1 << 13) | (J2 << 11) | lo;
18376 md_number_to_chars (buf, newval, THUMB_SIZE);
18377 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
18378 }
18379 break;
18380
18381 case BFD_RELOC_THUMB_PCREL_BLX:
18382 case BFD_RELOC_THUMB_PCREL_BRANCH23:
18383 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
18384 as_bad_where (fixP->fx_file, fixP->fx_line,
18385 _("branch out of range"));
18386
18387 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
18388 /* For a BLX instruction, make sure that the relocation is rounded up
18389 to a word boundary. This follows the semantics of the instruction
18390 which specifies that bit 1 of the target address will come from bit
18391 1 of the base address. */
18392 value = (value + 1) & ~ 1;
18393
18394 if (fixP->fx_done || !seg->use_rela_p)
18395 {
18396 offsetT newval2;
18397
18398 newval = md_chars_to_number (buf, THUMB_SIZE);
18399 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
18400 newval |= (value & 0x7fffff) >> 12;
18401 newval2 |= (value & 0xfff) >> 1;
18402 md_number_to_chars (buf, newval, THUMB_SIZE);
18403 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
18404 }
18405 break;
18406
18407 case BFD_RELOC_THUMB_PCREL_BRANCH25:
18408 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
18409 as_bad_where (fixP->fx_file, fixP->fx_line,
18410 _("branch out of range"));
18411
18412 if (fixP->fx_done || !seg->use_rela_p)
18413 {
18414 offsetT newval2;
18415 addressT S, I1, I2, lo, hi;
18416
18417 S = (value & 0x01000000) >> 24;
18418 I1 = (value & 0x00800000) >> 23;
18419 I2 = (value & 0x00400000) >> 22;
18420 hi = (value & 0x003ff000) >> 12;
18421 lo = (value & 0x00000ffe) >> 1;
18422
18423 I1 = !(I1 ^ S);
18424 I2 = !(I2 ^ S);
18425
18426 newval = md_chars_to_number (buf, THUMB_SIZE);
18427 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
18428 newval |= (S << 10) | hi;
18429 newval2 |= (I1 << 13) | (I2 << 11) | lo;
18430 md_number_to_chars (buf, newval, THUMB_SIZE);
18431 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
18432 }
18433 break;
18434
18435 case BFD_RELOC_8:
18436 if (fixP->fx_done || !seg->use_rela_p)
18437 md_number_to_chars (buf, value, 1);
18438 break;
18439
18440 case BFD_RELOC_16:
18441 if (fixP->fx_done || !seg->use_rela_p)
18442 md_number_to_chars (buf, value, 2);
18443 break;
18444
18445#ifdef OBJ_ELF
18446 case BFD_RELOC_ARM_TLS_GD32:
18447 case BFD_RELOC_ARM_TLS_LE32:
18448 case BFD_RELOC_ARM_TLS_IE32:
18449 case BFD_RELOC_ARM_TLS_LDM32:
18450 case BFD_RELOC_ARM_TLS_LDO32:
18451 S_SET_THREAD_LOCAL (fixP->fx_addsy);
18452 /* fall through */
18453
18454 case BFD_RELOC_ARM_GOT32:
18455 case BFD_RELOC_ARM_GOTOFF:
18456 case BFD_RELOC_ARM_TARGET2:
18457 if (fixP->fx_done || !seg->use_rela_p)
18458 md_number_to_chars (buf, 0, 4);
18459 break;
18460#endif
18461
18462 case BFD_RELOC_RVA:
18463 case BFD_RELOC_32:
18464 case BFD_RELOC_ARM_TARGET1:
18465 case BFD_RELOC_ARM_ROSEGREL32:
18466 case BFD_RELOC_ARM_SBREL32:
18467 case BFD_RELOC_32_PCREL:
18468#ifdef TE_PE
18469 case BFD_RELOC_32_SECREL:
18470#endif
18471 if (fixP->fx_done || !seg->use_rela_p)
18472#ifdef TE_WINCE
18473 /* For WinCE we only do this for pcrel fixups. */
18474 if (fixP->fx_done || fixP->fx_pcrel)
18475#endif
18476 md_number_to_chars (buf, value, 4);
18477 break;
18478
18479#ifdef OBJ_ELF
18480 case BFD_RELOC_ARM_PREL31:
18481 if (fixP->fx_done || !seg->use_rela_p)
18482 {
18483 newval = md_chars_to_number (buf, 4) & 0x80000000;
18484 if ((value ^ (value >> 1)) & 0x40000000)
18485 {
18486 as_bad_where (fixP->fx_file, fixP->fx_line,
18487 _("rel31 relocation overflow"));
18488 }
18489 newval |= value & 0x7fffffff;
18490 md_number_to_chars (buf, newval, 4);
18491 }
18492 break;
18493#endif
18494
18495 case BFD_RELOC_ARM_CP_OFF_IMM:
18496 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
18497 if (value < -1023 || value > 1023 || (value & 3))
18498 as_bad_where (fixP->fx_file, fixP->fx_line,
18499 _("co-processor offset out of range"));
18500 cp_off_common:
18501 sign = value >= 0;
18502 if (value < 0)
18503 value = -value;
18504 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
18505 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
18506 newval = md_chars_to_number (buf, INSN_SIZE);
18507 else
18508 newval = get_thumb32_insn (buf);
18509 newval &= 0xff7fff00;
18510 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
18511 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
18512 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
18513 md_number_to_chars (buf, newval, INSN_SIZE);
18514 else
18515 put_thumb32_insn (buf, newval);
18516 break;
18517
18518 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
18519 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
18520 if (value < -255 || value > 255)
18521 as_bad_where (fixP->fx_file, fixP->fx_line,
18522 _("co-processor offset out of range"));
18523 value *= 4;
18524 goto cp_off_common;
18525
18526 case BFD_RELOC_ARM_THUMB_OFFSET:
18527 newval = md_chars_to_number (buf, THUMB_SIZE);
18528 /* Exactly what ranges, and where the offset is inserted depends
18529 on the type of instruction, we can establish this from the
18530 top 4 bits. */
18531 switch (newval >> 12)
18532 {
18533 case 4: /* PC load. */
18534 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18535 forced to zero for these loads; md_pcrel_from has already
18536 compensated for this. */
18537 if (value & 3)
18538 as_bad_where (fixP->fx_file, fixP->fx_line,
18539 _("invalid offset, target not word aligned (0x%08lX)"),
18540 (((unsigned long) fixP->fx_frag->fr_address
18541 + (unsigned long) fixP->fx_where) & ~3)
18542 + (unsigned long) value);
18543
18544 if (value & ~0x3fc)
18545 as_bad_where (fixP->fx_file, fixP->fx_line,
18546 _("invalid offset, value too big (0x%08lX)"),
18547 (long) value);
18548
18549 newval |= value >> 2;
18550 break;
18551
18552 case 9: /* SP load/store. */
18553 if (value & ~0x3fc)
18554 as_bad_where (fixP->fx_file, fixP->fx_line,
18555 _("invalid offset, value too big (0x%08lX)"),
18556 (long) value);
18557 newval |= value >> 2;
18558 break;
18559
18560 case 6: /* Word load/store. */
18561 if (value & ~0x7c)
18562 as_bad_where (fixP->fx_file, fixP->fx_line,
18563 _("invalid offset, value too big (0x%08lX)"),
18564 (long) value);
18565 newval |= value << 4; /* 6 - 2. */
18566 break;
18567
18568 case 7: /* Byte load/store. */
18569 if (value & ~0x1f)
18570 as_bad_where (fixP->fx_file, fixP->fx_line,
18571 _("invalid offset, value too big (0x%08lX)"),
18572 (long) value);
18573 newval |= value << 6;
18574 break;
18575
18576 case 8: /* Halfword load/store. */
18577 if (value & ~0x3e)
18578 as_bad_where (fixP->fx_file, fixP->fx_line,
18579 _("invalid offset, value too big (0x%08lX)"),
18580 (long) value);
18581 newval |= value << 5; /* 6 - 1. */
18582 break;
18583
18584 default:
18585 as_bad_where (fixP->fx_file, fixP->fx_line,
18586 "Unable to process relocation for thumb opcode: %lx",
18587 (unsigned long) newval);
18588 break;
18589 }
18590 md_number_to_chars (buf, newval, THUMB_SIZE);
18591 break;
18592
18593 case BFD_RELOC_ARM_THUMB_ADD:
18594 /* This is a complicated relocation, since we use it for all of
18595 the following immediate relocations:
18596
18597 3bit ADD/SUB
18598 8bit ADD/SUB
18599 9bit ADD/SUB SP word-aligned
18600 10bit ADD PC/SP word-aligned
18601
18602 The type of instruction being processed is encoded in the
18603 instruction field:
18604
18605 0x8000 SUB
18606 0x00F0 Rd
18607 0x000F Rs
18608 */
18609 newval = md_chars_to_number (buf, THUMB_SIZE);
18610 {
18611 int rd = (newval >> 4) & 0xf;
18612 int rs = newval & 0xf;
18613 int subtract = !!(newval & 0x8000);
18614
18615 /* Check for HI regs, only very restricted cases allowed:
18616 Adjusting SP, and using PC or SP to get an address. */
18617 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
18618 || (rs > 7 && rs != REG_SP && rs != REG_PC))
18619 as_bad_where (fixP->fx_file, fixP->fx_line,
18620 _("invalid Hi register with immediate"));
18621
18622 /* If value is negative, choose the opposite instruction. */
18623 if (value < 0)
18624 {
18625 value = -value;
18626 subtract = !subtract;
18627 if (value < 0)
18628 as_bad_where (fixP->fx_file, fixP->fx_line,
18629 _("immediate value out of range"));
18630 }
18631
18632 if (rd == REG_SP)
18633 {
18634 if (value & ~0x1fc)
18635 as_bad_where (fixP->fx_file, fixP->fx_line,
18636 _("invalid immediate for stack address calculation"));
18637 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
18638 newval |= value >> 2;
18639 }
18640 else if (rs == REG_PC || rs == REG_SP)
18641 {
18642 if (subtract || value & ~0x3fc)
18643 as_bad_where (fixP->fx_file, fixP->fx_line,
18644 _("invalid immediate for address calculation (value = 0x%08lX)"),
18645 (unsigned long) value);
18646 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
18647 newval |= rd << 8;
18648 newval |= value >> 2;
18649 }
18650 else if (rs == rd)
18651 {
18652 if (value & ~0xff)
18653 as_bad_where (fixP->fx_file, fixP->fx_line,
18654 _("immediate value out of range"));
18655 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
18656 newval |= (rd << 8) | value;
18657 }
18658 else
18659 {
18660 if (value & ~0x7)
18661 as_bad_where (fixP->fx_file, fixP->fx_line,
18662 _("immediate value out of range"));
18663 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
18664 newval |= rd | (rs << 3) | (value << 6);
18665 }
18666 }
18667 md_number_to_chars (buf, newval, THUMB_SIZE);
18668 break;
18669
18670 case BFD_RELOC_ARM_THUMB_IMM:
18671 newval = md_chars_to_number (buf, THUMB_SIZE);
18672 if (value < 0 || value > 255)
18673 as_bad_where (fixP->fx_file, fixP->fx_line,
18674 _("invalid immediate: %ld is too large"),
18675 (long) value);
18676 newval |= value;
18677 md_number_to_chars (buf, newval, THUMB_SIZE);
18678 break;
18679
18680 case BFD_RELOC_ARM_THUMB_SHIFT:
18681 /* 5bit shift value (0..32). LSL cannot take 32. */
18682 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
18683 temp = newval & 0xf800;
18684 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
18685 as_bad_where (fixP->fx_file, fixP->fx_line,
18686 _("invalid shift value: %ld"), (long) value);
18687 /* Shifts of zero must be encoded as LSL. */
18688 if (value == 0)
18689 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
18690 /* Shifts of 32 are encoded as zero. */
18691 else if (value == 32)
18692 value = 0;
18693 newval |= value << 6;
18694 md_number_to_chars (buf, newval, THUMB_SIZE);
18695 break;
18696
18697 case BFD_RELOC_VTABLE_INHERIT:
18698 case BFD_RELOC_VTABLE_ENTRY:
18699 fixP->fx_done = 0;
18700 return;
18701
18702 case BFD_RELOC_ARM_MOVW:
18703 case BFD_RELOC_ARM_MOVT:
18704 case BFD_RELOC_ARM_THUMB_MOVW:
18705 case BFD_RELOC_ARM_THUMB_MOVT:
18706 if (fixP->fx_done || !seg->use_rela_p)
18707 {
18708 /* REL format relocations are limited to a 16-bit addend. */
18709 if (!fixP->fx_done)
18710 {
18711 if (value < -0x1000 || value > 0xffff)
18712 as_bad_where (fixP->fx_file, fixP->fx_line,
18713 _("offset too big"));
18714 }
18715 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
18716 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
18717 {
18718 value >>= 16;
18719 }
18720
18721 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
18722 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
18723 {
18724 newval = get_thumb32_insn (buf);
18725 newval &= 0xfbf08f00;
18726 newval |= (value & 0xf000) << 4;
18727 newval |= (value & 0x0800) << 15;
18728 newval |= (value & 0x0700) << 4;
18729 newval |= (value & 0x00ff);
18730 put_thumb32_insn (buf, newval);
18731 }
18732 else
18733 {
18734 newval = md_chars_to_number (buf, 4);
18735 newval &= 0xfff0f000;
18736 newval |= value & 0x0fff;
18737 newval |= (value & 0xf000) << 4;
18738 md_number_to_chars (buf, newval, 4);
18739 }
18740 }
18741 return;
18742
18743 case BFD_RELOC_ARM_ALU_PC_G0_NC:
18744 case BFD_RELOC_ARM_ALU_PC_G0:
18745 case BFD_RELOC_ARM_ALU_PC_G1_NC:
18746 case BFD_RELOC_ARM_ALU_PC_G1:
18747 case BFD_RELOC_ARM_ALU_PC_G2:
18748 case BFD_RELOC_ARM_ALU_SB_G0_NC:
18749 case BFD_RELOC_ARM_ALU_SB_G0:
18750 case BFD_RELOC_ARM_ALU_SB_G1_NC:
18751 case BFD_RELOC_ARM_ALU_SB_G1:
18752 case BFD_RELOC_ARM_ALU_SB_G2:
18753 assert (!fixP->fx_done);
18754 if (!seg->use_rela_p)
18755 {
18756 bfd_vma insn;
18757 bfd_vma encoded_addend;
18758 bfd_vma addend_abs = abs (value);
18759
18760 /* Check that the absolute value of the addend can be
18761 expressed as an 8-bit constant plus a rotation. */
18762 encoded_addend = encode_arm_immediate (addend_abs);
18763 if (encoded_addend == (unsigned int) FAIL)
18764 as_bad_where (fixP->fx_file, fixP->fx_line,
18765 _("the offset 0x%08lX is not representable"),
18766 (unsigned long) addend_abs);
18767
18768 /* Extract the instruction. */
18769 insn = md_chars_to_number (buf, INSN_SIZE);
18770
18771 /* If the addend is positive, use an ADD instruction.
18772 Otherwise use a SUB. Take care not to destroy the S bit. */
18773 insn &= 0xff1fffff;
18774 if (value < 0)
18775 insn |= 1 << 22;
18776 else
18777 insn |= 1 << 23;
18778
18779 /* Place the encoded addend into the first 12 bits of the
18780 instruction. */
18781 insn &= 0xfffff000;
18782 insn |= encoded_addend;
18783
18784 /* Update the instruction. */
18785 md_number_to_chars (buf, insn, INSN_SIZE);
18786 }
18787 break;
18788
18789 case BFD_RELOC_ARM_LDR_PC_G0:
18790 case BFD_RELOC_ARM_LDR_PC_G1:
18791 case BFD_RELOC_ARM_LDR_PC_G2:
18792 case BFD_RELOC_ARM_LDR_SB_G0:
18793 case BFD_RELOC_ARM_LDR_SB_G1:
18794 case BFD_RELOC_ARM_LDR_SB_G2:
18795 assert (!fixP->fx_done);
18796 if (!seg->use_rela_p)
18797 {
18798 bfd_vma insn;
18799 bfd_vma addend_abs = abs (value);
18800
18801 /* Check that the absolute value of the addend can be
18802 encoded in 12 bits. */
18803 if (addend_abs >= 0x1000)
18804 as_bad_where (fixP->fx_file, fixP->fx_line,
18805 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18806 (unsigned long) addend_abs);
18807
18808 /* Extract the instruction. */
18809 insn = md_chars_to_number (buf, INSN_SIZE);
18810
18811 /* If the addend is negative, clear bit 23 of the instruction.
18812 Otherwise set it. */
18813 if (value < 0)
18814 insn &= ~(1 << 23);
18815 else
18816 insn |= 1 << 23;
18817
18818 /* Place the absolute value of the addend into the first 12 bits
18819 of the instruction. */
18820 insn &= 0xfffff000;
18821 insn |= addend_abs;
18822
18823 /* Update the instruction. */
18824 md_number_to_chars (buf, insn, INSN_SIZE);
18825 }
18826 break;
18827
18828 case BFD_RELOC_ARM_LDRS_PC_G0:
18829 case BFD_RELOC_ARM_LDRS_PC_G1:
18830 case BFD_RELOC_ARM_LDRS_PC_G2:
18831 case BFD_RELOC_ARM_LDRS_SB_G0:
18832 case BFD_RELOC_ARM_LDRS_SB_G1:
18833 case BFD_RELOC_ARM_LDRS_SB_G2:
18834 assert (!fixP->fx_done);
18835 if (!seg->use_rela_p)
18836 {
18837 bfd_vma insn;
18838 bfd_vma addend_abs = abs (value);
18839
18840 /* Check that the absolute value of the addend can be
18841 encoded in 8 bits. */
18842 if (addend_abs >= 0x100)
18843 as_bad_where (fixP->fx_file, fixP->fx_line,
18844 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18845 (unsigned long) addend_abs);
18846
18847 /* Extract the instruction. */
18848 insn = md_chars_to_number (buf, INSN_SIZE);
18849
18850 /* If the addend is negative, clear bit 23 of the instruction.
18851 Otherwise set it. */
18852 if (value < 0)
18853 insn &= ~(1 << 23);
18854 else
18855 insn |= 1 << 23;
18856
18857 /* Place the first four bits of the absolute value of the addend
18858 into the first 4 bits of the instruction, and the remaining
18859 four into bits 8 .. 11. */
18860 insn &= 0xfffff0f0;
18861 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
18862
18863 /* Update the instruction. */
18864 md_number_to_chars (buf, insn, INSN_SIZE);
18865 }
18866 break;
18867
18868 case BFD_RELOC_ARM_LDC_PC_G0:
18869 case BFD_RELOC_ARM_LDC_PC_G1:
18870 case BFD_RELOC_ARM_LDC_PC_G2:
18871 case BFD_RELOC_ARM_LDC_SB_G0:
18872 case BFD_RELOC_ARM_LDC_SB_G1:
18873 case BFD_RELOC_ARM_LDC_SB_G2:
18874 assert (!fixP->fx_done);
18875 if (!seg->use_rela_p)
18876 {
18877 bfd_vma insn;
18878 bfd_vma addend_abs = abs (value);
18879
18880 /* Check that the absolute value of the addend is a multiple of
18881 four and, when divided by four, fits in 8 bits. */
18882 if (addend_abs & 0x3)
18883 as_bad_where (fixP->fx_file, fixP->fx_line,
18884 _("bad offset 0x%08lX (must be word-aligned)"),
18885 (unsigned long) addend_abs);
18886
18887 if ((addend_abs >> 2) > 0xff)
18888 as_bad_where (fixP->fx_file, fixP->fx_line,
18889 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18890 (unsigned long) addend_abs);
18891
18892 /* Extract the instruction. */
18893 insn = md_chars_to_number (buf, INSN_SIZE);
18894
18895 /* If the addend is negative, clear bit 23 of the instruction.
18896 Otherwise set it. */
18897 if (value < 0)
18898 insn &= ~(1 << 23);
18899 else
18900 insn |= 1 << 23;
18901
18902 /* Place the addend (divided by four) into the first eight
18903 bits of the instruction. */
18904 insn &= 0xfffffff0;
18905 insn |= addend_abs >> 2;
18906
18907 /* Update the instruction. */
18908 md_number_to_chars (buf, insn, INSN_SIZE);
18909 }
18910 break;
18911
18912 case BFD_RELOC_UNUSED:
18913 default:
18914 as_bad_where (fixP->fx_file, fixP->fx_line,
18915 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
18916 }
18917}
18918
18919/* Translate internal representation of relocation info to BFD target
18920 format. */
18921
18922arelent *
18923tc_gen_reloc (asection *section, fixS *fixp)
18924{
18925 arelent * reloc;
18926 bfd_reloc_code_real_type code;
18927
18928 reloc = xmalloc (sizeof (arelent));
18929
18930 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
18931 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
18932 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
18933
18934 if (fixp->fx_pcrel)
18935 {
18936 if (section->use_rela_p)
18937 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
18938 else
18939 fixp->fx_offset = reloc->address;
18940 }
18941 reloc->addend = fixp->fx_offset;
18942
18943 switch (fixp->fx_r_type)
18944 {
18945 case BFD_RELOC_8:
18946 if (fixp->fx_pcrel)
18947 {
18948 code = BFD_RELOC_8_PCREL;
18949 break;
18950 }
18951
18952 case BFD_RELOC_16:
18953 if (fixp->fx_pcrel)
18954 {
18955 code = BFD_RELOC_16_PCREL;
18956 break;
18957 }
18958
18959 case BFD_RELOC_32:
18960 if (fixp->fx_pcrel)
18961 {
18962 code = BFD_RELOC_32_PCREL;
18963 break;
18964 }
18965
18966 case BFD_RELOC_ARM_MOVW:
18967 if (fixp->fx_pcrel)
18968 {
18969 code = BFD_RELOC_ARM_MOVW_PCREL;
18970 break;
18971 }
18972
18973 case BFD_RELOC_ARM_MOVT:
18974 if (fixp->fx_pcrel)
18975 {
18976 code = BFD_RELOC_ARM_MOVT_PCREL;
18977 break;
18978 }
18979
18980 case BFD_RELOC_ARM_THUMB_MOVW:
18981 if (fixp->fx_pcrel)
18982 {
18983 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
18984 break;
18985 }
18986
18987 case BFD_RELOC_ARM_THUMB_MOVT:
18988 if (fixp->fx_pcrel)
18989 {
18990 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
18991 break;
18992 }
18993
18994 case BFD_RELOC_NONE:
18995 case BFD_RELOC_ARM_PCREL_BRANCH:
18996 case BFD_RELOC_ARM_PCREL_BLX:
18997 case BFD_RELOC_RVA:
18998 case BFD_RELOC_THUMB_PCREL_BRANCH7:
18999 case BFD_RELOC_THUMB_PCREL_BRANCH9:
19000 case BFD_RELOC_THUMB_PCREL_BRANCH12:
19001 case BFD_RELOC_THUMB_PCREL_BRANCH20:
19002 case BFD_RELOC_THUMB_PCREL_BRANCH23:
19003 case BFD_RELOC_THUMB_PCREL_BRANCH25:
19004 case BFD_RELOC_THUMB_PCREL_BLX:
19005 case BFD_RELOC_VTABLE_ENTRY:
19006 case BFD_RELOC_VTABLE_INHERIT:
19007#ifdef TE_PE
19008 case BFD_RELOC_32_SECREL:
19009#endif
19010 code = fixp->fx_r_type;
19011 break;
19012
19013 case BFD_RELOC_ARM_LITERAL:
19014 case BFD_RELOC_ARM_HWLITERAL:
19015 /* If this is called then the a literal has
19016 been referenced across a section boundary. */
19017 as_bad_where (fixp->fx_file, fixp->fx_line,
19018 _("literal referenced across section boundary"));
19019 return NULL;
19020
19021#ifdef OBJ_ELF
19022 case BFD_RELOC_ARM_GOT32:
19023 case BFD_RELOC_ARM_GOTOFF:
19024 case BFD_RELOC_ARM_PLT32:
19025 case BFD_RELOC_ARM_TARGET1:
19026 case BFD_RELOC_ARM_ROSEGREL32:
19027 case BFD_RELOC_ARM_SBREL32:
19028 case BFD_RELOC_ARM_PREL31:
19029 case BFD_RELOC_ARM_TARGET2:
19030 case BFD_RELOC_ARM_TLS_LE32:
19031 case BFD_RELOC_ARM_TLS_LDO32:
19032 case BFD_RELOC_ARM_PCREL_CALL:
19033 case BFD_RELOC_ARM_PCREL_JUMP:
19034 case BFD_RELOC_ARM_ALU_PC_G0_NC:
19035 case BFD_RELOC_ARM_ALU_PC_G0:
19036 case BFD_RELOC_ARM_ALU_PC_G1_NC:
19037 case BFD_RELOC_ARM_ALU_PC_G1:
19038 case BFD_RELOC_ARM_ALU_PC_G2:
19039 case BFD_RELOC_ARM_LDR_PC_G0:
19040 case BFD_RELOC_ARM_LDR_PC_G1:
19041 case BFD_RELOC_ARM_LDR_PC_G2:
19042 case BFD_RELOC_ARM_LDRS_PC_G0:
19043 case BFD_RELOC_ARM_LDRS_PC_G1:
19044 case BFD_RELOC_ARM_LDRS_PC_G2:
19045 case BFD_RELOC_ARM_LDC_PC_G0:
19046 case BFD_RELOC_ARM_LDC_PC_G1:
19047 case BFD_RELOC_ARM_LDC_PC_G2:
19048 case BFD_RELOC_ARM_ALU_SB_G0_NC:
19049 case BFD_RELOC_ARM_ALU_SB_G0:
19050 case BFD_RELOC_ARM_ALU_SB_G1_NC:
19051 case BFD_RELOC_ARM_ALU_SB_G1:
19052 case BFD_RELOC_ARM_ALU_SB_G2:
19053 case BFD_RELOC_ARM_LDR_SB_G0:
19054 case BFD_RELOC_ARM_LDR_SB_G1:
19055 case BFD_RELOC_ARM_LDR_SB_G2:
19056 case BFD_RELOC_ARM_LDRS_SB_G0:
19057 case BFD_RELOC_ARM_LDRS_SB_G1:
19058 case BFD_RELOC_ARM_LDRS_SB_G2:
19059 case BFD_RELOC_ARM_LDC_SB_G0:
19060 case BFD_RELOC_ARM_LDC_SB_G1:
19061 case BFD_RELOC_ARM_LDC_SB_G2:
19062 code = fixp->fx_r_type;
19063 break;
19064
19065 case BFD_RELOC_ARM_TLS_GD32:
19066 case BFD_RELOC_ARM_TLS_IE32:
19067 case BFD_RELOC_ARM_TLS_LDM32:
19068 /* BFD will include the symbol's address in the addend.
19069 But we don't want that, so subtract it out again here. */
19070 if (!S_IS_COMMON (fixp->fx_addsy))
19071 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
19072 code = fixp->fx_r_type;
19073 break;
19074#endif
19075
19076 case BFD_RELOC_ARM_IMMEDIATE:
19077 as_bad_where (fixp->fx_file, fixp->fx_line,
19078 _("internal relocation (type: IMMEDIATE) not fixed up"));
19079 return NULL;
19080
19081 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
19082 as_bad_where (fixp->fx_file, fixp->fx_line,
19083 _("ADRL used for a symbol not defined in the same file"));
19084 return NULL;
19085
19086 case BFD_RELOC_ARM_OFFSET_IMM:
19087 if (section->use_rela_p)
19088 {
19089 code = fixp->fx_r_type;
19090 break;
19091 }
19092
19093 if (fixp->fx_addsy != NULL
19094 && !S_IS_DEFINED (fixp->fx_addsy)
19095 && S_IS_LOCAL (fixp->fx_addsy))
19096 {
19097 as_bad_where (fixp->fx_file, fixp->fx_line,
19098 _("undefined local label `%s'"),
19099 S_GET_NAME (fixp->fx_addsy));
19100 return NULL;
19101 }
19102
19103 as_bad_where (fixp->fx_file, fixp->fx_line,
19104 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19105 return NULL;
19106
19107 default:
19108 {
19109 char * type;
19110
19111 switch (fixp->fx_r_type)
19112 {
19113 case BFD_RELOC_NONE: type = "NONE"; break;
19114 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
19115 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
19116 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
19117 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
19118 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
19119 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
19120 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
19121 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
19122 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
19123 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
19124 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
19125 default: type = _("<unknown>"); break;
19126 }
19127 as_bad_where (fixp->fx_file, fixp->fx_line,
19128 _("cannot represent %s relocation in this object file format"),
19129 type);
19130 return NULL;
19131 }
19132 }
19133
19134#ifdef OBJ_ELF
19135 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
19136 && GOT_symbol
19137 && fixp->fx_addsy == GOT_symbol)
19138 {
19139 code = BFD_RELOC_ARM_GOTPC;
19140 reloc->addend = fixp->fx_offset = reloc->address;
19141 }
19142#endif
19143
19144 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
19145
19146 if (reloc->howto == NULL)
19147 {
19148 as_bad_where (fixp->fx_file, fixp->fx_line,
19149 _("cannot represent %s relocation in this object file format"),
19150 bfd_get_reloc_code_name (code));
19151 return NULL;
19152 }
19153
19154 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
19155 vtable entry to be used in the relocation's section offset. */
19156 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
19157 reloc->address = fixp->fx_offset;
19158
19159 return reloc;
19160}
19161
19162/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
19163
19164void
19165cons_fix_new_arm (fragS * frag,
19166 int where,
19167 int size,
19168 expressionS * exp)
19169{
19170 bfd_reloc_code_real_type type;
19171 int pcrel = 0;
19172
19173 /* Pick a reloc.
19174 FIXME: @@ Should look at CPU word size. */
19175 switch (size)
19176 {
19177 case 1:
19178 type = BFD_RELOC_8;
19179 break;
19180 case 2:
19181 type = BFD_RELOC_16;
19182 break;
19183 case 4:
19184 default:
19185 type = BFD_RELOC_32;
19186 break;
19187 case 8:
19188 type = BFD_RELOC_64;
19189 break;
19190 }
19191
19192#ifdef TE_PE
19193 if (exp->X_op == O_secrel)
19194 {
19195 exp->X_op = O_symbol;
19196 type = BFD_RELOC_32_SECREL;
19197 }
19198#endif
19199
19200 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
19201}
19202
19203#if defined OBJ_COFF || defined OBJ_ELF
19204void
19205arm_validate_fix (fixS * fixP)
19206{
19207 /* If the destination of the branch is a defined symbol which does not have
19208 the THUMB_FUNC attribute, then we must be calling a function which has
19209 the (interfacearm) attribute. We look for the Thumb entry point to that
19210 function and change the branch to refer to that function instead. */
19211 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
19212 && fixP->fx_addsy != NULL
19213 && S_IS_DEFINED (fixP->fx_addsy)
19214 && ! THUMB_IS_FUNC (fixP->fx_addsy))
19215 {
19216 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
19217 }
19218}
19219#endif
19220
19221int
19222arm_force_relocation (struct fix * fixp)
19223{
19224#if defined (OBJ_COFF) && defined (TE_PE)
19225 if (fixp->fx_r_type == BFD_RELOC_RVA)
19226 return 1;
19227#endif
19228
19229 /* Resolve these relocations even if the symbol is extern or weak. */
19230 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
19231 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
19232 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
19233 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
19234 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
19235 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
19236 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12)
19237 return 0;
19238
19239 /* Always leave these relocations for the linker. */
19240 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
19241 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
19242 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
19243 return 1;
19244
19245 /* Always generate relocations against function symbols. */
19246 if (fixp->fx_r_type == BFD_RELOC_32
19247 && fixp->fx_addsy
19248 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
19249 return 1;
19250
19251 return generic_force_reloc (fixp);
19252}
19253
19254#if defined (OBJ_ELF) || defined (OBJ_COFF)
19255/* Relocations against function names must be left unadjusted,
19256 so that the linker can use this information to generate interworking
19257 stubs. The MIPS version of this function
19258 also prevents relocations that are mips-16 specific, but I do not
19259 know why it does this.
19260
19261 FIXME:
19262 There is one other problem that ought to be addressed here, but
19263 which currently is not: Taking the address of a label (rather
19264 than a function) and then later jumping to that address. Such
19265 addresses also ought to have their bottom bit set (assuming that
19266 they reside in Thumb code), but at the moment they will not. */
19267
19268bfd_boolean
19269arm_fix_adjustable (fixS * fixP)
19270{
19271 if (fixP->fx_addsy == NULL)
19272 return 1;
19273
19274 /* Preserve relocations against symbols with function type. */
19275 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
19276 return 0;
19277
19278 if (THUMB_IS_FUNC (fixP->fx_addsy)
19279 && fixP->fx_subsy == NULL)
19280 return 0;
19281
19282 /* We need the symbol name for the VTABLE entries. */
19283 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
19284 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
19285 return 0;
19286
19287 /* Don't allow symbols to be discarded on GOT related relocs. */
19288 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
19289 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
19290 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
19291 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
19292 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
19293 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
19294 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
19295 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
19296 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
19297 return 0;
19298
19299 /* Similarly for group relocations. */
19300 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
19301 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
19302 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
19303 return 0;
19304
19305 return 1;
19306}
19307#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
19308
19309#ifdef OBJ_ELF
19310
19311const char *
19312elf32_arm_target_format (void)
19313{
19314#ifdef TE_SYMBIAN
19315 return (target_big_endian
19316 ? "elf32-bigarm-symbian"
19317 : "elf32-littlearm-symbian");
19318#elif defined (TE_VXWORKS)
19319 return (target_big_endian
19320 ? "elf32-bigarm-vxworks"
19321 : "elf32-littlearm-vxworks");
19322#else
19323 if (target_big_endian)
19324 return "elf32-bigarm";
19325 else
19326 return "elf32-littlearm";
19327#endif
19328}
19329
19330void
19331armelf_frob_symbol (symbolS * symp,
19332 int * puntp)
19333{
19334 elf_frob_symbol (symp, puntp);
19335}
19336#endif
19337
19338/* MD interface: Finalization. */
19339
19340/* A good place to do this, although this was probably not intended
19341 for this kind of use. We need to dump the literal pool before
19342 references are made to a null symbol pointer. */
19343
19344void
19345arm_cleanup (void)
19346{
19347 literal_pool * pool;
19348
19349 for (pool = list_of_pools; pool; pool = pool->next)
19350 {
19351 /* Put it at the end of the relevent section. */
19352 subseg_set (pool->section, pool->sub_section);
19353#ifdef OBJ_ELF
19354 arm_elf_change_section ();
19355#endif
19356 s_ltorg (0);
19357 }
19358}
19359
19360/* Adjust the symbol table. This marks Thumb symbols as distinct from
19361 ARM ones. */
19362
19363void
19364arm_adjust_symtab (void)
19365{
19366#ifdef OBJ_COFF
19367 symbolS * sym;
19368
19369 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
19370 {
19371 if (ARM_IS_THUMB (sym))
19372 {
19373 if (THUMB_IS_FUNC (sym))
19374 {
19375 /* Mark the symbol as a Thumb function. */
19376 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
19377 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
19378 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
19379
19380 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
19381 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
19382 else
19383 as_bad (_("%s: unexpected function type: %d"),
19384 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
19385 }
19386 else switch (S_GET_STORAGE_CLASS (sym))
19387 {
19388 case C_EXT:
19389 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
19390 break;
19391 case C_STAT:
19392 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
19393 break;
19394 case C_LABEL:
19395 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
19396 break;
19397 default:
19398 /* Do nothing. */
19399 break;
19400 }
19401 }
19402
19403 if (ARM_IS_INTERWORK (sym))
19404 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
19405 }
19406#endif
19407#ifdef OBJ_ELF
19408 symbolS * sym;
19409 char bind;
19410
19411 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
19412 {
19413 if (ARM_IS_THUMB (sym))
19414 {
19415 elf_symbol_type * elf_sym;
19416
19417 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
19418 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
19419
19420 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
19421 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
19422 {
19423 /* If it's a .thumb_func, declare it as so,
19424 otherwise tag label as .code 16. */
19425 if (THUMB_IS_FUNC (sym))
19426 elf_sym->internal_elf_sym.st_info =
19427 ELF_ST_INFO (bind, STT_ARM_TFUNC);
19428 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
19429 elf_sym->internal_elf_sym.st_info =
19430 ELF_ST_INFO (bind, STT_ARM_16BIT);
19431 }
19432 }
19433 }
19434#endif
19435}
19436
19437/* MD interface: Initialization. */
19438
19439static void
19440set_constant_flonums (void)
19441{
19442 int i;
19443
19444 for (i = 0; i < NUM_FLOAT_VALS; i++)
19445 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
19446 abort ();
19447}
19448
19449/* Auto-select Thumb mode if it's the only available instruction set for the
19450 given architecture. */
19451
19452static void
19453autoselect_thumb_from_cpu_variant (void)
19454{
19455 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
19456 opcode_select (16);
19457}
19458
19459void
19460md_begin (void)
19461{
19462 unsigned mach;
19463 unsigned int i;
19464
19465 if ( (arm_ops_hsh = hash_new ()) == NULL
19466 || (arm_cond_hsh = hash_new ()) == NULL
19467 || (arm_shift_hsh = hash_new ()) == NULL
19468 || (arm_psr_hsh = hash_new ()) == NULL
19469 || (arm_v7m_psr_hsh = hash_new ()) == NULL
19470 || (arm_reg_hsh = hash_new ()) == NULL
19471 || (arm_reloc_hsh = hash_new ()) == NULL
19472 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
19473 as_fatal (_("virtual memory exhausted"));
19474
19475 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
19476 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
19477 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
19478 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
19479 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
19480 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
19481 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
19482 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
19483 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
19484 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template, (PTR) (v7m_psrs + i));
19485 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
19486 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i));
19487 for (i = 0;
19488 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
19489 i++)
19490 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template,
19491 (PTR) (barrier_opt_names + i));
19492#ifdef OBJ_ELF
19493 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
19494 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i));
19495#endif
19496
19497 set_constant_flonums ();
19498
19499 /* Set the cpu variant based on the command-line options. We prefer
19500 -mcpu= over -march= if both are set (as for GCC); and we prefer
19501 -mfpu= over any other way of setting the floating point unit.
19502 Use of legacy options with new options are faulted. */
19503 if (legacy_cpu)
19504 {
19505 if (mcpu_cpu_opt || march_cpu_opt)
19506 as_bad (_("use of old and new-style options to set CPU type"));
19507
19508 mcpu_cpu_opt = legacy_cpu;
19509 }
19510 else if (!mcpu_cpu_opt)
19511 mcpu_cpu_opt = march_cpu_opt;
19512
19513 if (legacy_fpu)
19514 {
19515 if (mfpu_opt)
19516 as_bad (_("use of old and new-style options to set FPU type"));
19517
19518 mfpu_opt = legacy_fpu;
19519 }
19520 else if (!mfpu_opt)
19521 {
19522#if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19523 /* Some environments specify a default FPU. If they don't, infer it
19524 from the processor. */
19525 if (mcpu_fpu_opt)
19526 mfpu_opt = mcpu_fpu_opt;
19527 else
19528 mfpu_opt = march_fpu_opt;
19529#else
19530 mfpu_opt = &fpu_default;
19531#endif
19532 }
19533
19534 if (!mfpu_opt)
19535 {
19536 if (mcpu_cpu_opt != NULL)
19537 mfpu_opt = &fpu_default;
19538 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
19539 mfpu_opt = &fpu_arch_vfp_v2;
19540 else
19541 mfpu_opt = &fpu_arch_fpa;
19542 }
19543
19544#ifdef CPU_DEFAULT
19545 if (!mcpu_cpu_opt)
19546 {
19547 mcpu_cpu_opt = &cpu_default;
19548 selected_cpu = cpu_default;
19549 }
19550#else
19551 if (mcpu_cpu_opt)
19552 selected_cpu = *mcpu_cpu_opt;
19553 else
19554 mcpu_cpu_opt = &arm_arch_any;
19555#endif
19556
19557 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
19558
19559 autoselect_thumb_from_cpu_variant ();
19560
19561 arm_arch_used = thumb_arch_used = arm_arch_none;
19562
19563#if defined OBJ_COFF || defined OBJ_ELF
19564 {
19565 unsigned int flags = 0;
19566
19567#if defined OBJ_ELF
19568 flags = meabi_flags;
19569
19570 switch (meabi_flags)
19571 {
19572 case EF_ARM_EABI_UNKNOWN:
19573#endif
19574 /* Set the flags in the private structure. */
19575 if (uses_apcs_26) flags |= F_APCS26;
19576 if (support_interwork) flags |= F_INTERWORK;
19577 if (uses_apcs_float) flags |= F_APCS_FLOAT;
19578 if (pic_code) flags |= F_PIC;
19579 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
19580 flags |= F_SOFT_FLOAT;
19581
19582 switch (mfloat_abi_opt)
19583 {
19584 case ARM_FLOAT_ABI_SOFT:
19585 case ARM_FLOAT_ABI_SOFTFP:
19586 flags |= F_SOFT_FLOAT;
19587 break;
19588
19589 case ARM_FLOAT_ABI_HARD:
19590 if (flags & F_SOFT_FLOAT)
19591 as_bad (_("hard-float conflicts with specified fpu"));
19592 break;
19593 }
19594
19595 /* Using pure-endian doubles (even if soft-float). */
19596 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
19597 flags |= F_VFP_FLOAT;
19598
19599#if defined OBJ_ELF
19600 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
19601 flags |= EF_ARM_MAVERICK_FLOAT;
19602 break;
19603
19604 case EF_ARM_EABI_VER4:
19605 case EF_ARM_EABI_VER5:
19606 /* No additional flags to set. */
19607 break;
19608
19609 default:
19610 abort ();
19611 }
19612#endif
19613 bfd_set_private_flags (stdoutput, flags);
19614
19615 /* We have run out flags in the COFF header to encode the
19616 status of ATPCS support, so instead we create a dummy,
19617 empty, debug section called .arm.atpcs. */
19618 if (atpcs)
19619 {
19620 asection * sec;
19621
19622 sec = bfd_make_section (stdoutput, ".arm.atpcs");
19623
19624 if (sec != NULL)
19625 {
19626 bfd_set_section_flags
19627 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
19628 bfd_set_section_size (stdoutput, sec, 0);
19629 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
19630 }
19631 }
19632 }
19633#endif
19634
19635 /* Record the CPU type as well. */
19636 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
19637 mach = bfd_mach_arm_iWMMXt2;
19638 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
19639 mach = bfd_mach_arm_iWMMXt;
19640 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
19641 mach = bfd_mach_arm_XScale;
19642 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
19643 mach = bfd_mach_arm_ep9312;
19644 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
19645 mach = bfd_mach_arm_5TE;
19646 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
19647 {
19648 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
19649 mach = bfd_mach_arm_5T;
19650 else
19651 mach = bfd_mach_arm_5;
19652 }
19653 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
19654 {
19655 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
19656 mach = bfd_mach_arm_4T;
19657 else
19658 mach = bfd_mach_arm_4;
19659 }
19660 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
19661 mach = bfd_mach_arm_3M;
19662 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
19663 mach = bfd_mach_arm_3;
19664 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
19665 mach = bfd_mach_arm_2a;
19666 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
19667 mach = bfd_mach_arm_2;
19668 else
19669 mach = bfd_mach_arm_unknown;
19670
19671 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
19672}
19673
19674/* Command line processing. */
19675
19676/* md_parse_option
19677 Invocation line includes a switch not recognized by the base assembler.
19678 See if it's a processor-specific option.
19679
19680 This routine is somewhat complicated by the need for backwards
19681 compatibility (since older releases of gcc can't be changed).
19682 The new options try to make the interface as compatible as
19683 possible with GCC.
19684
19685 New options (supported) are:
19686
19687 -mcpu=<cpu name> Assemble for selected processor
19688 -march=<architecture name> Assemble for selected architecture
19689 -mfpu=<fpu architecture> Assemble for selected FPU.
19690 -EB/-mbig-endian Big-endian
19691 -EL/-mlittle-endian Little-endian
19692 -k Generate PIC code
19693 -mthumb Start in Thumb mode
19694 -mthumb-interwork Code supports ARM/Thumb interworking
19695
19696 For now we will also provide support for:
19697
19698 -mapcs-32 32-bit Program counter
19699 -mapcs-26 26-bit Program counter
19700 -macps-float Floats passed in FP registers
19701 -mapcs-reentrant Reentrant code
19702 -matpcs
19703 (sometime these will probably be replaced with -mapcs=<list of options>
19704 and -matpcs=<list of options>)
19705
19706 The remaining options are only supported for back-wards compatibility.
19707 Cpu variants, the arm part is optional:
19708 -m[arm]1 Currently not supported.
19709 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19710 -m[arm]3 Arm 3 processor
19711 -m[arm]6[xx], Arm 6 processors
19712 -m[arm]7[xx][t][[d]m] Arm 7 processors
19713 -m[arm]8[10] Arm 8 processors
19714 -m[arm]9[20][tdmi] Arm 9 processors
19715 -mstrongarm[110[0]] StrongARM processors
19716 -mxscale XScale processors
19717 -m[arm]v[2345[t[e]]] Arm architectures
19718 -mall All (except the ARM1)
19719 FP variants:
19720 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19721 -mfpe-old (No float load/store multiples)
19722 -mvfpxd VFP Single precision
19723 -mvfp All VFP
19724 -mno-fpu Disable all floating point instructions
19725
19726 The following CPU names are recognized:
19727 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19728 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19729 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19730 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19731 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19732 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19733 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19734
19735 */
19736
19737const char * md_shortopts = "m:k";
19738
19739#ifdef ARM_BI_ENDIAN
19740#define OPTION_EB (OPTION_MD_BASE + 0)
19741#define OPTION_EL (OPTION_MD_BASE + 1)
19742#else
19743#if TARGET_BYTES_BIG_ENDIAN
19744#define OPTION_EB (OPTION_MD_BASE + 0)
19745#else
19746#define OPTION_EL (OPTION_MD_BASE + 1)
19747#endif
19748#endif
19749
19750struct option md_longopts[] =
19751{
19752#ifdef OPTION_EB
19753 {"EB", no_argument, NULL, OPTION_EB},
19754#endif
19755#ifdef OPTION_EL
19756 {"EL", no_argument, NULL, OPTION_EL},
19757#endif
19758 {NULL, no_argument, NULL, 0}
19759};
19760
19761size_t md_longopts_size = sizeof (md_longopts);
19762
19763struct arm_option_table
19764{
19765 char *option; /* Option name to match. */
19766 char *help; /* Help information. */
19767 int *var; /* Variable to change. */
19768 int value; /* What to change it to. */
19769 char *deprecated; /* If non-null, print this message. */
19770};
19771
19772struct arm_option_table arm_opts[] =
19773{
19774 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
19775 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
19776 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19777 &support_interwork, 1, NULL},
19778 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
19779 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
19780 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
19781 1, NULL},
19782 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
19783 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
19784 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
19785 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
19786 NULL},
19787
19788 /* These are recognized by the assembler, but have no affect on code. */
19789 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
19790 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
19791 {NULL, NULL, NULL, 0, NULL}
19792};
19793
19794struct arm_legacy_option_table
19795{
19796 char *option; /* Option name to match. */
19797 const arm_feature_set **var; /* Variable to change. */
19798 const arm_feature_set value; /* What to change it to. */
19799 char *deprecated; /* If non-null, print this message. */
19800};
19801
19802const struct arm_legacy_option_table arm_legacy_opts[] =
19803{
19804 /* DON'T add any new processors to this list -- we want the whole list
19805 to go away... Add them to the processors table instead. */
19806 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
19807 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
19808 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
19809 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
19810 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
19811 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
19812 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
19813 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
19814 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
19815 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
19816 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
19817 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
19818 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
19819 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
19820 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
19821 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
19822 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
19823 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
19824 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
19825 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
19826 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
19827 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
19828 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
19829 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
19830 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
19831 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
19832 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
19833 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
19834 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
19835 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
19836 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
19837 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
19838 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
19839 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
19840 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
19841 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
19842 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
19843 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
19844 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
19845 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
19846 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
19847 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
19848 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
19849 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
19850 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
19851 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
19852 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19853 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19854 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19855 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19856 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
19857 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
19858 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
19859 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
19860 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
19861 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
19862 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
19863 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
19864 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
19865 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
19866 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
19867 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
19868 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
19869 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
19870 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
19871 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
19872 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
19873 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
19874 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
19875 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
19876 N_("use -mcpu=strongarm110")},
19877 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
19878 N_("use -mcpu=strongarm1100")},
19879 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
19880 N_("use -mcpu=strongarm1110")},
19881 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
19882 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
19883 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
19884
19885 /* Architecture variants -- don't add any more to this list either. */
19886 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
19887 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
19888 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
19889 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
19890 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
19891 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
19892 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
19893 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
19894 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
19895 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
19896 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
19897 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
19898 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
19899 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
19900 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
19901 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
19902 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
19903 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
19904
19905 /* Floating point variants -- don't add any more to this list either. */
19906 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
19907 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
19908 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
19909 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
19910 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
19911
19912 {NULL, NULL, ARM_ARCH_NONE, NULL}
19913};
19914
19915struct arm_cpu_option_table
19916{
19917 char *name;
19918 const arm_feature_set value;
19919 /* For some CPUs we assume an FPU unless the user explicitly sets
19920 -mfpu=... */
19921 const arm_feature_set default_fpu;
19922 /* The canonical name of the CPU, or NULL to use NAME converted to upper
19923 case. */
19924 const char *canonical_name;
19925};
19926
19927/* This list should, at a minimum, contain all the cpu names
19928 recognized by GCC. */
19929static const struct arm_cpu_option_table arm_cpus[] =
19930{
19931 {"all", ARM_ANY, FPU_ARCH_FPA, NULL},
19932 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL},
19933 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL},
19934 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
19935 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
19936 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19937 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19938 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19939 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19940 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19941 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19942 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
19943 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19944 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
19945 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19946 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
19947 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19948 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19949 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19950 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19951 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19952 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19953 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19954 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19955 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19956 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19957 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19958 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
19959 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19960 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19961 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19962 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
19963 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
19964 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
19965 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
19966 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
19967 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
19968 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
19969 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19970 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"},
19971 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19972 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19973 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19974 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
19975 /* For V5 or later processors we default to using VFP; but the user
19976 should really set the FPU type explicitly. */
19977 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
19978 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
19979 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
19980 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
19981 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
19982 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
19983 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"},
19984 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
19985 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
19986 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"},
19987 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
19988 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
19989 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
19990 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
19991 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
19992 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"},
19993 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
19994 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
19995 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
19996 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
19997 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
19998 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"},
19999 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL},
20000 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"},
20001 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL},
20002 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL},
20003 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL},
20004 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL},
20005 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
20006 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
20007 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
20008 {"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3
20009 | FPU_NEON_EXT_V1),
20010 NULL},
|